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thebeekeep |
-- here's the whole thing
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-- on 22 mar i did something strange. i took the pc off the clock and made it
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-- transition on the signal next_instr from the control unit. that way, the
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-- states will get the correct instruction
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library ieee;
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use ieee.std_logic_1164.all;
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entity cowgirl is
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port (
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clk : in std_logic; -- system clock
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reset : in std_logic; -- system reset
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to_ram : out std_logic_vector(15 downto 0)); -- write to RAM
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end cowgirl;
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architecture cowgirl_arch of cowgirl is
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component alu
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port (
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a : in std_logic_vector(15 downto 0);
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b : in std_logic_vector(15 downto 0);
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a_or_l : in std_logic;
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op : in std_logic_vector(2 downto 0);
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o : out std_logic_vector(15 downto 0));
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end component;
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component pc
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port (
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reset : in std_logic;
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clk : in std_logic;
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load : in std_logic;
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d : in std_logic_vector(15 downto 0);
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c : out std_logic_vector(15 downto 0));
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end component;
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component registers
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port (
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d : in std_logic_vector(15 downto 0);
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clk : in std_logic;
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addr_a : in std_logic_vector(2 downto 0);
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addr_b : in std_logic_vector(2 downto 0);
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wr_en : in std_logic;
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a_o : out std_logic_vector(15 downto 0);
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b_o : out std_logic_vector(15 downto 0));
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end component;
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component shifter
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port (
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n_shift : in std_logic_vector(7 downto 0);
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sh_type : in std_logic_vector(1 downto 0);
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data : in std_logic_vector(15 downto 0);
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o : out std_logic_vector(15 downto 0));
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end component;
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component control
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port (
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instr : in std_logic_vector(15 downto 0);
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clk : in std_logic;
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reset : in std_logic;
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mem_ready : in std_logic;
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a_or_l : out std_logic;
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op : out std_logic_vector(2 downto 0);
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addr_a : out std_logic_vector(2 downto 0);
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addr_b : out std_logic_vector(2 downto 0);
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reg_addr : out std_logic_vector(2 downto 0);
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to_regs : out std_logic_vector(15 downto 0);
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to_pc : out std_logic_vector(15 downto 0);
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load_pc : out std_logic;
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reg_wr : out std_logic;
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alu_or_imm: out std_logic;
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next_instr: out std_logic;
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curr_state: out std_logic_vector(15 downto 0));
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end component;
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component mux_2_1
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port (
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a : in std_logic_vector(15 downto 0);
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b : in std_logic_vector(15 downto 0);
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sel : in std_logic;
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o : out std_logic_vector(15 downto 0));
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end component;
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component prog_rom
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port (
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input : in std_logic_vector(15 downto 0);
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output : out std_logic_vector(15 downto 0));
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end component;
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-- here are my internal signals
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signal reg_a_out, reg_b_out, alu_out, pc_to_rom, rom_out, immediate, reg_val : std_logic_vector(15 downto 0);
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signal control_to_pc, curr_state : std_logic_vector(15 downto 0);
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signal address_a, address_b, alu_opcode, reg_wr_addr : std_logic_vector(2 downto 0);
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signal write_regs, a_or_l, load_pc, mem_ready, alu_or_imm, pc_clock : std_logic;
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begin -- cowgirl_arch
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regs: registers
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port map (d => reg_val, clk => clk, addr_a => address_a, addr_b => address_b, wr_en => write_regs, a_o => reg_a_out, b_o => reg_b_out);
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abacus: alu
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port map (reg_a_out, reg_b_out, a_or_l, alu_opcode, alu_out);
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program_counter: pc
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port map (reset, pc_clock, load_pc, reg_a_out, pc_to_rom);
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program_rom: prog_rom
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port map (pc_to_rom, rom_out);
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reg_mux: mux_2_1
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port map (alu_out, immediate, alu_or_imm, reg_val);
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brain: control
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port map (rom_out, clk, reset, mem_ready, a_or_l, alu_opcode, address_a, address_b, reg_wr_addr, immediate, control_to_pc, load_pc, write_regs, alu_or_imm, pc_clock, curr_state);
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end cowgirl_arch;
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