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[/] [cowgirl/] [trunk/] [regsiters.vhdl] - Blame information for rev 4

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-- 10/24/2005
-- General Purpose Register Bank
 
library ieee;
use ieee.std_logic_1164.all;
 
entity registers is port(
        d:      in std_logic_vector(15 downto 0);
        clk:    in std_logic;
        addr_a: in std_logic_vector(2 downto 0);
        addr_b: in std_logic_vector(2 downto 0);
        wr_en:  in std_logic;
        a_o:    out std_logic_vector(15 downto 0);
        b_o:    out std_logic_vector(15 downto 0)
);
end registers;
 
architecture regs_arch of registers is
 
component reg port(
        d:      in std_logic_vector(15 downto 0);
        clk:    in std_logic;
        wr_en:  in std_logic;
        q:      out std_logic_vector(15 downto 0)
);
end component;
 
component reg_dec port(
        addr:   in std_logic_vector(2 downto 0);
        en0:    out std_logic;
        en1:    out std_logic;
        en2:    out std_logic;
        en3:    out std_logic;
        en4:    out std_logic;
        en5:    out std_logic;
        en6:    out std_logic;
        en7:    out std_logic
);
end component;
 
component mux_8_1 port(
        a:      in std_logic_vector(15 downto 0);
        b:      in std_logic_vector(15 downto 0);
        c:      in std_logic_vector(15 downto 0);
        d:      in std_logic_vector(15 downto 0);
        e:      in std_logic_vector(15 downto 0);
        f:      in std_logic_vector(15 downto 0);
        g:      in std_logic_vector(15 downto 0);
        h:      in std_logic_vector(15 downto 0);
        sel:    in std_logic_vector(2 downto 0);
        o:      out std_logic_vector(15 downto 0)
);
end component;
 
signal w0, w1, w2, w3, w4, w5, w6, w7: std_logic;
signal q0, q1, q2, q3, q4, q5, q6, q7: std_logic_vector(15 downto 0);
signal wr_clk: std_logic;
 
begin
        wr_clk <= wr_en and clk;
        decode: reg_dec
                port map(addr_a, w0, w1, w2, w3, w4, w5, w6, w7);
        r0: reg
                port map(d, wr_clk, w0, q0);
        r1: reg
                port map(d, wr_clk, w1, q1);
        r2: reg
                port map(d, wr_clk, w2, q2);
        r3: reg
                port map(d, wr_clk, w3, q3);
        r4: reg
                port map(d, wr_clk, w4, q4);
        r5: reg
                port map(d, wr_clk, w5, q5);
        r6: reg
                port map(d, wr_clk, w6, q6);
        r7: reg
                port map(d, wr_clk, w7, q7);
        out_mux_a: mux_8_1
                port map(q0, q1, q2, q3, q4, q5, q6, q7, addr_a, a_o);
        out_mux_b: mux_8_1
                port map(q0, q1, q2, q3, q4, q5, q6, q7, addr_b, b_o);
end regs_arch;

Line No.	Rev	Author	Line
1	2	thebeekeep	`-- 10/24/2005`
2			`-- General Purpose Register Bank`
3
4			`library ieee;`
5			`use ieee.std_logic_1164.all;`
6
7			`entity registers is port(`
8			`d: in std_logic_vector(15 downto 0);`
9			`clk: in std_logic;`
10			`addr_a: in std_logic_vector(2 downto 0);`
11			`addr_b: in std_logic_vector(2 downto 0);`
12			`wr_en: in std_logic;`
13			`a_o: out std_logic_vector(15 downto 0);`
14			`b_o: out std_logic_vector(15 downto 0)`
15			`);`
16			`end registers;`
17
18			`architecture regs_arch of registers is`
19
20			`component reg port(`
21			`d: in std_logic_vector(15 downto 0);`
22			`clk: in std_logic;`
23			`wr_en: in std_logic;`
24			`q: out std_logic_vector(15 downto 0)`
25			`);`
26			`end component;`
27
28			`component reg_dec port(`
29			`addr: in std_logic_vector(2 downto 0);`
30			`en0: out std_logic;`
31			`en1: out std_logic;`
32			`en2: out std_logic;`
33			`en3: out std_logic;`
34			`en4: out std_logic;`
35			`en5: out std_logic;`
36			`en6: out std_logic;`
37			`en7: out std_logic`
38			`);`
39			`end component;`
40
41			`component mux_8_1 port(`
42			`a: in std_logic_vector(15 downto 0);`
43			`b: in std_logic_vector(15 downto 0);`
44			`c: in std_logic_vector(15 downto 0);`
45			`d: in std_logic_vector(15 downto 0);`
46			`e: in std_logic_vector(15 downto 0);`
47			`f: in std_logic_vector(15 downto 0);`
48			`g: in std_logic_vector(15 downto 0);`
49			`h: in std_logic_vector(15 downto 0);`
50			`sel: in std_logic_vector(2 downto 0);`
51			`o: out std_logic_vector(15 downto 0)`
52			`);`
53			`end component;`
54
55			`signal w0, w1, w2, w3, w4, w5, w6, w7: std_logic;`
56			`signal q0, q1, q2, q3, q4, q5, q6, q7: std_logic_vector(15 downto 0);`
57			`signal wr_clk: std_logic;`
58
59			`begin`
60			`wr_clk <= wr_en and clk;`
61			`decode: reg_dec`
62			`port map(addr_a, w0, w1, w2, w3, w4, w5, w6, w7);`
63			`r0: reg`
64			`port map(d, wr_clk, w0, q0);`
65			`r1: reg`
66			`port map(d, wr_clk, w1, q1);`
67			`r2: reg`
68			`port map(d, wr_clk, w2, q2);`
69			`r3: reg`
70			`port map(d, wr_clk, w3, q3);`
71			`r4: reg`
72			`port map(d, wr_clk, w4, q4);`
73			`r5: reg`
74			`port map(d, wr_clk, w5, q5);`
75			`r6: reg`
76			`port map(d, wr_clk, w6, q6);`
77			`r7: reg`
78			`port map(d, wr_clk, w7, q7);`
79			`out_mux_a: mux_8_1`
80			`port map(q0, q1, q2, q3, q4, q5, q6, q7, addr_a, a_o);`
81			`out_mux_b: mux_8_1`
82			`port map(q0, q1, q2, q3, q4, q5, q6, q7, addr_b, b_o);`
83			`end regs_arch;`

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