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[/] [cpu16/] [trunk/] [regfile8x16.v] - Blame information for rev 2

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1 2 yzoer 
// megafunction wizard: %RAM: 3-PORT%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: alt3pram
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// ============================================================
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// File Name: regfile8x16.v
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// Megafunction Name(s):
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//                      alt3pram
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//
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// Simulation Library Files(s):
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//                      altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
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// ************************************************************
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//Copyright (C) 1991-2009 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, Altera MegaCore Function License
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//Agreement, or other applicable license agreement, including,
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//without limitation, that your use is for the sole purpose of
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//programming logic devices manufactured by Altera and sold by
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//Altera or its authorized distributors.  Please refer to the
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//applicable agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module regfile8x16 (
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        clock,
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        data,
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        rdaddress_a,
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        rdaddress_b,
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        wraddress,
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        wren,
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        qa,
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        qb);
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        input     clock;
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        input   [15:0]  data;
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        input   [2:0]  rdaddress_a;
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        input   [2:0]  rdaddress_b;
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        input   [2:0]  wraddress;
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        input     wren;
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        output  [15:0]  qa;
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        output  [15:0]  qb;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_off
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`endif
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        tri0      wren;
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`ifndef ALTERA_RESERVED_QIS
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// synopsys translate_on
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`endif
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        wire [15:0] sub_wire0;
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        wire [15:0] sub_wire1;
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        wire [15:0] qa = sub_wire0[15:0];
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        wire [15:0] qb = sub_wire1[15:0];
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        alt3pram        alt3pram_component (
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                                .wren (wren),
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                                .inclock (clock),
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                                .data (data),
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                                .rdaddress_a (rdaddress_a),
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                                .wraddress (wraddress),
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                                .rdaddress_b (rdaddress_b),
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                                .qa (sub_wire0),
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                                .qb (sub_wire1)
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                                // synopsys translate_off
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                                ,
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                                .aclr (),
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                                .inclocken (),
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                                .outclock (),
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                                .outclocken (),
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                                .rden_a (),
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                                .rden_b ()
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                                // synopsys translate_on
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                                );
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        defparam
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                alt3pram_component.indata_aclr = "OFF",
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                alt3pram_component.indata_reg = "INCLOCK",
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                alt3pram_component.intended_device_family = "Cyclone II",
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                alt3pram_component.lpm_type = "alt3pram",
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                alt3pram_component.outdata_aclr_a = "OFF",
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                alt3pram_component.outdata_aclr_b = "OFF",
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                alt3pram_component.outdata_reg_a = "UNREGISTERED",
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                alt3pram_component.outdata_reg_b = "UNREGISTERED",
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                alt3pram_component.rdaddress_aclr_a = "OFF",
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                alt3pram_component.rdaddress_aclr_b = "OFF",
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                alt3pram_component.rdaddress_reg_a = "INCLOCK",
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                alt3pram_component.rdaddress_reg_b = "INCLOCK",
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                alt3pram_component.rdcontrol_aclr_a = "OFF",
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                alt3pram_component.rdcontrol_aclr_b = "OFF",
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                alt3pram_component.rdcontrol_reg_a = "UNREGISTERED",
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                alt3pram_component.rdcontrol_reg_b = "UNREGISTERED",
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                alt3pram_component.width = 16,
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                alt3pram_component.widthad = 3,
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                alt3pram_component.write_aclr = "OFF",
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                alt3pram_component.write_reg = "INCLOCK";
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
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// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
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// Retrieval info: PRIVATE: CLRqa NUMERIC "0"
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// Retrieval info: PRIVATE: CLRqb NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrdaddress_a NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrdaddress_b NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrren_a NUMERIC "0"
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// Retrieval info: PRIVATE: CLRrren_b NUMERIC "0"
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// Retrieval info: PRIVATE: CLRwrite NUMERIC "0"
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// Retrieval info: PRIVATE: Clock NUMERIC "0"
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// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
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// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
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// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
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// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
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// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
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// Retrieval info: PRIVATE: MIFfilename STRING ""
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
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// Retrieval info: PRIVATE: REGdata NUMERIC "1"
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// Retrieval info: PRIVATE: REGqa NUMERIC "0"
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// Retrieval info: PRIVATE: REGqb NUMERIC "0"
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// Retrieval info: PRIVATE: REGrdaddress_a NUMERIC "1"
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// Retrieval info: PRIVATE: REGrdaddress_b NUMERIC "1"
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// Retrieval info: PRIVATE: REGrren_a NUMERIC "0"
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// Retrieval info: PRIVATE: REGrren_b NUMERIC "0"
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// Retrieval info: PRIVATE: REGwrite NUMERIC "1"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: WidthAddr NUMERIC "3"
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// Retrieval info: PRIVATE: WidthData NUMERIC "16"
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// Retrieval info: PRIVATE: enable NUMERIC "0"
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// Retrieval info: PRIVATE: rden_a NUMERIC "0"
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// Retrieval info: PRIVATE: rden_b NUMERIC "0"
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// Retrieval info: CONSTANT: INDATA_ACLR STRING "OFF"
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// Retrieval info: CONSTANT: INDATA_REG STRING "INCLOCK"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "alt3pram"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "OFF"
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// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "OFF"
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// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: RDADDRESS_ACLR_A STRING "OFF"
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// Retrieval info: CONSTANT: RDADDRESS_ACLR_B STRING "OFF"
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// Retrieval info: CONSTANT: RDADDRESS_REG_A STRING "INCLOCK"
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// Retrieval info: CONSTANT: RDADDRESS_REG_B STRING "INCLOCK"
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// Retrieval info: CONSTANT: RDCONTROL_ACLR_A STRING "OFF"
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// Retrieval info: CONSTANT: RDCONTROL_ACLR_B STRING "OFF"
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// Retrieval info: CONSTANT: RDCONTROL_REG_A STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "UNREGISTERED"
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// Retrieval info: CONSTANT: WIDTH NUMERIC "16"
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// Retrieval info: CONSTANT: WIDTHAD NUMERIC "3"
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// Retrieval info: CONSTANT: WRITE_ACLR STRING "OFF"
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// Retrieval info: CONSTANT: WRITE_REG STRING "INCLOCK"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
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// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
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// Retrieval info: USED_PORT: qa 0 0 16 0 OUTPUT NODEFVAL qa[15..0]
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// Retrieval info: USED_PORT: qb 0 0 16 0 OUTPUT NODEFVAL qb[15..0]
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// Retrieval info: USED_PORT: rdaddress_a 0 0 3 0 INPUT NODEFVAL rdaddress_a[2..0]
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// Retrieval info: USED_PORT: rdaddress_b 0 0 3 0 INPUT NODEFVAL rdaddress_b[2..0]
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// Retrieval info: USED_PORT: wraddress 0 0 3 0 INPUT NODEFVAL wraddress[2..0]
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// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND wren
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// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
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// Retrieval info: CONNECT: qa 0 0 16 0 @qa 0 0 16 0
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// Retrieval info: CONNECT: qb 0 0 16 0 @qb 0 0 16 0
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// Retrieval info: CONNECT: @wraddress 0 0 3 0 wraddress 0 0 3 0
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// Retrieval info: CONNECT: @rdaddress_a 0 0 3 0 rdaddress_a 0 0 3 0
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// Retrieval info: CONNECT: @rdaddress_b 0 0 3 0 rdaddress_b 0 0 3 0
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// Retrieval info: CONNECT: @wren 0 0 0 0 wren 0 0 0 0
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// Retrieval info: CONNECT: @inclock 0 0 0 0 clock 0 0 0 0
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: GEN_FILE: TYPE_NORMAL regfile8x16.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL regfile8x16.inc TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL regfile8x16.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL regfile8x16.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL regfile8x16_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL regfile8x16_bb.v TRUE
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// Retrieval info: LIB_FILE: altera_mf

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