1 |
2 |
yzoer |
// megafunction wizard: %RAM: 3-PORT%
|
2 |
|
|
// GENERATION: STANDARD
|
3 |
|
|
// VERSION: WM1.0
|
4 |
|
|
// MODULE: alt3pram
|
5 |
|
|
|
6 |
|
|
// ============================================================
|
7 |
|
|
// File Name: regfile8x16.v
|
8 |
|
|
// Megafunction Name(s):
|
9 |
|
|
// alt3pram
|
10 |
|
|
//
|
11 |
|
|
// Simulation Library Files(s):
|
12 |
|
|
// altera_mf
|
13 |
|
|
// ============================================================
|
14 |
|
|
// ************************************************************
|
15 |
|
|
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
16 |
|
|
//
|
17 |
|
|
// 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
|
18 |
|
|
// ************************************************************
|
19 |
|
|
|
20 |
|
|
|
21 |
|
|
//Copyright (C) 1991-2009 Altera Corporation
|
22 |
|
|
//Your use of Altera Corporation's design tools, logic functions
|
23 |
|
|
//and other software and tools, and its AMPP partner logic
|
24 |
|
|
//functions, and any output files from any of the foregoing
|
25 |
|
|
//(including device programming or simulation files), and any
|
26 |
|
|
//associated documentation or information are expressly subject
|
27 |
|
|
//to the terms and conditions of the Altera Program License
|
28 |
|
|
//Subscription Agreement, Altera MegaCore Function License
|
29 |
|
|
//Agreement, or other applicable license agreement, including,
|
30 |
|
|
//without limitation, that your use is for the sole purpose of
|
31 |
|
|
//programming logic devices manufactured by Altera and sold by
|
32 |
|
|
//Altera or its authorized distributors. Please refer to the
|
33 |
|
|
//applicable agreement for further details.
|
34 |
|
|
|
35 |
|
|
|
36 |
|
|
// synopsys translate_off
|
37 |
|
|
`timescale 1 ps / 1 ps
|
38 |
|
|
// synopsys translate_on
|
39 |
|
|
module regfile8x16 (
|
40 |
|
|
clock,
|
41 |
|
|
data,
|
42 |
|
|
rdaddress_a,
|
43 |
|
|
rdaddress_b,
|
44 |
|
|
wraddress,
|
45 |
|
|
wren,
|
46 |
|
|
qa,
|
47 |
|
|
qb);
|
48 |
|
|
|
49 |
|
|
input clock;
|
50 |
|
|
input [15:0] data;
|
51 |
|
|
input [2:0] rdaddress_a;
|
52 |
|
|
input [2:0] rdaddress_b;
|
53 |
|
|
input [2:0] wraddress;
|
54 |
|
|
input wren;
|
55 |
|
|
output [15:0] qa;
|
56 |
|
|
output [15:0] qb;
|
57 |
|
|
`ifndef ALTERA_RESERVED_QIS
|
58 |
|
|
// synopsys translate_off
|
59 |
|
|
`endif
|
60 |
|
|
tri0 wren;
|
61 |
|
|
`ifndef ALTERA_RESERVED_QIS
|
62 |
|
|
// synopsys translate_on
|
63 |
|
|
`endif
|
64 |
|
|
|
65 |
|
|
wire [15:0] sub_wire0;
|
66 |
|
|
wire [15:0] sub_wire1;
|
67 |
|
|
wire [15:0] qa = sub_wire0[15:0];
|
68 |
|
|
wire [15:0] qb = sub_wire1[15:0];
|
69 |
|
|
|
70 |
|
|
alt3pram alt3pram_component (
|
71 |
|
|
.wren (wren),
|
72 |
|
|
.inclock (clock),
|
73 |
|
|
.data (data),
|
74 |
|
|
.rdaddress_a (rdaddress_a),
|
75 |
|
|
.wraddress (wraddress),
|
76 |
|
|
.rdaddress_b (rdaddress_b),
|
77 |
|
|
.qa (sub_wire0),
|
78 |
|
|
.qb (sub_wire1)
|
79 |
|
|
// synopsys translate_off
|
80 |
|
|
,
|
81 |
|
|
.aclr (),
|
82 |
|
|
.inclocken (),
|
83 |
|
|
.outclock (),
|
84 |
|
|
.outclocken (),
|
85 |
|
|
.rden_a (),
|
86 |
|
|
.rden_b ()
|
87 |
|
|
// synopsys translate_on
|
88 |
|
|
);
|
89 |
|
|
defparam
|
90 |
|
|
alt3pram_component.indata_aclr = "OFF",
|
91 |
|
|
alt3pram_component.indata_reg = "INCLOCK",
|
92 |
|
|
alt3pram_component.intended_device_family = "Cyclone II",
|
93 |
|
|
alt3pram_component.lpm_type = "alt3pram",
|
94 |
|
|
alt3pram_component.outdata_aclr_a = "OFF",
|
95 |
|
|
alt3pram_component.outdata_aclr_b = "OFF",
|
96 |
|
|
alt3pram_component.outdata_reg_a = "UNREGISTERED",
|
97 |
|
|
alt3pram_component.outdata_reg_b = "UNREGISTERED",
|
98 |
|
|
alt3pram_component.rdaddress_aclr_a = "OFF",
|
99 |
|
|
alt3pram_component.rdaddress_aclr_b = "OFF",
|
100 |
|
|
alt3pram_component.rdaddress_reg_a = "INCLOCK",
|
101 |
|
|
alt3pram_component.rdaddress_reg_b = "INCLOCK",
|
102 |
|
|
alt3pram_component.rdcontrol_aclr_a = "OFF",
|
103 |
|
|
alt3pram_component.rdcontrol_aclr_b = "OFF",
|
104 |
|
|
alt3pram_component.rdcontrol_reg_a = "UNREGISTERED",
|
105 |
|
|
alt3pram_component.rdcontrol_reg_b = "UNREGISTERED",
|
106 |
|
|
alt3pram_component.width = 16,
|
107 |
|
|
alt3pram_component.widthad = 3,
|
108 |
|
|
alt3pram_component.write_aclr = "OFF",
|
109 |
|
|
alt3pram_component.write_reg = "INCLOCK";
|
110 |
|
|
|
111 |
|
|
|
112 |
|
|
endmodule
|
113 |
|
|
|
114 |
|
|
// ============================================================
|
115 |
|
|
// CNX file retrieval info
|
116 |
|
|
// ============================================================
|
117 |
|
|
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
|
118 |
|
|
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
|
119 |
|
|
// Retrieval info: PRIVATE: CLRqa NUMERIC "0"
|
120 |
|
|
// Retrieval info: PRIVATE: CLRqb NUMERIC "0"
|
121 |
|
|
// Retrieval info: PRIVATE: CLRrdaddress_a NUMERIC "0"
|
122 |
|
|
// Retrieval info: PRIVATE: CLRrdaddress_b NUMERIC "0"
|
123 |
|
|
// Retrieval info: PRIVATE: CLRrren_a NUMERIC "0"
|
124 |
|
|
// Retrieval info: PRIVATE: CLRrren_b NUMERIC "0"
|
125 |
|
|
// Retrieval info: PRIVATE: CLRwrite NUMERIC "0"
|
126 |
|
|
// Retrieval info: PRIVATE: Clock NUMERIC "0"
|
127 |
|
|
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
128 |
|
|
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
129 |
|
|
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
|
130 |
|
|
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
|
131 |
|
|
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
|
132 |
|
|
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
|
133 |
|
|
// Retrieval info: PRIVATE: MIFfilename STRING ""
|
134 |
|
|
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
135 |
|
|
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
136 |
|
|
// Retrieval info: PRIVATE: REGqa NUMERIC "0"
|
137 |
|
|
// Retrieval info: PRIVATE: REGqb NUMERIC "0"
|
138 |
|
|
// Retrieval info: PRIVATE: REGrdaddress_a NUMERIC "1"
|
139 |
|
|
// Retrieval info: PRIVATE: REGrdaddress_b NUMERIC "1"
|
140 |
|
|
// Retrieval info: PRIVATE: REGrren_a NUMERIC "0"
|
141 |
|
|
// Retrieval info: PRIVATE: REGrren_b NUMERIC "0"
|
142 |
|
|
// Retrieval info: PRIVATE: REGwrite NUMERIC "1"
|
143 |
|
|
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
144 |
|
|
// Retrieval info: PRIVATE: WidthAddr NUMERIC "3"
|
145 |
|
|
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
|
146 |
|
|
// Retrieval info: PRIVATE: enable NUMERIC "0"
|
147 |
|
|
// Retrieval info: PRIVATE: rden_a NUMERIC "0"
|
148 |
|
|
// Retrieval info: PRIVATE: rden_b NUMERIC "0"
|
149 |
|
|
// Retrieval info: CONSTANT: INDATA_ACLR STRING "OFF"
|
150 |
|
|
// Retrieval info: CONSTANT: INDATA_REG STRING "INCLOCK"
|
151 |
|
|
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
|
152 |
|
|
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt3pram"
|
153 |
|
|
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "OFF"
|
154 |
|
|
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "OFF"
|
155 |
|
|
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
|
156 |
|
|
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
|
157 |
|
|
// Retrieval info: CONSTANT: RDADDRESS_ACLR_A STRING "OFF"
|
158 |
|
|
// Retrieval info: CONSTANT: RDADDRESS_ACLR_B STRING "OFF"
|
159 |
|
|
// Retrieval info: CONSTANT: RDADDRESS_REG_A STRING "INCLOCK"
|
160 |
|
|
// Retrieval info: CONSTANT: RDADDRESS_REG_B STRING "INCLOCK"
|
161 |
|
|
// Retrieval info: CONSTANT: RDCONTROL_ACLR_A STRING "OFF"
|
162 |
|
|
// Retrieval info: CONSTANT: RDCONTROL_ACLR_B STRING "OFF"
|
163 |
|
|
// Retrieval info: CONSTANT: RDCONTROL_REG_A STRING "UNREGISTERED"
|
164 |
|
|
// Retrieval info: CONSTANT: RDCONTROL_REG_B STRING "UNREGISTERED"
|
165 |
|
|
// Retrieval info: CONSTANT: WIDTH NUMERIC "16"
|
166 |
|
|
// Retrieval info: CONSTANT: WIDTHAD NUMERIC "3"
|
167 |
|
|
// Retrieval info: CONSTANT: WRITE_ACLR STRING "OFF"
|
168 |
|
|
// Retrieval info: CONSTANT: WRITE_REG STRING "INCLOCK"
|
169 |
|
|
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
|
170 |
|
|
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
|
171 |
|
|
// Retrieval info: USED_PORT: qa 0 0 16 0 OUTPUT NODEFVAL qa[15..0]
|
172 |
|
|
// Retrieval info: USED_PORT: qb 0 0 16 0 OUTPUT NODEFVAL qb[15..0]
|
173 |
|
|
// Retrieval info: USED_PORT: rdaddress_a 0 0 3 0 INPUT NODEFVAL rdaddress_a[2..0]
|
174 |
|
|
// Retrieval info: USED_PORT: rdaddress_b 0 0 3 0 INPUT NODEFVAL rdaddress_b[2..0]
|
175 |
|
|
// Retrieval info: USED_PORT: wraddress 0 0 3 0 INPUT NODEFVAL wraddress[2..0]
|
176 |
|
|
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND wren
|
177 |
|
|
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
|
178 |
|
|
// Retrieval info: CONNECT: qa 0 0 16 0 @qa 0 0 16 0
|
179 |
|
|
// Retrieval info: CONNECT: qb 0 0 16 0 @qb 0 0 16 0
|
180 |
|
|
// Retrieval info: CONNECT: @wraddress 0 0 3 0 wraddress 0 0 3 0
|
181 |
|
|
// Retrieval info: CONNECT: @rdaddress_a 0 0 3 0 rdaddress_a 0 0 3 0
|
182 |
|
|
// Retrieval info: CONNECT: @rdaddress_b 0 0 3 0 rdaddress_b 0 0 3 0
|
183 |
|
|
// Retrieval info: CONNECT: @wren 0 0 0 0 wren 0 0 0 0
|
184 |
|
|
// Retrieval info: CONNECT: @inclock 0 0 0 0 clock 0 0 0 0
|
185 |
|
|
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
186 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL regfile8x16.v TRUE
|
187 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL regfile8x16.inc TRUE
|
188 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL regfile8x16.cmp FALSE
|
189 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL regfile8x16.bsf FALSE
|
190 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL regfile8x16_inst.v FALSE
|
191 |
|
|
// Retrieval info: GEN_FILE: TYPE_NORMAL regfile8x16_bb.v TRUE
|
192 |
|
|
// Retrieval info: LIB_FILE: altera_mf
|