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Subversion Repositories cpu6502_true_cycle

[/] [cpu6502_true_cycle/] [branches/] [avendor/] [TO_DO_list.txt] - Blame information for rev 18

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(January, 4th 2009)
- (DONE) Remove unused nets, register and modules
- (85%) Finish working for Specification of cpu65C02_tc
- (DONE) Update the HDL Designer files for better viewing and
  understanding
 
(August, 5th 2008)
- (DONE) Rename all port names (_i, _o, _o_i)
- (DONE) Test and verify all Op Codes
- (DONE) Optimize core for speed
- (75%) Finish working for Specification of cpu65C02_tc
- (WORKING) Create high level testbench in assembler and hardware for
  testing all Op Codes (include accurate cycle timing)
- (WORKING) Create simulation files for Modelsim
- (WORKING) Create a simple .wlf file to demonstrate the cpu65C02_tc
- Update the HDL Designer files for better viewing and understanding

Line No.	Rev	Author	Line
1	6	fpga_is_fu	`(January, 4th 2009)`
2			`- (DONE) Remove unused nets, register and modules`
3			`- (85%) Finish working for Specification of cpu65C02_tc`
4			`- (DONE) Update the HDL Designer files for better viewing and`
5			`understanding`
6
7			`(August, 5th 2008)`
8			`- (DONE) Rename all port names (_i, _o, _o_i)`
9			`- (DONE) Test and verify all Op Codes`
10			`- (DONE) Optimize core for speed`
11			`- (75%) Finish working for Specification of cpu65C02_tc`
12			`- (WORKING) Create high level testbench in assembler and hardware for`
13	2	fpga_is_fu	`testing all Op Codes (include accurate cycle timing)`
14	6	fpga_is_fu	`- (WORKING) Create simulation files for Modelsim`
15			`- (WORKING) Create a simple .wlf file to demonstrate the cpu65C02_tc`
16	2	fpga_is_fu	`- Update the HDL Designer files for better viewing and understanding`

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Subversion Repositories cpu6502_true_cycle

[/] [cpu6502_true_cycle/] [branches/] [avendor/] [TO_DO_list.txt] - Blame information for rev 18