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[/] [cpu6502_true_cycle/] [branches/] [avendor/] [rtl/] [vhdl/] [add_sub.vhd] - Blame information for rev 18

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1 2 fpga_is_fu 
-- VHDL Entity R6502_TC.ADD_SUB.symbol
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--
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-- Created:
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--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
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--          at - 19:06:54 08.04.2008
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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entity ADD_SUB is
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   port(
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      ch_a_i           : in     std_logic_vector ( 7 downto 0 ) := X"00";
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      ch_b_i           : in     std_logic_vector ( 7 downto 0 ) := X"00";
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      reg_0flag_i      : in     std_logic                       := '0';
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      reg_7flag_core_i : in     std_logic                       := '0';
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      sel              : in     std_logic_vector ( 1 downto 0 ) := "00";
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      q_a_o            : out    std_logic_vector ( 7 downto 0 ) := X"00";
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      reg_0flag_o      : out    std_logic                       := '0';
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      reg_6flag_o      : out    std_logic                       := '0';
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      zw_alu           : inout  std_logic_vector ( 8 downto 0 ) := '0' & X"00";
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      zw_alu1          : inout  std_logic_vector ( 8 downto 0 ) := '0' & X"00";
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      zw_alu2          : inout  std_logic_vector ( 8 downto 0 ) := '0' & X"00";
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      zw_alu3          : inout  std_logic_vector ( 8 downto 0 ) := '0' & X"00";
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      zw_alu4          : inout  std_logic_vector ( 8 downto 0 ) := '0' & X"00";
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      zw_alu5          : inout  std_logic_vector ( 8 downto 0 ) := '0' & X"00";
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      zw_alu6          : inout  std_logic_vector ( 8 downto 0 ) := '0' & X"00"
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   );
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-- Declarations
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end ADD_SUB ;
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-- Jens-D. Gutschmidt     Project:  R6502_TC
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-- scantara2003@yahoo.de
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-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
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--
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or any later version.
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--
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.
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--
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-- CVS Revisins History
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--
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-- $Log: not supported by cvs2svn $
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--
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-- Title:  Adder and Substractor
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-- Path:  R6502_TC/ADD_SUB/flow
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-- Edited:  by eda on 08 Apr 2008
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--
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-- VHDL Architecture R6502_TC.ADD_SUB.flow
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--
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-- Created:
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--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
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--          at - 19:06:54 08.04.2008
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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architecture flow of ADD_SUB is
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begin
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   -----------------------------------------------------------------
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   process0_proc : process (ch_a_i, ch_b_i, reg_0flag_i, reg_7flag_core_i, sel, zw_alu, zw_alu1, zw_alu2, zw_alu3, zw_alu4, zw_alu5, zw_alu6)
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   -----------------------------------------------------------------
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   begin
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      case sel(1 downto 0) is
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      when "01" =>
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         reg_6flag_o <= reg_7flag_core_i XOR zw_ALU(7);
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         reg_0flag_o <= zw_ALU4(4);
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         q_a_o <= zw_ALU(7 downto 0);
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         zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) +
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          unsigned (zw_ALU6(7 downto 5));
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         zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) +
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          unsigned (zw_ALU5(7 downto 5));
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         zw_ALU6(7 downto 5) <=  (zw_ALU2(4) OR zw_ALU4(4)) &
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          (zw_ALU2(4) OR zw_ALU4(4)) & '0';
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         zw_ALU5(7 downto 5) <=  (zw_ALU1(4) OR zw_ALU3(4)) &
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          (zw_ALU1(4) OR zw_ALU3(4)) & '0';
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         zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
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         zw_ALU2(4 downto 0) <= unsigned ('0' & ch_a_i(7 downto 4)) + unsigned
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         ('0' & ch_b_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
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         zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
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         zw_ALU1(4 downto 0) <= unsigned ('0' & ch_a_i(3 downto 0)) + unsigned
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         ('0' & ch_b_i(3 downto 0)) + reg_0flag_i;
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      when "00" =>
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         reg_6flag_o <= reg_7flag_core_i XOR zw_ALU(7);
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         reg_0flag_o <= zw_ALU(8);
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         q_a_o <= zw_ALU(7 downto 0);
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         zw_ALU <= unsigned ('0' & ch_a_i) + unsigned ('0' & ch_b_i) + reg_0flag_i;
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      when "10" =>
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         reg_6flag_o <= reg_7flag_core_i XOR zw_ALU(7);
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         reg_0flag_o <= zw_ALU(8);
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         q_a_o <= zw_ALU(7 downto 0);
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         zw_ALU <= unsigned ('0' & ch_a_i) + unsigned ('0' & NOT (ch_b_i)) + reg_0flag_i;
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      when "11" =>
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         reg_6flag_o <= reg_7flag_core_i XOR zw_ALU(7);
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         reg_0flag_o <= zw_ALU2(4);
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         q_a_o <= zw_ALU(7 downto 0);
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         zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) +
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         unsigned ((zw_ALU6(8 downto 5)));
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         zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) +
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         unsigned ((zw_ALU5(8 downto 5)));
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         zw_ALU6(8 downto 5) <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' &
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         (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
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         zw_ALU5(8 downto 5) <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' &
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         (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
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         zw_ALU4(4 downto 0) <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
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         zw_ALU2(4 downto 0) <= unsigned ('0' & ch_a_i(7 downto 4)) + unsigned
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         ('0' & NOT (ch_b_i(7 downto 4))) + zw_ALU1(4);
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         zw_ALU3(4 downto 0) <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
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         zw_ALU1(4 downto 0) <= unsigned ('0' & ch_a_i(3 downto 0)) + unsigned
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         ('0' & NOT (ch_b_i(3 downto 0))) + reg_0flag_i;
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      when others =>
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         reg_6flag_o <= reg_7flag_core_i XOR zw_ALU(7);
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         reg_0flag_o <= zw_ALU(8);
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         q_a_o <= zw_ALU(7 downto 0);
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         zw_ALU <= unsigned ('0' & ch_a_i) + unsigned ('0' & ch_b_i) + reg_0flag_i;
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      end case;
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   end process process0_proc;
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end flow;

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