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-- VHDL Entity R6502_TC.fsm_core_V2_0.symbol

--

-- Created:

--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)

--          at - 19:06:55 08.04.2008

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

--

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

entity fsm_core_V2_0 is

   port(

      adr_nxt_pc_i    : in     std_logic_vector (15 downto 0);

      adr_nxt_sp_i    : in     std_logic_vector (15 downto 0);

      adr_pc_i        : in     std_logic_vector (15 downto 0);

      adr_sp_i        : in     std_logic_vector (15 downto 0);

      clk_clk_i       : in     std_logic;

      cout_pc_i       : in     std_logic;

      d_alu_i         : in     std_logic_vector ( 7 downto 0 );

      d_i             : in     std_logic_vector ( 7 downto 0 );

      d_regs_out_i    : in     std_logic_vector ( 7 downto 0 );

      irq_n_i         : in     std_logic;

      nmi_i           : in     std_logic;

      q_a_i           : in     std_logic_vector ( 7 downto 0 );

      q_x_i           : in     std_logic_vector ( 7 downto 0 );

      q_y_i           : in     std_logic_vector ( 7 downto 0 );

      rdy_i           : in     std_logic;

      reg_0flag_i     : in     std_logic;

      reg_1flag_i     : in     std_logic;

      reg_6flag_i     : in     std_logic;

      reg_7flag_i     : in     std_logic;

      rst_rst_n_i     : in     std_logic;

      so_n_i          : in     std_logic;

      a_o             : out    std_logic_vector (15 downto 0);

      adr_o           : out    std_logic_vector (15 downto 0);

      ch_a_o          : out    std_logic_vector ( 7 downto 0 );

      ch_b_o          : out    std_logic_vector ( 7 downto 0 );

      d_o             : out    std_logic_vector ( 7 downto 0 );

      d_regs_in_o     : out    std_logic_vector ( 7 downto 0 );

      ld_o            : out    std_logic_vector ( 1 downto 0 );

      ld_pc_o         : out    std_logic;

      ld_sp_o         : out    std_logic;

      load_regs_o     : out    std_logic;

      offset_o        : out    std_logic_vector ( 15 downto 0 );

      rd_o            : out    std_logic;

      reg_0flag_o     : out    std_logic;

      reg_1flag_o     : out    std_logic;

      reg_3flag_o     : out    std_logic;

      reg_7flag_o     : out    std_logic;

      sync_o          : out    std_logic;

      wr_n_o          : out    std_logic;

      wr_o            : out    std_logic;

      sel_alu_as_o_i  : inout  std_logic;

      sel_alu_out_o_i : inout  std_logic_vector ( 2 downto 0 );

      sel_pc_as_o_i   : inout  std_logic;

      sel_pc_in_o_i   : inout  std_logic_vector ( 1 downto 0 );

      sel_pc_val_o_i  : inout  std_logic_vector ( 1 downto 0 );

      sel_rb_in_o_i   : inout  std_logic_vector ( 2 downto 0 );

      sel_rb_out_o_i  : inout  std_logic_vector ( 2 downto 0 );

      sel_reg_o_i     : inout  std_logic_vector ( 1 downto 0 );

      sel_sp_as_o_i   : inout  std_logic;

      sel_sp_in_o_i   : inout  std_logic_vector ( 1 downto 0 );

      sel_sp_val_o_i  : inout  std_logic_vector ( 1 downto 0 )

   );

-- Declarations

end fsm_core_V2_0 ;

-- Jens-D. Gutschmidt     Project:  R6502_TC  

-- scantara2003@yahoo.de                      

-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG                                                                                     

--                                                                                                                                             

-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by   

-- the Free Software Foundation, either version 3 of the License, or any later version.                                                        

--                                                                                                                                             

-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of              

-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.                                  

--                                                                                                                                             

-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.     

--                                                                                                                                             

-- CVS Revisins History                                                                                                                        

--                                                                                                                                             

-- $Log: not supported by cvs2svn $                                                                                                                                       

--                                                                                                                                             

-- Title:  FSM for all op codes  

-- Path:  R6502_TC/fsm_core_V2_0/fsm  

-- Edited:  by eda on 08 Apr 2008  

--

-- VHDL Architecture R6502_TC.fsm_core_V2_0.fsm

--

-- Created:

--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)

--          at - 19:06:56 08.04.2008

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

--

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

architecture fsm of fsm_core_V2_0 is

   -- Architecture Declarations

   signal reg_F : std_logic_vector( 7 DOWNTO 0 );

   signal reg_PC : std_logic_vector(15 DOWNTO 0);

   signal reg_PC1 : std_logic_vector( 15 DOWNTO 0 );

   signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );

   signal sig_PC : std_logic_vector(15 DOWNTO 0);

   signal sig_RD : std_logic;

   signal sig_RWn : std_logic;

   signal sig_SYNC : std_logic;

   signal sig_WR : std_logic;

   signal zw_ALU : std_logic_vector( 8 DOWNTO 0 );

   signal zw_ALU1 : std_logic_vector( 8 DOWNTO 0 );

   signal zw_ALU2 : std_logic_vector( 8 DOWNTO 0 );

   signal zw_ALU3 : std_logic_vector( 8 DOWNTO 0 );

   signal zw_ALU4 : std_logic_vector( 8 DOWNTO 0 );

   signal zw_ALU5 : std_logic_vector( 8 DOWNTO 0 );

   signal zw_ALU6 : std_logic_vector( 8 DOWNTO 0 );

   signal zw_PC : std_logic_vector( 15 DOWNTO 0 );

   signal zw_REG_ALU : std_logic_vector( 8 DOWNTO 0 );

   signal zw_REG_NMI : std_logic;

   signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );

   signal zw_REG_sig_PC : std_logic_vector(15 DOWNTO 0);

   signal zw_b1 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b2 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b3 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b4 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_w1 : std_logic_vector( 15 DOWNTO 0 );

   signal zw_w2 : std_logic_vector( 15 DOWNTO 0 );

   signal zw_w3 : std_logic_vector( 15 DOWNTO 0 );

   subtype state_type is

      std_logic_vector(7 downto 0);

   -- State vector declaration

   attribute state_vector : string;

   attribute state_vector of fsm : architecture is "current_state";

   -- Hard encoding

   constant FETCH : state_type := "00000000";

   constant s1 : state_type := "00000001";

   constant s2 : state_type := "00000011";

   constant s5 : state_type := "00000010";

   constant s3 : state_type := "00000110";

   constant s4 : state_type := "00000111";

   constant s12 : state_type := "00000101";

   constant s16 : state_type := "00000100";

   constant s17 : state_type := "00001100";

   constant s24 : state_type := "00001101";

   constant s25 : state_type := "00001111";

   constant s271 : state_type := "00001110";

   constant s273 : state_type := "00001010";

   constant s304 : state_type := "00001011";

   constant s307 : state_type := "00001001";

   constant s177 : state_type := "00001000";

   constant s180 : state_type := "00011000";

   constant s181 : state_type := "00011001";

   constant s182 : state_type := "00011011";

   constant s183 : state_type := "00011010";

   constant s184 : state_type := "00011110";

   constant s185 : state_type := "00011111";

   constant s186 : state_type := "00011101";

   constant s187 : state_type := "00011100";

   constant s188 : state_type := "00010100";

   constant s189 : state_type := "00010101";

   constant s190 : state_type := "00010111";

   constant s191 : state_type := "00010110";

   constant s192 : state_type := "00010010";

   constant s193 : state_type := "00010011";

   constant s377 : state_type := "00010001";

   constant s381 : state_type := "00010000";

   constant s378 : state_type := "00110000";

   constant s382 : state_type := "00110001";

   constant s379 : state_type := "00110011";

   constant s383 : state_type := "00110010";

   constant s384 : state_type := "00110110";

   constant s380 : state_type := "00110111";

   constant s385 : state_type := "00110101";

   constant s386 : state_type := "00110100";

   constant s387 : state_type := "00111100";

   constant s388 : state_type := "00111101";

   constant s389 : state_type := "00111111";

   constant s391 : state_type := "00111110";

   constant s392 : state_type := "00111010";

   constant s390 : state_type := "00111011";

   constant s393 : state_type := "00111001";

   constant s394 : state_type := "00111000";

   constant s395 : state_type := "00101000";

   constant s396 : state_type := "00101001";

   constant s397 : state_type := "00101011";

   constant s398 : state_type := "00101010";

   constant s399 : state_type := "00101110";

   constant s400 : state_type := "00101111";

   constant s401 : state_type := "00101101";

   constant s526 : state_type := "00101100";

   constant s527 : state_type := "00100100";

   constant s528 : state_type := "00100101";

   constant s529 : state_type := "00100111";

   constant s530 : state_type := "00100110";

   constant s531 : state_type := "00100010";

   constant s544 : state_type := "00100011";

   constant s545 : state_type := "00100001";

   constant s546 : state_type := "00100000";

   constant s547 : state_type := "01100000";

   constant s549 : state_type := "01100001";

   constant s550 : state_type := "01100011";

   constant s404 : state_type := "01100010";

   constant s556 : state_type := "01100110";

   constant s557 : state_type := "01100111";

   constant s579 : state_type := "01100101";

   constant s201 : state_type := "01100100";

   constant s202 : state_type := "01101100";

   constant s210 : state_type := "01101101";

   constant s211 : state_type := "01101111";

   constant s215 : state_type := "01101110";

   constant s217 : state_type := "01101010";

   constant s218 : state_type := "01101011";

   constant s222 : state_type := "01101001";

   constant s223 : state_type := "01101000";

   constant s224 : state_type := "01111000";

   constant s225 : state_type := "01111001";

   constant s226 : state_type := "01111011";

   constant s243 : state_type := "01111010";

   constant s244 : state_type := "01111110";

   constant s247 : state_type := "01111111";

   constant s344 : state_type := "01111101";

   constant s343 : state_type := "01111100";

   constant s250 : state_type := "01110100";

   constant s251 : state_type := "01110101";

   constant s351 : state_type := "01110111";

   constant s361 : state_type := "01110110";

   constant s360 : state_type := "01110010";

   constant s403 : state_type := "01110011";

   constant s406 : state_type := "01110001";

   constant s407 : state_type := "01110000";

   constant s409 : state_type := "01010000";

   constant s412 : state_type := "01010001";

   constant s413 : state_type := "01010011";

   constant s416 : state_type := "01010010";

   constant s418 : state_type := "01010110";

   constant s510 : state_type := "01010111";

   constant s553 : state_type := "01010101";

   constant s555 : state_type := "01010100";

   constant s558 : state_type := "01011100";

   constant s560 : state_type := "01011101";

   constant s561 : state_type := "01011111";

   constant s563 : state_type := "01011110";

   constant s564 : state_type := "01011010";

   constant s565 : state_type := "01011011";

   constant s566 : state_type := "01011001";

   constant s266 : state_type := "01011000";

   constant s301 : state_type := "01001000";

   constant s302 : state_type := "01001001";

   constant RES : state_type := "01001011";

   constant s511 : state_type := "01001010";

   constant s559 : state_type := "01001110";

   constant s562 : state_type := "01001111";

   constant s567 : state_type := "01001101";

   constant s568 : state_type := "01001100";

   constant s569 : state_type := "01000100";

   constant s570 : state_type := "01000101";

   constant s571 : state_type := "01000111";

   constant s572 : state_type := "01000110";

   constant s573 : state_type := "01000010";

   constant s574 : state_type := "01000011";

   constant s548 : state_type := "01000001";

   constant s551 : state_type := "01000000";

   constant s552 : state_type := "11000000";

   constant s575 : state_type := "11000001";

   constant s576 : state_type := "11000011";

   constant s577 : state_type := "11000010";

   constant s532 : state_type := "11000110";

   constant s533 : state_type := "11000111";

   constant s534 : state_type := "11000101";

   constant s535 : state_type := "11000100";

   constant s536 : state_type := "11001100";

   constant s537 : state_type := "11001101";

   -- Declare current and next state signals

   signal current_state : state_type;

   signal next_state : state_type;

   -- Declare any pre-registered internal signals

   signal d_o_cld : std_logic_vector ( 7 downto 0 );

   signal rd_o_cld : std_logic ;

   signal sync_o_cld : std_logic ;

   signal wr_n_o_cld : std_logic ;

   signal wr_o_cld : std_logic ;

   signal sel_alu_as_o_i_cld : std_logic ;

   signal sel_alu_out_o_i_cld : std_logic_vector ( 2 downto 0 );

   signal sel_pc_as_o_i_cld : std_logic ;

   signal sel_pc_in_o_i_cld : std_logic_vector ( 1 downto 0 );

   signal sel_pc_val_o_i_cld : std_logic_vector ( 1 downto 0 );

   signal sel_rb_in_o_i_cld : std_logic_vector ( 2 downto 0 );

   signal sel_rb_out_o_i_cld : std_logic_vector ( 2 downto 0 );

   signal sel_reg_o_i_cld : std_logic_vector ( 1 downto 0 );

   signal sel_sp_as_o_i_cld : std_logic ;

   signal sel_sp_in_o_i_cld : std_logic_vector ( 1 downto 0 );

   signal sel_sp_val_o_i_cld : std_logic_vector ( 1 downto 0 );

begin

   -----------------------------------------------------------------

   clocked_proc : process (

      clk_clk_i,

      rst_rst_n_i

   )

   -----------------------------------------------------------------

   begin

      if (rst_rst_n_i = '0') then

         current_state <= RES;

         -- Default Reset Values

         d_o_cld <= X"00";

         rd_o_cld <= '0';

         sync_o_cld <= '0';

         wr_n_o_cld <= '1';

         wr_o_cld <= '0';

         sel_alu_as_o_i_cld <= '0';

         sel_alu_out_o_i_cld <= "000";

         sel_pc_as_o_i_cld <= '0';

         sel_pc_in_o_i_cld <= "00";

         sel_pc_val_o_i_cld <= "00";

         sel_rb_in_o_i_cld <= "000";

         sel_rb_out_o_i_cld <= "000";

         sel_reg_o_i_cld <= "00";

         sel_sp_as_o_i_cld <= '0';

         sel_sp_in_o_i_cld <= "00";

         sel_sp_val_o_i_cld <= "00";

         reg_F <= "00000100";

         reg_PC <= X"0000";

         reg_PC1 <= X"0000";

         sig_PC <= X"0000";

         zw_PC <= X"0000";

         zw_REG_ALU <= '0' & X"00";

         zw_REG_NMI <= '0';

         zw_REG_OP <= X"00";

         zw_REG_sig_PC <= X"0000";

         zw_b1 <= X"00";

         zw_b2 <= X"00";

         zw_b3 <= X"00";

         zw_b4 <= X"00";

         zw_w1 <= X"0000";

         zw_w2 <= X"0000";

         zw_w3 <= X"0000";

      elsif (clk_clk_i'event and clk_clk_i = '1') then

         current_state <= next_state;

         -- Default Assignment To Internals

         reg_F <= reg_F or ('0' & (not so_n_i) & "000000");

         reg_PC <= reg_PC;

         reg_PC1 <= reg_PC1;

         sig_PC <= sig_PC;

         zw_PC <= zw_PC;

         zw_REG_ALU <= zw_REG_ALU;

         zw_REG_NMI <= zw_REG_NMI or nmi_i;

         zw_REG_OP <= zw_REG_OP;

         zw_REG_sig_PC <= zw_REG_sig_PC;

         zw_b1 <= zw_b1;

         zw_b2 <= zw_b2;

         zw_b3 <= zw_b3;

         zw_b4 <= zw_b4;

         zw_w1 <= zw_w1;

         zw_w2 <= zw_w2;

         zw_w3 <= zw_w3;

         d_o_cld <= sig_D_OUT;

         rd_o_cld <= sig_RD;

         sync_o_cld <= sig_SYNC;

         wr_n_o_cld <= sig_RWn;

         wr_o_cld <= sig_WR;

         sel_alu_as_o_i_cld <= sel_alu_as_o_i;

         sel_alu_out_o_i_cld <= sel_alu_out_o_i;

         sel_pc_as_o_i_cld <= sel_pc_as_o_i;

         sel_pc_in_o_i_cld <= sel_pc_in_o_i;

         sel_pc_val_o_i_cld <= sel_pc_val_o_i;

         sel_rb_in_o_i_cld <= sel_rb_in_o_i;

         sel_rb_out_o_i_cld <= sel_rb_out_o_i;

         sel_reg_o_i_cld <= sel_reg_o_i;

         sel_sp_as_o_i_cld <= sel_sp_as_o_i;

         sel_sp_in_o_i_cld <= sel_sp_in_o_i;

         sel_sp_val_o_i_cld <= sel_sp_val_o_i;

         -- Combined Actions

         case current_state is

            when FETCH =>

               zw_REG_OP <= d_i;

               if ((zw_REG_NMI = '1') and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

                  sel_sp_in_o_i_cld <= "00";

                  sel_sp_as_o_i_cld <= '0';

                  sel_sp_val_o_i_cld <= "00";

                  zw_REG_NMI <= '0';

               elsif ((irq_n_i = '0' and

                      reg_F(2) = '0') and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

                  sel_sp_in_o_i_cld <= "00";

                  sel_sp_as_o_i_cld <= '0';

                  sel_sp_val_o_i_cld <= "00";

               elsif ((d_i = X"69" or

                      d_i = X"65" or

                      d_i = X"75" or

                      d_i = X"6D" or

                      d_i = X"7D" or

                      d_i = X"79" or

                      d_i = X"61" or

                      d_i = X"71") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

                  sel_alu_out_o_i_cld <= "110";

                  sel_alu_as_o_i_cld <= '0';

                  sel_reg_o_i_cld <= "00";

                  sel_rb_in_o_i_cld <= "011";

                  zw_b1(0) <= reg_F(7);

               elsif ((d_i = X"06" or

                      d_i = X"16" or

                      d_i = X"0E" or

                      d_i = X"1E") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

                  sel_alu_out_o_i_cld <= "110";

                  sel_alu_as_o_i_cld <= '0';

               elsif ((d_i = X"90" or

                      d_i = X"B0" or

                      d_i = X"F0" or

                      d_i = X"30" or

                      d_i = X"D0" or

                      d_i = X"10" or

                      d_i = X"50" or

                      d_i = X"70") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

                  zw_b3 <= adr_nxt_pc_i (15 downto 8);

               elsif ((d_i = X"24" or

                      d_i = X"2C") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

                  sel_alu_out_o_i_cld <= "110";

                  sel_alu_as_o_i_cld <= '0';

               elsif ((d_i = X"00") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

                  sel_sp_in_o_i_cld <= "00";

                  sel_sp_as_o_i_cld <= '0';

                  sel_sp_val_o_i_cld <= "00";

               elsif ((d_i = X"18") and (rdy_i = '1')) then

               elsif ((d_i = X"D8") and (rdy_i = '1')) then

               elsif ((d_i = X"58") and (rdy_i = '1')) then

               elsif ((d_i = X"B8") and (rdy_i = '1')) then

               elsif ((d_i = X"E0" or

                      d_i = X"E4" or

                      d_i = X"EC") and (rdy_i = '1')) then

                  sel_rb_out_o_i_cld <= "001";

                  sig_PC <= adr_nxt_pc_i;

                  sel_alu_out_o_i_cld <= "110";

                  sel_alu_as_o_i_cld <= '0';

               elsif ((d_i = X"C0" or

                      d_i = X"C4" or

                      d_i = X"CC") and (rdy_i = '1')) then

                  sel_rb_out_o_i_cld <= "010";

                  sig_PC <= adr_nxt_pc_i;

                  sel_alu_out_o_i_cld <= "110";

                  sel_alu_as_o_i_cld <= '0';

               elsif ((d_i = X"C6" or

                      d_i = X"D6" or

                      d_i = X"CE" or

                      d_i = X"DE") and (rdy_i = '1')) then

                  zw_b4 <= X"FF";

                  sig_PC <= adr_nxt_pc_i;

                  sel_alu_out_o_i_cld <= "110";

                  sel_alu_as_o_i_cld <= '0';

               elsif ((d_i = X"CA") and (rdy_i = '1')) then

                  sel_rb_out_o_i_cld <= "001";

                  sel_reg_o_i_cld <= "01";

                  sel_rb_in_o_i_cld <= "011";

                  zw_b4 <= X"FF";

                  sel_alu_out_o_i_cld <= "110";

                  sel_alu_as_o_i_cld <= '0';

               elsif ((d_i = X"88") and (rdy_i = '1')) then

                  sel_rb_out_o_i_cld <= "010";

                  sel_reg_o_i_cld <= "10";

                  sel_rb_in_o_i_cld <= "011";

                  zw_b4 <= X"FF";

                  sel_alu_out_o_i_cld <= "110";

                  sel_alu_as_o_i_cld <= '0';

               elsif ((d_i = X"49" or

                      d_i = X"45" or

                      d_i = X"55" or

                      d_i = X"4D" or

                      d_i = X"5D" or

                      d_i = X"59" or

                      d_i = X"41" or

                      d_i = X"51" or

                      d_i = X"09" or

                      d_i = X"05" or

                      d_i = X"15" or

                      d_i = X"0D" or

                      d_i = X"1D" or

                      d_i = X"19" or

                      d_i = X"01" or

                      d_i = X"11" or

                      d_i = X"29" or

                      d_i = X"25" or

                      d_i = X"35" or

                      d_i = X"2D" or

                      d_i = X"3D" or

                      d_i = X"39" or

                      d_i = X"21" or

                      d_i = X"31" or

                      d_i = X"C9" or

                      d_i = X"C5" or

                      d_i = X"D5" or

                      d_i = X"CD" or

                      d_i = X"DD" or

                      d_i = X"D9" or

                      d_i = X"C1" or

                      d_i = X"D1") and (rdy_i = '1')) then

                  sel_rb_out_o_i_cld <= "000";

                  sel_reg_o_i_cld <= "00";

                  sel_rb_in_o_i_cld <= "011";

                  sel_alu_out_o_i_cld <= "110";

                  sel_alu_as_o_i_cld <= '0';

                  sig_PC <= adr_nxt_pc_i;

                  sel_alu_out_o_i_cld <= "110";

                  sel_alu_as_o_i_cld <= '0';

               elsif ((d_i = X"E6" or

                      d_i = X"F6" or

                      d_i = X"EE" or

                      d_i = X"FE") and (rdy_i = '1')) then

                  zw_b4 <= X"01";

                  sig_PC <= adr_nxt_pc_i;

                  sel_alu_out_o_i_cld <= "110";

                  sel_alu_as_o_i_cld <= '0';

               elsif ((d_i = X"E8") and (rdy_i = '1')) then

                  sel_rb_out_o_i_cld <= "001";

                  sel_reg_o_i_cld <= "01";

                  sel_rb_in_o_i_cld <= "011";

                  zw_b4 <= X"01";

                  sel_alu_out_o_i_cld <= "110";

                  sel_alu_as_o_i_cld <= '0';

               elsif ((d_i = X"C8") and (rdy_i = '1')) then

                  sel_rb_out_o_i_cld <= "010";

                  sel_reg_o_i_cld <= "10";

                  sel_rb_in_o_i_cld <= "011";

                  zw_b4 <= X"01";

                  sel_alu_out_o_i_cld <= "110";

                  sel_alu_as_o_i_cld <= '0';

               elsif ((d_i = X"4C" or

                      d_i = X"6C") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"20") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"A9" or

                      d_i = X"A5" or

                      d_i = X"B5" or

                      d_i = X"AD" or

                      d_i = X"BD" or

                      d_i = X"B9" or

                      d_i = X"A1" or

                      d_i = X"B1") and (rdy_i = '1')) then

                  sel_reg_o_i_cld <= "00";

                  sel_rb_in_o_i_cld <= "011";

                  sel_alu_out_o_i_cld <= "110";

                  sel_alu_as_o_i_cld <= '0';

                  sig_PC <= adr_nxt_pc_i;

                  sel_alu_out_o_i_cld <= "110";

                  sel_alu_as_o_i_cld <= '0';

               elsif ((d_i = X"A2" or

                      d_i = X"A6" or

                      d_i = X"B6" or

                      d_i = X"AE" or

                      d_i = X"BE") and (rdy_i = '1')) then

                  sel_reg_o_i_cld <= "01";

                  sel_rb_in_o_i_cld <= "011";