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https://opencores.org/ocsvn/cpu6502_true_cycle/cpu6502_true_cycle/trunk
[/] [cpu6502_true_cycle/] [trunk/] [TO_DO_list.txt] - Blame information for rev 18
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Rev |
Author |
Line |
| 1 |
15 |
fpga_is_fu |
(February 25th 2009)
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| 2 |
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- (DONE) CORRECTED "RTI" (wrong: use of stack pointer)
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| 3 |
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- (DONE) RENAME all states of "FSM Execution Unit" for better reading
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| 4 |
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- (90%) Finish working for Specification of cpu6502_tc
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| 5 |
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| 6 |
6 |
fpga_is_fu |
(January, 4th 2009)
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| 7 |
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- (DONE) Remove unused nets, register and modules
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| 8 |
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- (85%) Finish working for Specification of cpu65C02_tc
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| 9 |
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- (DONE) Update the HDL Designer files for better viewing and
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| 10 |
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understanding
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| 11 |
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| 12 |
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(August, 5th 2008)
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| 13 |
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- (DONE) Rename all port names (_i, _o, _o_i)
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| 14 |
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- (DONE) Test and verify all Op Codes
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| 15 |
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- (DONE) Optimize core for speed
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| 16 |
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- (75%) Finish working for Specification of cpu65C02_tc
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| 17 |
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- (WORKING) Create high level testbench in assembler and hardware for
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| 18 |
2 |
fpga_is_fu |
testing all Op Codes (include accurate cycle timing)
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| 19 |
6 |
fpga_is_fu |
- (WORKING) Create simulation files for Modelsim
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| 20 |
15 |
fpga_is_fu |
- (WORKING) Create a simple .wlf file to demonstrate the cpu6502_tc
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| 21 |
2 |
fpga_is_fu |
- Update the HDL Designer files for better viewing and understanding
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