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[/] [cpu6502_true_cycle/] [trunk/] [doc/] [errata.txt] - Blame information for rev 25

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v1.11 BETA 2013/07/24
FUNCTIONALITY:
- ADC and SBC in decimal mode (all op codes -
  seems to use a formula different from a real R6502.
 
TIMING:
- All Branch Instructions
  (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS)
  4 cycles if branch forward occur and the branch
  instruction lies on a xxFEh location.
  Must be 3 cycles.
 
SIGNALING:
- Hardware Interrupts NMI & IRQ - NO "SYNC"
- RESET generates NO SYNC

Line No.	Rev	Author	Line
1	25	fpga_is_fu	`v1.11 BETA 2013/07/24`
2			`FUNCTIONALITY:`
3			`- ADC and SBC in decimal mode (all op codes -`
4			`seems to use a formula different from a real R6502.`
5
6			`TIMING:`
7			`- All Branch Instructions`
8			`(BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS)`
9			`4 cycles if branch forward occur and the branch`
10			`instruction lies on a xxFEh location.`
11			`Must be 3 cycles.`
12
13			`SIGNALING:`
14			`- Hardware Interrupts NMI & IRQ - NO "SYNC"`
15			`- RESET generates NO SYNC`

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[/] [cpu6502_true_cycle/] [trunk/] [doc/] [errata.txt] - Blame information for rev 25