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-- VHDL Entity R6502_TC.Core.symbol
--
-- Created:
--          by - eda.UNKNOWN (TEST)
--          at - 19:21:54 07.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY Core IS
   PORT(
      clk_clk_i   : IN     std_logic;
      d_i         : IN     std_logic_vector (7 DOWNTO 0);
      irq_n_i     : IN     std_logic;
      nmi_n_i     : IN     std_logic;
      rdy_i       : IN     std_logic;
      rst_rst_n_i : IN     std_logic;
      so_n_i      : IN     std_logic;
      a_o         : OUT    std_logic_vector (15 DOWNTO 0);
      d_o         : OUT    std_logic_vector (7 DOWNTO 0);
      rd_o        : OUT    std_logic;
      sync_o      : OUT    std_logic;
      wr_n_o      : OUT    std_logic;
      wr_o        : OUT    std_logic
   );
 
-- Declarations
 
END Core ;
 
-- Jens-D. Gutschmidt     Project:  R6502_TC  
-- scantara2003@yahoo.de                      
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG                                                                                                                                  
--                                                                                                                                                                                          
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version   
-- 3 of the License, or any later version.                                                                                                                                                  
--                                                                                                                                                                                          
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A                          
-- PARTICULAR PURPOSE.  See the GNU General Public License for more details.                                                                                                                
--                                                                                                                                                                                          
-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.                                                  
--                                                                                                                                                                                          
-- CVS Revisins History                                                                                                                                                                     
--                                                                                                                                                                                          
-- $Log: not supported by cvs2svn $                                                                                                                                                                      
--   <<-- more -->>                                                                                                                                                                         
-- Title:  Core  
-- Path:  R6502_TC/Core/struct  
-- Edited:  by eda on 07 Jan 2009  
--
-- VHDL Architecture R6502_TC.Core.struct
--
-- Created:
--          by - eda.UNKNOWN (TEST)
--          at - 19:21:55 07.01.2009
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
 
ARCHITECTURE struct OF Core IS
 
   -- Architecture declarations
 
   -- Internal signal declarations
   SIGNAL adr_nxt_pc_o_i : std_logic_vector(15 DOWNTO 0);
   SIGNAL adr_o_i        : std_logic_vector(15 DOWNTO 0);
   SIGNAL adr_pc_o_i     : std_logic_vector(15 DOWNTO 0);
   SIGNAL adr_sp_o_i     : std_logic_vector(15 DOWNTO 0);
   SIGNAL ch_a_o_i       : std_logic_vector(7 DOWNTO 0);
   SIGNAL ch_b_o_i       : std_logic_vector(7 DOWNTO 0);
   SIGNAL d_alu_n_o_i    : std_logic;
   SIGNAL d_alu_o_i      : std_logic_vector(7 DOWNTO 0);
   SIGNAL d_alu_or_o_i   : std_logic;
   SIGNAL d_regs_in_o_i  : std_logic_vector(7 DOWNTO 0);
   SIGNAL d_regs_out_o_i : std_logic_vector(7 DOWNTO 0);
   SIGNAL fetch_o_i      : std_logic;
   SIGNAL ld_o_i         : std_logic_vector(1 DOWNTO 0);
   SIGNAL ld_pc_o_i      : std_logic;
   SIGNAL ld_sp_o_i      : std_logic;
   SIGNAL load_regs_o_i  : std_logic;
   SIGNAL nmi_o_i        : std_logic;
   SIGNAL offset_o_i     : std_logic_vector(15 DOWNTO 0);
   SIGNAL q_a_o_i        : std_logic_vector(7 DOWNTO 0);
   SIGNAL q_x_o_i        : std_logic_vector(7 DOWNTO 0);
   SIGNAL q_y_o_i        : std_logic_vector(7 DOWNTO 0);
   SIGNAL reg_0flag_o_i  : std_logic;
   SIGNAL reg_1flag_o_i  : std_logic;
   SIGNAL reg_7flag_o_i  : std_logic;
   SIGNAL sel_pc_in_o_i  : std_logic;
   SIGNAL sel_pc_val_o_i : std_logic_vector(1 DOWNTO 0);
   SIGNAL sel_rb_in_o_i  : std_logic_vector(1 DOWNTO 0);
   SIGNAL sel_rb_out_o_i : std_logic_vector(1 DOWNTO 0);
   SIGNAL sel_reg_o_i    : std_logic_vector(1 DOWNTO 0);
   SIGNAL sel_sp_as_o_i  : std_logic;
   SIGNAL sel_sp_in_o_i  : std_logic;
 
 
   -- Component Declarations
   COMPONENT FSM_Execution_Unit
   PORT (
      adr_nxt_pc_i : IN     std_logic_vector (15 DOWNTO 0);
      adr_pc_i     : IN     std_logic_vector (15 DOWNTO 0);
      adr_sp_i     : IN     std_logic_vector (15 DOWNTO 0);
      clk_clk_i    : IN     std_logic ;
      d_alu_i      : IN     std_logic_vector ( 7 DOWNTO 0 );
      d_i          : IN     std_logic_vector ( 7 DOWNTO 0 );
      d_regs_out_i : IN     std_logic_vector ( 7 DOWNTO 0 );
      irq_n_i      : IN     std_logic ;
      nmi_i        : IN     std_logic ;
      q_a_i        : IN     std_logic_vector ( 7 DOWNTO 0 );
      q_x_i        : IN     std_logic_vector ( 7 DOWNTO 0 );
      q_y_i        : IN     std_logic_vector ( 7 DOWNTO 0 );
      rdy_i        : IN     std_logic ;
      reg_0flag_i  : IN     std_logic ;
      reg_1flag_i  : IN     std_logic ;
      reg_7flag_i  : IN     std_logic ;
      rst_rst_n_i  : IN     std_logic ;
      so_n_i       : IN     std_logic ;
      a_o          : OUT    std_logic_vector (15 DOWNTO 0);
      adr_o        : OUT    std_logic_vector (15 DOWNTO 0);
      ch_a_o       : OUT    std_logic_vector ( 7 DOWNTO 0 );
      ch_b_o       : OUT    std_logic_vector ( 7 DOWNTO 0 );
      d_o          : OUT    std_logic_vector ( 7 DOWNTO 0 );
      d_regs_in_o  : OUT    std_logic_vector ( 7 DOWNTO 0 );
      fetch_o      : OUT    std_logic ;
      ld_o         : OUT    std_logic_vector ( 1 DOWNTO 0 );
      ld_pc_o      : OUT    std_logic ;
      ld_sp_o      : OUT    std_logic ;
      load_regs_o  : OUT    std_logic ;
      offset_o     : OUT    std_logic_vector ( 15 DOWNTO 0 );
      rd_o         : OUT    std_logic ;
      sel_pc_in_o  : OUT    std_logic ;
      sel_pc_val_o : OUT    std_logic_vector ( 1 DOWNTO 0 );
      sel_rb_in_o  : OUT    std_logic_vector ( 1 DOWNTO 0 );
      sel_rb_out_o : OUT    std_logic_vector ( 1 DOWNTO 0 );
      sel_reg_o    : OUT    std_logic_vector ( 1 DOWNTO 0 );
      sel_sp_as_o  : OUT    std_logic ;
      sel_sp_in_o  : OUT    std_logic ;
      sync_o       : OUT    std_logic ;
      wr_n_o       : OUT    std_logic ;
      wr_o         : OUT    std_logic
   );
   END COMPONENT;
   COMPONENT FSM_NMI
   PORT (
      clk_clk_i   : IN     std_logic ;
      fetch_i     : IN     std_logic ;
      nmi_n_i     : IN     std_logic ;
      rst_rst_n_i : IN     std_logic ;
      nmi_o       : OUT    std_logic
   );
   END COMPONENT;
   COMPONENT RegBank_AXY
   PORT (
      clk_clk_i    : IN     std_logic ;
      d_regs_in_i  : IN     std_logic_vector (7 DOWNTO 0);
      load_regs_i  : IN     std_logic ;
      rst_rst_n_i  : IN     std_logic ;
      sel_rb_in_i  : IN     std_logic_vector (1 DOWNTO 0);
      sel_rb_out_i : IN     std_logic_vector (1 DOWNTO 0);
      sel_reg_i    : IN     std_logic_vector (1 DOWNTO 0);
      d_regs_out_o : OUT    std_logic_vector (7 DOWNTO 0);
      q_a_o        : OUT    std_logic_vector (7 DOWNTO 0);
      q_x_o        : OUT    std_logic_vector (7 DOWNTO 0);
      q_y_o        : OUT    std_logic_vector (7 DOWNTO 0)
   );
   END COMPONENT;
   COMPONENT Reg_PC
   PORT (
      adr_i        : IN     std_logic_vector (15 DOWNTO 0);
      clk_clk_i    : IN     std_logic ;
      ld_i         : IN     std_logic_vector (1 DOWNTO 0);
      ld_pc_i      : IN     std_logic ;
      offset_i     : IN     std_logic_vector (15 DOWNTO 0);
      rst_rst_n_i  : IN     std_logic ;
      sel_pc_in_i  : IN     std_logic ;
      sel_pc_val_i : IN     std_logic_vector (1 DOWNTO 0);
      adr_nxt_pc_o : OUT    std_logic_vector (15 DOWNTO 0);
      adr_pc_o     : OUT    std_logic_vector (15 DOWNTO 0)
   );
   END COMPONENT;
   COMPONENT Reg_SP
   PORT (
      adr_low_i   : IN     std_logic_vector (7 DOWNTO 0);
      clk_clk_i   : IN     std_logic ;
      ld_low_i    : IN     std_logic ;
      ld_sp_i     : IN     std_logic ;
      rst_rst_n_i : IN     std_logic ;
      sel_sp_as_i : IN     std_logic ;
      sel_sp_in_i : IN     std_logic ;
      adr_sp_o    : OUT    std_logic_vector (15 DOWNTO 0)
   );
   END COMPONENT;
 
 
BEGIN
 
   -- ModuleWare code(v1.9) for instance 'U_11' of 'add'
   u_11combo_proc: PROCESS (ch_a_o_i, ch_b_o_i)
   VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);
   VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);
   VARIABLE temp_sum : unsigned(8 DOWNTO 0);
   VARIABLE temp_carry : std_logic;
   BEGIN
      temp_din0 := '0' & ch_a_o_i;
      temp_din1 := '0' & ch_b_o_i;
      temp_carry := '0';
      temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
      d_alu_o_i <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
      reg_0flag_o_i <= temp_sum(8) ;
   END PROCESS u_11combo_proc;
 
   -- ModuleWare code(v1.9) for instance 'U_8' of 'inv'
   reg_1flag_o_i <= NOT(d_alu_or_o_i);
 
   -- ModuleWare code(v1.9) for instance 'U_9' of 'inv'
   reg_7flag_o_i <= NOT(d_alu_n_o_i);
 
   -- ModuleWare code(v1.9) for instance 'U_10' of 'inv'
   d_alu_n_o_i <= NOT(d_alu_o_i(7));
 
   -- ModuleWare code(v1.9) for instance 'U_7' of 'por'
   d_alu_or_o_i <= d_alu_o_i(0) OR  d_alu_o_i(1) OR  d_alu_o_i(2) OR  d_alu_o_i(3) OR  d_alu_o_i(4) OR  d_alu_o_i(5) OR  d_alu_o_i(6) OR  d_alu_o_i(7);
 
   -- Instance port mappings.
   U_4 : FSM_Execution_Unit
      PORT MAP (
         adr_nxt_pc_i => adr_nxt_pc_o_i,
         adr_pc_i     => adr_pc_o_i,
         adr_sp_i     => adr_sp_o_i,
         clk_clk_i    => clk_clk_i,
         d_alu_i      => d_alu_o_i,
         d_i          => d_i,
         d_regs_out_i => d_regs_out_o_i,
         irq_n_i      => irq_n_i,
         nmi_i        => nmi_o_i,
         q_a_i        => q_a_o_i,
         q_x_i        => q_x_o_i,
         q_y_i        => q_y_o_i,
         rdy_i        => rdy_i,
         reg_0flag_i  => reg_0flag_o_i,
         reg_1flag_i  => reg_1flag_o_i,
         reg_7flag_i  => reg_7flag_o_i,
         rst_rst_n_i  => rst_rst_n_i,
         so_n_i       => so_n_i,
         a_o          => a_o,
         adr_o        => adr_o_i,
         ch_a_o       => ch_a_o_i,
         ch_b_o       => ch_b_o_i,
         d_o          => d_o,
         d_regs_in_o  => d_regs_in_o_i,
         fetch_o      => fetch_o_i,
         ld_o         => ld_o_i,
         ld_pc_o      => ld_pc_o_i,
         ld_sp_o      => ld_sp_o_i,
         load_regs_o  => load_regs_o_i,
         offset_o     => offset_o_i,
         rd_o         => rd_o,
         sel_pc_in_o  => sel_pc_in_o_i,
         sel_pc_val_o => sel_pc_val_o_i,
         sel_rb_in_o  => sel_rb_in_o_i,
         sel_rb_out_o => sel_rb_out_o_i,
         sel_reg_o    => sel_reg_o_i,
         sel_sp_as_o  => sel_sp_as_o_i,
         sel_sp_in_o  => sel_sp_in_o_i,
         sync_o       => sync_o,
         wr_n_o       => wr_n_o,
         wr_o         => wr_o
      );
   U_6 : FSM_NMI
      PORT MAP (
         clk_clk_i   => clk_clk_i,
         fetch_i     => fetch_o_i,
         nmi_n_i     => nmi_n_i,
         rst_rst_n_i => rst_rst_n_i,
         nmi_o       => nmi_o_i
      );
   U_2 : RegBank_AXY
      PORT MAP (
         clk_clk_i    => clk_clk_i,
         d_regs_in_i  => d_regs_in_o_i,
         load_regs_i  => load_regs_o_i,
         rst_rst_n_i  => rst_rst_n_i,
         sel_rb_in_i  => sel_rb_in_o_i,
         sel_rb_out_i => sel_rb_out_o_i,
         sel_reg_i    => sel_reg_o_i,
         d_regs_out_o => d_regs_out_o_i,
         q_a_o        => q_a_o_i,
         q_x_o        => q_x_o_i,
         q_y_o        => q_y_o_i
      );
   U_0 : Reg_PC
      PORT MAP (
         adr_i        => adr_o_i,
         clk_clk_i    => clk_clk_i,
         ld_i         => ld_o_i,
         ld_pc_i      => ld_pc_o_i,
         offset_i     => offset_o_i,
         rst_rst_n_i  => rst_rst_n_i,
         sel_pc_in_i  => sel_pc_in_o_i,
         sel_pc_val_i => sel_pc_val_o_i,
         adr_nxt_pc_o => adr_nxt_pc_o_i,
         adr_pc_o     => adr_pc_o_i
      );
   U_1 : Reg_SP
      PORT MAP (
         adr_low_i   => adr_o_i(7 DOWNTO 0),
         clk_clk_i   => clk_clk_i,
         ld_low_i    => ld_o_i(0),
         ld_sp_i     => ld_sp_o_i,
         rst_rst_n_i => rst_rst_n_i,
         sel_sp_as_i => sel_sp_as_o_i,
         sel_sp_in_i => sel_sp_in_o_i,
         adr_sp_o    => adr_sp_o_i
      );
 
END struct;

Line No.	Rev	Author	Line
1	2	fpga_is_fu	`-- VHDL Entity R6502_TC.Core.symbol`
2			`--`
3			`-- Created:`
4	14	fpga_is_fu	`-- by - eda.UNKNOWN (TEST)`
5			`-- at - 19:21:54 07.01.2009`
6	2	fpga_is_fu	`--`
7			`-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)`
8			`--`
9			`LIBRARY ieee;`
10			`USE ieee.std_logic_1164.all;`
11			`USE ieee.std_logic_arith.all;`
12
13	14	fpga_is_fu	`ENTITY Core IS`
14			`PORT(`
15			`clk_clk_i : IN std_logic;`
16			`d_i : IN std_logic_vector (7 DOWNTO 0);`
17			`irq_n_i : IN std_logic;`
18			`nmi_n_i : IN std_logic;`
19			`rdy_i : IN std_logic;`
20			`rst_rst_n_i : IN std_logic;`
21			`so_n_i : IN std_logic;`
22			`a_o : OUT std_logic_vector (15 DOWNTO 0);`
23			`d_o : OUT std_logic_vector (7 DOWNTO 0);`
24			`rd_o : OUT std_logic;`
25			`sync_o : OUT std_logic;`
26			`wr_n_o : OUT std_logic;`
27			`wr_o : OUT std_logic`
28	2	fpga_is_fu	`);`
29
30			`-- Declarations`
31
32	14	fpga_is_fu	`END Core ;`
33	2	fpga_is_fu
34			`-- Jens-D. Gutschmidt Project: R6502_TC`
35			`-- scantara2003@yahoo.de`
36			`-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG`
37			`--`
38			`-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version`
39			`-- 3 of the License, or any later version.`
40			`--`
41			`-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A`
42			`-- PARTICULAR PURPOSE. See the GNU General Public License for more details.`
43			`--`
44			`-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.`
45			`--`
46			`-- CVS Revisins History`
47			`--`
48	11	fpga_is_fu	`-- $Log: not supported by cvs2svn $`
49			`-- <<-- more -->>`
50			`-- Title: Core`
51	2	fpga_is_fu	`-- Path: R6502_TC/Core/struct`
52	14	fpga_is_fu	`-- Edited: by eda on 07 Jan 2009`
53	2	fpga_is_fu	`--`
54			`-- VHDL Architecture R6502_TC.Core.struct`
55			`--`
56			`-- Created:`
57	14	fpga_is_fu	`-- by - eda.UNKNOWN (TEST)`
58			`-- at - 19:21:55 07.01.2009`
59	2	fpga_is_fu	`--`
60			`-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)`
61			`--`
62			`LIBRARY ieee;`
63			`USE ieee.std_logic_1164.all;`
64			`USE ieee.std_logic_arith.all;`
65
66
67	14	fpga_is_fu	`ARCHITECTURE struct OF Core IS`
68	2	fpga_is_fu
69			`-- Architecture declarations`
70
71			`-- Internal signal declarations`
72	14	fpga_is_fu	`SIGNAL adr_nxt_pc_o_i : std_logic_vector(15 DOWNTO 0);`
73			`SIGNAL adr_o_i : std_logic_vector(15 DOWNTO 0);`
74			`SIGNAL adr_pc_o_i : std_logic_vector(15 DOWNTO 0);`
75			`SIGNAL adr_sp_o_i : std_logic_vector(15 DOWNTO 0);`
76			`SIGNAL ch_a_o_i : std_logic_vector(7 DOWNTO 0);`
77			`SIGNAL ch_b_o_i : std_logic_vector(7 DOWNTO 0);`
78			`SIGNAL d_alu_n_o_i : std_logic;`
79			`SIGNAL d_alu_o_i : std_logic_vector(7 DOWNTO 0);`
80			`SIGNAL d_alu_or_o_i : std_logic;`
81			`SIGNAL d_regs_in_o_i : std_logic_vector(7 DOWNTO 0);`
82			`SIGNAL d_regs_out_o_i : std_logic_vector(7 DOWNTO 0);`
83			`SIGNAL fetch_o_i : std_logic;`
84			`SIGNAL ld_o_i : std_logic_vector(1 DOWNTO 0);`
85			`SIGNAL ld_pc_o_i : std_logic;`
86			`SIGNAL ld_sp_o_i : std_logic;`
87			`SIGNAL load_regs_o_i : std_logic;`
88			`SIGNAL nmi_o_i : std_logic;`
89			`SIGNAL offset_o_i : std_logic_vector(15 DOWNTO 0);`
90			`SIGNAL q_a_o_i : std_logic_vector(7 DOWNTO 0);`
91			`SIGNAL q_x_o_i : std_logic_vector(7 DOWNTO 0);`
92			`SIGNAL q_y_o_i : std_logic_vector(7 DOWNTO 0);`
93			`SIGNAL reg_0flag_o_i : std_logic;`
94			`SIGNAL reg_1flag_o_i : std_logic;`
95			`SIGNAL reg_7flag_o_i : std_logic;`
96			`SIGNAL sel_pc_in_o_i : std_logic;`
97			`SIGNAL sel_pc_val_o_i : std_logic_vector(1 DOWNTO 0);`
98			`SIGNAL sel_rb_in_o_i : std_logic_vector(1 DOWNTO 0);`
99			`SIGNAL sel_rb_out_o_i : std_logic_vector(1 DOWNTO 0);`
100			`SIGNAL sel_reg_o_i : std_logic_vector(1 DOWNTO 0);`
101			`SIGNAL sel_sp_as_o_i : std_logic;`
102			`SIGNAL sel_sp_in_o_i : std_logic;`
103	2	fpga_is_fu
104
105			`-- Component Declarations`
106	14	fpga_is_fu	`COMPONENT FSM_Execution_Unit`
107			`PORT (`
108			`adr_nxt_pc_i : IN std_logic_vector (15 DOWNTO 0);`
109			`adr_pc_i : IN std_logic_vector (15 DOWNTO 0);`
110			`adr_sp_i : IN std_logic_vector (15 DOWNTO 0);`
111			`clk_clk_i : IN std_logic ;`
112			`d_alu_i : IN std_logic_vector ( 7 DOWNTO 0 );`
113			`d_i : IN std_logic_vector ( 7 DOWNTO 0 );`
114			`d_regs_out_i : IN std_logic_vector ( 7 DOWNTO 0 );`
115			`irq_n_i : IN std_logic ;`
116			`nmi_i : IN std_logic ;`
117			`q_a_i : IN std_logic_vector ( 7 DOWNTO 0 );`
118			`q_x_i : IN std_logic_vector ( 7 DOWNTO 0 );`
119			`q_y_i : IN std_logic_vector ( 7 DOWNTO 0 );`
120			`rdy_i : IN std_logic ;`
121			`reg_0flag_i : IN std_logic ;`
122			`reg_1flag_i : IN std_logic ;`
123			`reg_7flag_i : IN std_logic ;`
124			`rst_rst_n_i : IN std_logic ;`
125			`so_n_i : IN std_logic ;`
126			`a_o : OUT std_logic_vector (15 DOWNTO 0);`
127			`adr_o : OUT std_logic_vector (15 DOWNTO 0);`
128			`ch_a_o : OUT std_logic_vector ( 7 DOWNTO 0 );`
129			`ch_b_o : OUT std_logic_vector ( 7 DOWNTO 0 );`
130			`d_o : OUT std_logic_vector ( 7 DOWNTO 0 );`
131			`d_regs_in_o : OUT std_logic_vector ( 7 DOWNTO 0 );`
132			`fetch_o : OUT std_logic ;`
133			`ld_o : OUT std_logic_vector ( 1 DOWNTO 0 );`
134			`ld_pc_o : OUT std_logic ;`
135			`ld_sp_o : OUT std_logic ;`
136			`load_regs_o : OUT std_logic ;`
137			`offset_o : OUT std_logic_vector ( 15 DOWNTO 0 );`
138			`rd_o : OUT std_logic ;`
139			`sel_pc_in_o : OUT std_logic ;`
140			`sel_pc_val_o : OUT std_logic_vector ( 1 DOWNTO 0 );`
141			`sel_rb_in_o : OUT std_logic_vector ( 1 DOWNTO 0 );`
142			`sel_rb_out_o : OUT std_logic_vector ( 1 DOWNTO 0 );`
143			`sel_reg_o : OUT std_logic_vector ( 1 DOWNTO 0 );`
144			`sel_sp_as_o : OUT std_logic ;`
145			`sel_sp_in_o : OUT std_logic ;`
146			`sync_o : OUT std_logic ;`
147			`wr_n_o : OUT std_logic ;`
148			`wr_o : OUT std_logic`
149	2	fpga_is_fu	`);`
150	14	fpga_is_fu	`END COMPONENT;`
151			`COMPONENT FSM_NMI`
152			`PORT (`
153			`clk_clk_i : IN std_logic ;`
154			`fetch_i : IN std_logic ;`
155			`nmi_n_i : IN std_logic ;`
156			`rst_rst_n_i : IN std_logic ;`
157			`nmi_o : OUT std_logic`
158	11	fpga_is_fu	`);`
159	14	fpga_is_fu	`END COMPONENT;`
160			`COMPONENT RegBank_AXY`
161			`PORT (`
162			`clk_clk_i : IN std_logic ;`
163			`d_regs_in_i : IN std_logic_vector (7 DOWNTO 0);`
164			`load_regs_i : IN std_logic ;`
165			`rst_rst_n_i : IN std_logic ;`
166			`sel_rb_in_i : IN std_logic_vector (1 DOWNTO 0);`
167			`sel_rb_out_i : IN std_logic_vector (1 DOWNTO 0);`
168			`sel_reg_i : IN std_logic_vector (1 DOWNTO 0);`
169			`d_regs_out_o : OUT std_logic_vector (7 DOWNTO 0);`
170			`q_a_o : OUT std_logic_vector (7 DOWNTO 0);`
171			`q_x_o : OUT std_logic_vector (7 DOWNTO 0);`
172			`q_y_o : OUT std_logic_vector (7 DOWNTO 0)`
173	2	fpga_is_fu	`);`
174	14	fpga_is_fu	`END COMPONENT;`
175			`COMPONENT Reg_PC`
176			`PORT (`
177			`adr_i : IN std_logic_vector (15 DOWNTO 0);`
178			`clk_clk_i : IN std_logic ;`
179			`ld_i : IN std_logic_vector (1 DOWNTO 0);`
180			`ld_pc_i : IN std_logic ;`
181			`offset_i : IN std_logic_vector (15 DOWNTO 0);`
182			`rst_rst_n_i : IN std_logic ;`
183			`sel_pc_in_i : IN std_logic ;`
184			`sel_pc_val_i : IN std_logic_vector (1 DOWNTO 0);`
185			`adr_nxt_pc_o : OUT std_logic_vector (15 DOWNTO 0);`
186			`adr_pc_o : OUT std_logic_vector (15 DOWNTO 0)`
187	2	fpga_is_fu	`);`
188	14	fpga_is_fu	`END COMPONENT;`
189			`COMPONENT Reg_SP`
190			`PORT (`
191			`adr_low_i : IN std_logic_vector (7 DOWNTO 0);`
192			`clk_clk_i : IN std_logic ;`
193			`ld_low_i : IN std_logic ;`
194			`ld_sp_i : IN std_logic ;`
195			`rst_rst_n_i : IN std_logic ;`
196			`sel_sp_as_i : IN std_logic ;`
197			`sel_sp_in_i : IN std_logic ;`
198			`adr_sp_o : OUT std_logic_vector (15 DOWNTO 0)`
199	5	fpga_is_fu	`);`
200	14	fpga_is_fu	`END COMPONENT;`
201	2	fpga_is_fu
202
203	14	fpga_is_fu	`BEGIN`
204	2	fpga_is_fu
205	11	fpga_is_fu	`-- ModuleWare code(v1.9) for instance 'U_11' of 'add'`
206	14	fpga_is_fu	`u_11combo_proc: PROCESS (ch_a_o_i, ch_b_o_i)`
207			`VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);`
208			`VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);`
209			`VARIABLE temp_sum : unsigned(8 DOWNTO 0);`
210			`VARIABLE temp_carry : std_logic;`
211			`BEGIN`
212			`temp_din0 := '0' & ch_a_o_i;`
213			`temp_din1 := '0' & ch_b_o_i;`
214	11	fpga_is_fu	`temp_carry := '0';`
215	14	fpga_is_fu	`temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;`
216			`d_alu_o_i <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);`
217			`reg_0flag_o_i <= temp_sum(8) ;`
218			`END PROCESS u_11combo_proc;`
219	2	fpga_is_fu
220	11	fpga_is_fu	`-- ModuleWare code(v1.9) for instance 'U_8' of 'inv'`
221	14	fpga_is_fu	`reg_1flag_o_i <= NOT(d_alu_or_o_i);`
222	11	fpga_is_fu
223			`-- ModuleWare code(v1.9) for instance 'U_9' of 'inv'`
224	14	fpga_is_fu	`reg_7flag_o_i <= NOT(d_alu_n_o_i);`
225	11	fpga_is_fu
226			`-- ModuleWare code(v1.9) for instance 'U_10' of 'inv'`
227	14	fpga_is_fu	`d_alu_n_o_i <= NOT(d_alu_o_i(7));`
228	11	fpga_is_fu
229			`-- ModuleWare code(v1.9) for instance 'U_7' of 'por'`
230	14	fpga_is_fu	`d_alu_or_o_i <= d_alu_o_i(0) OR d_alu_o_i(1) OR d_alu_o_i(2) OR d_alu_o_i(3) OR d_alu_o_i(4) OR d_alu_o_i(5) OR d_alu_o_i(6) OR d_alu_o_i(7);`
231	11	fpga_is_fu
232	2	fpga_is_fu	`-- Instance port mappings.`
233	11	fpga_is_fu	`U_4 : FSM_Execution_Unit`
234	14	fpga_is_fu	`PORT MAP (`
235	11	fpga_is_fu	`adr_nxt_pc_i => adr_nxt_pc_o_i,`
236			`adr_pc_i => adr_pc_o_i,`
237			`adr_sp_i => adr_sp_o_i,`
238			`clk_clk_i => clk_clk_i,`
239			`d_alu_i => d_alu_o_i,`
240			`d_i => d_i,`
241			`d_regs_out_i => d_regs_out_o_i,`
242			`irq_n_i => irq_n_i,`
243			`nmi_i => nmi_o_i,`
244			`q_a_i => q_a_o_i,`
245			`q_x_i => q_x_o_i,`
246			`q_y_i => q_y_o_i,`
247			`rdy_i => rdy_i,`
248			`reg_0flag_i => reg_0flag_o_i,`
249			`reg_1flag_i => reg_1flag_o_i,`
250			`reg_7flag_i => reg_7flag_o_i,`
251			`rst_rst_n_i => rst_rst_n_i,`
252			`so_n_i => so_n_i,`
253			`a_o => a_o,`
254			`adr_o => adr_o_i,`
255			`ch_a_o => ch_a_o_i,`
256			`ch_b_o => ch_b_o_i,`
257			`d_o => d_o,`
258			`d_regs_in_o => d_regs_in_o_i,`
259			`fetch_o => fetch_o_i,`
260			`ld_o => ld_o_i,`
261			`ld_pc_o => ld_pc_o_i,`
262			`ld_sp_o => ld_sp_o_i,`
263			`load_regs_o => load_regs_o_i,`
264			`offset_o => offset_o_i,`
265			`rd_o => rd_o,`
266			`sel_pc_in_o => sel_pc_in_o_i,`
267			`sel_pc_val_o => sel_pc_val_o_i,`
268			`sel_rb_in_o => sel_rb_in_o_i,`
269			`sel_rb_out_o => sel_rb_out_o_i,`
270			`sel_reg_o => sel_reg_o_i,`
271			`sel_sp_as_o => sel_sp_as_o_i,`
272			`sel_sp_in_o => sel_sp_in_o_i,`
273			`sync_o => sync_o,`
274			`wr_n_o => wr_n_o,`
275			`wr_o => wr_o`
276	2	fpga_is_fu	`);`
277	11	fpga_is_fu	`U_6 : FSM_NMI`
278	14	fpga_is_fu	`PORT MAP (`
279	11	fpga_is_fu	`clk_clk_i => clk_clk_i,`
280			`fetch_i => fetch_o_i,`
281			`nmi_n_i => nmi_n_i,`
282			`rst_rst_n_i => rst_rst_n_i,`
283			`nmi_o => nmi_o_i`
284			`);`
285	2	fpga_is_fu	`U_2 : RegBank_AXY`
286	14	fpga_is_fu	`PORT MAP (`
287	2	fpga_is_fu	`clk_clk_i => clk_clk_i,`
288			`d_regs_in_i => d_regs_in_o_i,`
289			`load_regs_i => load_regs_o_i,`
290	11	fpga_is_fu	`rst_rst_n_i => rst_rst_n_i,`
291	2	fpga_is_fu	`sel_rb_in_i => sel_rb_in_o_i,`
292	11	fpga_is_fu	`sel_rb_out_i => sel_rb_out_o_i,`
293	2	fpga_is_fu	`sel_reg_i => sel_reg_o_i,`
294			`d_regs_out_o => d_regs_out_o_i,`
295			`q_a_o => q_a_o_i,`
296			`q_x_o => q_x_o_i,`
297			`q_y_o => q_y_o_i`
298			`);`
299			`U_0 : Reg_PC`
300	14	fpga_is_fu	`PORT MAP (`
301	2	fpga_is_fu	`adr_i => adr_o_i,`
302			`clk_clk_i => clk_clk_i,`
303			`ld_i => ld_o_i,`
304			`ld_pc_i => ld_pc_o_i,`
305			`offset_i => offset_o_i,`
306	11	fpga_is_fu	`rst_rst_n_i => rst_rst_n_i,`
307			`sel_pc_in_i => sel_pc_in_o_i,`
308	2	fpga_is_fu	`sel_pc_val_i => sel_pc_val_o_i,`
309			`adr_nxt_pc_o => adr_nxt_pc_o_i,`
310	11	fpga_is_fu	`adr_pc_o => adr_pc_o_i`
311	2	fpga_is_fu	`);`
312			`U_1 : Reg_SP`
313	14	fpga_is_fu	`PORT MAP (`
314	11	fpga_is_fu	`adr_low_i => adr_o_i(7 DOWNTO 0),`
315	5	fpga_is_fu	`clk_clk_i => clk_clk_i,`
316	11	fpga_is_fu	`ld_low_i => ld_o_i(0),`
317			`ld_sp_i => ld_sp_o_i,`
318	5	fpga_is_fu	`rst_rst_n_i => rst_rst_n_i,`
319	11	fpga_is_fu	`sel_sp_as_i => sel_sp_as_o_i,`
320			`sel_sp_in_i => sel_sp_in_o_i,`
321			`adr_sp_o => adr_sp_o_i`
322	5	fpga_is_fu	`);`
323	2	fpga_is_fu
324	14	fpga_is_fu	`END struct;`

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