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-- VHDL Entity R6502_TC.Core.symbol
--
-- Created:
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
--          at - 19:07:10 08.04.2008
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
entity Core is
   port(
      clk_clk_i   : in     std_logic;
      d_i         : in     std_logic_vector (7 downto 0);
      irq_n_i     : in     std_logic;
      nmi_i       : in     std_logic;
      rdy_i       : in     std_logic;
      rst_rst_n_i : in     std_logic;
      so_n_i      : in     std_logic;
      a_o         : out    std_logic_vector (15 downto 0);
      d_o         : out    std_logic_vector (7 downto 0);
      rd_o        : out    std_logic;
      sync_o      : out    std_logic;
      wr_n_o      : out    std_logic;
      wr_o        : out    std_logic
   );
 
-- Declarations
 
end Core ;
 
-- Jens-D. Gutschmidt     Project:  R6502_TC  
-- scantara2003@yahoo.de                      
-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG                                                                                                                                  
--                                                                                                                                                                                          
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version   
-- 3 of the License, or any later version.                                                                                                                                                  
--                                                                                                                                                                                          
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A                          
-- PARTICULAR PURPOSE.  See the GNU General Public License for more details.                                                                                                                
--                                                                                                                                                                                          
-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.                                                  
--                                                                                                                                                                                          
-- CVS Revisins History                                                                                                                                                                     
--                                                                                                                                                                                          
-- $Log: not supported by cvs2svn $                                                                                                                                                                                    
--                                                                                                                                                                                          
-- Title:  Core of 6502  
-- Path:  R6502_TC/Core/struct  
-- Edited:  by eda on 08 Apr 2008  
--
-- VHDL Architecture R6502_TC.Core.struct
--
-- Created:
--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
--          at - 19:07:10 08.04.2008
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
library R6502_TC;
 
architecture struct of Core is
 
   -- Architecture declarations
 
   -- Internal signal declarations
   signal adr_nxt_pc_o_i     : std_logic_vector(15 downto 0);
   signal adr_nxt_sp_o_i     : std_logic_vector(15 downto 0);
   signal adr_o_i            : std_logic_vector(15 downto 0);
   signal adr_pc_o_i         : std_logic_vector(15 downto 0);
   signal adr_sp_o_i         : std_logic_vector(15 downto 0);
   signal ch_a_o_i           : std_logic_vector(7 downto 0);
   signal ch_b_o_i           : std_logic_vector(7 downto 0);
   signal cout_pc_o_i        : std_logic;
   signal d_alu_o_i          : std_logic_vector(7 downto 0);
   signal d_regs_in_o_i      : std_logic_vector(7 downto 0);
   signal d_regs_out_o_i     : std_logic_vector(7 downto 0);
   signal ld_o_i             : std_logic_vector(1 downto 0);
   signal ld_pc_o_i          : std_logic;
   signal ld_sp_o_i          : std_logic;
   signal load_regs_o_i      : std_logic;
   signal offset_o_i         : std_logic_vector(15 downto 0);
   signal q_a_o_i            : std_logic_vector(7 downto 0);
   signal q_x_o_i            : std_logic_vector(7 downto 0);
   signal q_y_o_i            : std_logic_vector(7 downto 0);
   signal reg_0flag_core_o_i : std_logic;
   signal reg_0flag_o_i      : std_logic;
   signal reg_1flag_o_i      : std_logic;
   signal reg_3flag_core_o_i : std_logic;
   signal reg_6flag_o_i      : std_logic;
   signal reg_7flag_core_o_i : std_logic;
   signal reg_7flag_o_i      : std_logic;
   signal rst_rst_int_o_i    : std_logic;
   signal sel_alu_as_o_i     : std_logic;
   signal sel_alu_out_o_i    : std_logic_vector(2 downto 0);
   signal sel_pc_as_o_i      : std_logic;
   signal sel_pc_in_o_i      : std_logic_vector(1 downto 0);
   signal sel_pc_val_o_i     : std_logic_vector(1 downto 0);
   signal sel_rb_in_o_i      : std_logic_vector(2 downto 0);
   signal sel_rb_out_o_i     : std_logic_vector(2 downto 0);
   signal sel_reg_o_i        : std_logic_vector(1 downto 0);
   signal sel_sp_as_o_i      : std_logic;
   signal sel_sp_in_o_i      : std_logic_vector(1 downto 0);
   signal sel_sp_val_o_i     : std_logic_vector(1 downto 0);
 
 
   -- Component Declarations
   component ALU
   port (
      ch_a_i           : in     std_logic_vector (7 downto 0);
      ch_b_i           : in     std_logic_vector (7 downto 0);
      reg_0flag_core_i : in     std_logic ;
      reg_3flag_core_i : in     std_logic ;
      reg_7flag_core_i : in     std_logic ;
      sel_alu_as_i     : in     std_logic ;
      sel_alu_out_i    : in     std_logic_vector (2 downto 0);
      d_alu_o          : out    std_logic_vector (7 downto 0);
      reg_0flag_o      : out    std_logic ;
      reg_1flag_o      : out    std_logic ;
      reg_6flag_o      : out    std_logic ;
      reg_7flag_o      : out    std_logic
   );
   end component;
   component RegBank_AXY
   port (
      clk_clk_i    : in     std_logic ;
      d_regs_in_i  : in     std_logic_vector (7 downto 0);
      load_regs_i  : in     std_logic ;
      rst_rst_i    : in     std_logic ;
      sel_rb_in_i  : in     std_logic_vector (2 downto 0);
      sel_rb_out_i : in     std_logic_vector (1 downto 0);
      sel_reg_i    : in     std_logic_vector (1 downto 0);
      d_regs_out_o : out    std_logic_vector (7 downto 0);
      q_a_o        : out    std_logic_vector (7 downto 0);
      q_x_o        : out    std_logic_vector (7 downto 0);
      q_y_o        : out    std_logic_vector (7 downto 0)
   );
   end component;
   component Reg_PC
   port (
      adr_i        : in     std_logic_vector (15 downto 0);
      clk_clk_i    : in     std_logic ;
      ld_i         : in     std_logic_vector (1 downto 0);
      ld_pc_i      : in     std_logic ;
      offset_i     : in     std_logic_vector (15 downto 0);
      rst_rst_i    : in     std_logic ;
      sel_pc_as_i  : in     std_logic ;
      sel_pc_in_i  : in     std_logic ;
      sel_pc_val_i : in     std_logic_vector (1 downto 0);
      adr_nxt_pc_o : out    std_logic_vector (15 downto 0);
      adr_pc_o     : out    std_logic_vector (15 downto 0);
      cout_pc_o    : out    std_logic
   );
   end component;
   component Reg_SP
   port (
      adr_i        : in     std_logic_vector (15 downto 0);
      clk_clk_i    : in     std_logic ;
      ld_i         : in     std_logic_vector (1 downto 0);
      ld_sp_i      : in     std_logic ;
      rst_rst_i    : in     std_logic ;
      sel_sp_as_i  : in     std_logic ;
      sel_sp_in_i  : in     std_logic ;
      sel_sp_val_i : in     std_logic ;
      adr_nxt_sp_o : out    std_logic_vector (15 downto 0);
      adr_sp_o     : out    std_logic_vector (15 downto 0)
   );
   end component;
   component fsm_core_V2_0
   port (
      adr_nxt_pc_i    : in     std_logic_vector (15 downto 0);
      adr_nxt_sp_i    : in     std_logic_vector (15 downto 0);
      adr_pc_i        : in     std_logic_vector (15 downto 0);
      adr_sp_i        : in     std_logic_vector (15 downto 0);
      clk_clk_i       : in     std_logic ;
      cout_pc_i       : in     std_logic ;
      d_alu_i         : in     std_logic_vector ( 7 downto 0 );
      d_i             : in     std_logic_vector ( 7 downto 0 );
      d_regs_out_i    : in     std_logic_vector ( 7 downto 0 );
      irq_n_i         : in     std_logic ;
      nmi_i           : in     std_logic ;
      q_a_i           : in     std_logic_vector ( 7 downto 0 );
      q_x_i           : in     std_logic_vector ( 7 downto 0 );
      q_y_i           : in     std_logic_vector ( 7 downto 0 );
      rdy_i           : in     std_logic ;
      reg_0flag_i     : in     std_logic ;
      reg_1flag_i     : in     std_logic ;
      reg_6flag_i     : in     std_logic ;
      reg_7flag_i     : in     std_logic ;
      rst_rst_n_i     : in     std_logic ;
      so_n_i          : in     std_logic ;
      a_o             : out    std_logic_vector (15 downto 0);
      adr_o           : out    std_logic_vector (15 downto 0);
      ch_a_o          : out    std_logic_vector ( 7 downto 0 );
      ch_b_o          : out    std_logic_vector ( 7 downto 0 );
      d_o             : out    std_logic_vector ( 7 downto 0 );
      d_regs_in_o     : out    std_logic_vector ( 7 downto 0 );
      ld_o            : out    std_logic_vector ( 1 downto 0 );
      ld_pc_o         : out    std_logic ;
      ld_sp_o         : out    std_logic ;
      load_regs_o     : out    std_logic ;
      offset_o        : out    std_logic_vector ( 15 downto 0 );
      rd_o            : out    std_logic ;
      reg_0flag_o     : out    std_logic ;
      reg_1flag_o     : out    std_logic ;
      reg_3flag_o     : out    std_logic ;
      reg_7flag_o     : out    std_logic ;
      sync_o          : out    std_logic ;
      wr_n_o          : out    std_logic ;
      wr_o            : out    std_logic ;
      sel_alu_as_o_i  : inout  std_logic ;
      sel_alu_out_o_i : inout  std_logic_vector ( 2 downto 0 );
      sel_pc_as_o_i   : inout  std_logic ;
      sel_pc_in_o_i   : inout  std_logic_vector ( 1 downto 0 );
      sel_pc_val_o_i  : inout  std_logic_vector ( 1 downto 0 );
      sel_rb_in_o_i   : inout  std_logic_vector ( 2 downto 0 );
      sel_rb_out_o_i  : inout  std_logic_vector ( 2 downto 0 );
      sel_reg_o_i     : inout  std_logic_vector ( 1 downto 0 );
      sel_sp_as_o_i   : inout  std_logic ;
      sel_sp_in_o_i   : inout  std_logic_vector ( 1 downto 0 );
      sel_sp_val_o_i  : inout  std_logic_vector ( 1 downto 0 )
   );
   end component;
 
   -- Optional embedded configurations
   -- pragma synthesis_off
   for all : ALU use entity R6502_TC.ALU;
   for all : RegBank_AXY use entity R6502_TC.RegBank_AXY;
   for all : Reg_PC use entity R6502_TC.Reg_PC;
   for all : Reg_SP use entity R6502_TC.Reg_SP;
   for all : fsm_core_V2_0 use entity R6502_TC.fsm_core_V2_0;
   -- pragma synthesis_on
 
 
begin
 
   -- ModuleWare code(v1.9) for instance 'U_5' of 'inv'
   rst_rst_int_o_i <= not(rst_rst_n_i);
 
   -- Instance port mappings.
   U_3 : ALU
      port map (
         ch_a_i           => ch_a_o_i,
         ch_b_i           => ch_b_o_i,
         reg_0flag_core_i => reg_0flag_core_o_i,
         reg_3flag_core_i => reg_3flag_core_o_i,
         reg_7flag_core_i => reg_7flag_core_o_i,
         sel_alu_as_i     => sel_alu_as_o_i,
         sel_alu_out_i    => sel_alu_out_o_i,
         d_alu_o          => d_alu_o_i,
         reg_0flag_o      => reg_0flag_o_i,
         reg_1flag_o      => reg_1flag_o_i,
         reg_6flag_o      => reg_6flag_o_i,
         reg_7flag_o      => reg_7flag_o_i
      );
   U_2 : RegBank_AXY
      port map (
         clk_clk_i    => clk_clk_i,
         d_regs_in_i  => d_regs_in_o_i,
         load_regs_i  => load_regs_o_i,
         rst_rst_i    => rst_rst_int_o_i,
         sel_rb_in_i  => sel_rb_in_o_i,
         sel_rb_out_i => sel_rb_out_o_i(1 DOWNTO 0),
         sel_reg_i    => sel_reg_o_i,
         d_regs_out_o => d_regs_out_o_i,
         q_a_o        => q_a_o_i,
         q_x_o        => q_x_o_i,
         q_y_o        => q_y_o_i
      );
   U_0 : Reg_PC
      port map (
         adr_i        => adr_o_i,
         clk_clk_i    => clk_clk_i,
         ld_i         => ld_o_i,
         ld_pc_i      => ld_pc_o_i,
         offset_i     => offset_o_i,
         rst_rst_i    => rst_rst_int_o_i,
         sel_pc_as_i  => sel_pc_as_o_i,
         sel_pc_in_i  => sel_pc_in_o_i(0),
         sel_pc_val_i => sel_pc_val_o_i,
         adr_nxt_pc_o => adr_nxt_pc_o_i,
         adr_pc_o     => adr_pc_o_i,
         cout_pc_o    => cout_pc_o_i
      );
   U_1 : Reg_SP
      port map (
         adr_i        => adr_o_i,
         clk_clk_i    => clk_clk_i,
         ld_i         => ld_o_i,
         ld_sp_i      => ld_sp_o_i,
         rst_rst_i    => rst_rst_int_o_i,
         sel_sp_as_i  => sel_sp_as_o_i,
         sel_sp_in_i  => sel_sp_in_o_i(0),
         sel_sp_val_i => sel_sp_val_o_i(0),
         adr_nxt_sp_o => adr_nxt_sp_o_i,
         adr_sp_o     => adr_sp_o_i
      );
   U_4 : fsm_core_V2_0
      port map (
         adr_nxt_pc_i    => adr_nxt_pc_o_i,
         adr_nxt_sp_i    => adr_nxt_sp_o_i,
         adr_pc_i        => adr_pc_o_i,
         adr_sp_i        => adr_sp_o_i,
         clk_clk_i       => clk_clk_i,
         cout_pc_i       => cout_pc_o_i,
         d_alu_i         => d_alu_o_i,
         d_i             => d_i,
         d_regs_out_i    => d_regs_out_o_i,
         irq_n_i         => irq_n_i,
         nmi_i           => nmi_i,
         q_a_i           => q_a_o_i,
         q_x_i           => q_x_o_i,
         q_y_i           => q_y_o_i,
         rdy_i           => rdy_i,
         reg_0flag_i     => reg_0flag_o_i,
         reg_1flag_i     => reg_1flag_o_i,
         reg_6flag_i     => reg_6flag_o_i,
         reg_7flag_i     => reg_7flag_o_i,
         rst_rst_n_i     => rst_rst_n_i,
         so_n_i          => so_n_i,
         a_o             => a_o,
         adr_o           => adr_o_i,
         ch_a_o          => ch_a_o_i,
         ch_b_o          => ch_b_o_i,
         d_o             => d_o,
         d_regs_in_o     => d_regs_in_o_i,
         ld_o            => ld_o_i,
         ld_pc_o         => ld_pc_o_i,
         ld_sp_o         => ld_sp_o_i,
         load_regs_o     => load_regs_o_i,
         offset_o        => offset_o_i,
         rd_o            => rd_o,
         reg_0flag_o     => reg_0flag_core_o_i,
         reg_1flag_o     => open,
         reg_3flag_o     => reg_3flag_core_o_i,
         reg_7flag_o     => reg_7flag_core_o_i,
         sync_o          => sync_o,
         wr_n_o          => wr_n_o,
         wr_o            => wr_o,
         sel_alu_as_o_i  => sel_alu_as_o_i,
         sel_alu_out_o_i => sel_alu_out_o_i,
         sel_pc_as_o_i   => sel_pc_as_o_i,
         sel_pc_in_o_i   => sel_pc_in_o_i,
         sel_pc_val_o_i  => sel_pc_val_o_i,
         sel_rb_in_o_i   => sel_rb_in_o_i,
         sel_rb_out_o_i  => sel_rb_out_o_i,
         sel_reg_o_i     => sel_reg_o_i,
         sel_sp_as_o_i   => sel_sp_as_o_i,
         sel_sp_in_o_i   => sel_sp_in_o_i,
         sel_sp_val_o_i  => sel_sp_val_o_i
      );
 
end struct;

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Subversion Repositories cpu6502_true_cycle

[/] [cpu6502_true_cycle/] [trunk/] [rtl/] [vhdl/] [core.vhd] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	fpga_is_fu	`-- VHDL Entity R6502_TC.Core.symbol`
2			`--`
3			`-- Created:`
4			`-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)`
5			`-- at - 19:07:10 08.04.2008`
6			`--`
7			`-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)`
8			`--`
9			`LIBRARY ieee;`
10			`USE ieee.std_logic_1164.all;`
11			`USE ieee.std_logic_arith.all;`
12
13			`entity Core is`
14			`port(`
15			`clk_clk_i : in std_logic;`
16			`d_i : in std_logic_vector (7 downto 0);`
17			`irq_n_i : in std_logic;`
18			`nmi_i : in std_logic;`
19			`rdy_i : in std_logic;`
20			`rst_rst_n_i : in std_logic;`
21			`so_n_i : in std_logic;`
22			`a_o : out std_logic_vector (15 downto 0);`
23			`d_o : out std_logic_vector (7 downto 0);`
24			`rd_o : out std_logic;`
25			`sync_o : out std_logic;`
26			`wr_n_o : out std_logic;`
27			`wr_o : out std_logic`
28			`);`
29
30			`-- Declarations`
31
32			`end Core ;`
33
34			`-- Jens-D. Gutschmidt Project: R6502_TC`
35			`-- scantara2003@yahoo.de`
36			`-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG`
37			`--`
38			`-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version`
39			`-- 3 of the License, or any later version.`
40			`--`
41			`-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A`
42			`-- PARTICULAR PURPOSE. See the GNU General Public License for more details.`
43			`--`
44			`-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.`
45			`--`
46			`-- CVS Revisins History`
47			`--`
48			`-- $Log: not supported by cvs2svn $`
49			`--`
50			`-- Title: Core of 6502`
51			`-- Path: R6502_TC/Core/struct`
52			`-- Edited: by eda on 08 Apr 2008`
53			`--`
54			`-- VHDL Architecture R6502_TC.Core.struct`
55			`--`
56			`-- Created:`
57			`-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)`
58			`-- at - 19:07:10 08.04.2008`
59			`--`
60			`-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)`
61			`--`
62			`LIBRARY ieee;`
63			`USE ieee.std_logic_1164.all;`
64			`USE ieee.std_logic_arith.all;`
65
66			`library R6502_TC;`
67
68			`architecture struct of Core is`
69
70			`-- Architecture declarations`
71
72			`-- Internal signal declarations`
73			`signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0);`
74			`signal adr_nxt_sp_o_i : std_logic_vector(15 downto 0);`
75			`signal adr_o_i : std_logic_vector(15 downto 0);`
76			`signal adr_pc_o_i : std_logic_vector(15 downto 0);`
77			`signal adr_sp_o_i : std_logic_vector(15 downto 0);`
78			`signal ch_a_o_i : std_logic_vector(7 downto 0);`
79			`signal ch_b_o_i : std_logic_vector(7 downto 0);`
80			`signal cout_pc_o_i : std_logic;`
81			`signal d_alu_o_i : std_logic_vector(7 downto 0);`
82			`signal d_regs_in_o_i : std_logic_vector(7 downto 0);`
83			`signal d_regs_out_o_i : std_logic_vector(7 downto 0);`
84			`signal ld_o_i : std_logic_vector(1 downto 0);`
85			`signal ld_pc_o_i : std_logic;`
86			`signal ld_sp_o_i : std_logic;`
87			`signal load_regs_o_i : std_logic;`
88			`signal offset_o_i : std_logic_vector(15 downto 0);`
89			`signal q_a_o_i : std_logic_vector(7 downto 0);`
90			`signal q_x_o_i : std_logic_vector(7 downto 0);`
91			`signal q_y_o_i : std_logic_vector(7 downto 0);`
92			`signal reg_0flag_core_o_i : std_logic;`
93			`signal reg_0flag_o_i : std_logic;`
94			`signal reg_1flag_o_i : std_logic;`
95			`signal reg_3flag_core_o_i : std_logic;`
96			`signal reg_6flag_o_i : std_logic;`
97			`signal reg_7flag_core_o_i : std_logic;`
98			`signal reg_7flag_o_i : std_logic;`
99			`signal rst_rst_int_o_i : std_logic;`
100			`signal sel_alu_as_o_i : std_logic;`
101			`signal sel_alu_out_o_i : std_logic_vector(2 downto 0);`
102			`signal sel_pc_as_o_i : std_logic;`
103			`signal sel_pc_in_o_i : std_logic_vector(1 downto 0);`
104			`signal sel_pc_val_o_i : std_logic_vector(1 downto 0);`
105			`signal sel_rb_in_o_i : std_logic_vector(2 downto 0);`
106			`signal sel_rb_out_o_i : std_logic_vector(2 downto 0);`
107			`signal sel_reg_o_i : std_logic_vector(1 downto 0);`
108			`signal sel_sp_as_o_i : std_logic;`
109			`signal sel_sp_in_o_i : std_logic_vector(1 downto 0);`
110			`signal sel_sp_val_o_i : std_logic_vector(1 downto 0);`
111
112
113			`-- Component Declarations`
114			`component ALU`
115			`port (`
116			`ch_a_i : in std_logic_vector (7 downto 0);`
117			`ch_b_i : in std_logic_vector (7 downto 0);`
118			`reg_0flag_core_i : in std_logic ;`
119			`reg_3flag_core_i : in std_logic ;`
120			`reg_7flag_core_i : in std_logic ;`
121			`sel_alu_as_i : in std_logic ;`
122			`sel_alu_out_i : in std_logic_vector (2 downto 0);`
123			`d_alu_o : out std_logic_vector (7 downto 0);`
124			`reg_0flag_o : out std_logic ;`
125			`reg_1flag_o : out std_logic ;`
126			`reg_6flag_o : out std_logic ;`
127			`reg_7flag_o : out std_logic`
128			`);`
129			`end component;`
130			`component RegBank_AXY`
131			`port (`
132			`clk_clk_i : in std_logic ;`
133			`d_regs_in_i : in std_logic_vector (7 downto 0);`
134			`load_regs_i : in std_logic ;`
135			`rst_rst_i : in std_logic ;`
136			`sel_rb_in_i : in std_logic_vector (2 downto 0);`
137			`sel_rb_out_i : in std_logic_vector (1 downto 0);`
138			`sel_reg_i : in std_logic_vector (1 downto 0);`
139			`d_regs_out_o : out std_logic_vector (7 downto 0);`
140			`q_a_o : out std_logic_vector (7 downto 0);`
141			`q_x_o : out std_logic_vector (7 downto 0);`
142			`q_y_o : out std_logic_vector (7 downto 0)`
143			`);`
144			`end component;`
145			`component Reg_PC`
146			`port (`
147			`adr_i : in std_logic_vector (15 downto 0);`
148			`clk_clk_i : in std_logic ;`
149			`ld_i : in std_logic_vector (1 downto 0);`
150			`ld_pc_i : in std_logic ;`
151			`offset_i : in std_logic_vector (15 downto 0);`
152			`rst_rst_i : in std_logic ;`
153			`sel_pc_as_i : in std_logic ;`
154			`sel_pc_in_i : in std_logic ;`
155			`sel_pc_val_i : in std_logic_vector (1 downto 0);`
156			`adr_nxt_pc_o : out std_logic_vector (15 downto 0);`
157			`adr_pc_o : out std_logic_vector (15 downto 0);`
158			`cout_pc_o : out std_logic`
159			`);`
160			`end component;`
161			`component Reg_SP`
162			`port (`
163			`adr_i : in std_logic_vector (15 downto 0);`
164			`clk_clk_i : in std_logic ;`
165			`ld_i : in std_logic_vector (1 downto 0);`
166			`ld_sp_i : in std_logic ;`
167			`rst_rst_i : in std_logic ;`
168			`sel_sp_as_i : in std_logic ;`
169			`sel_sp_in_i : in std_logic ;`
170			`sel_sp_val_i : in std_logic ;`
171			`adr_nxt_sp_o : out std_logic_vector (15 downto 0);`
172			`adr_sp_o : out std_logic_vector (15 downto 0)`
173			`);`
174			`end component;`
175			`component fsm_core_V2_0`
176			`port (`
177			`adr_nxt_pc_i : in std_logic_vector (15 downto 0);`
178			`adr_nxt_sp_i : in std_logic_vector (15 downto 0);`
179			`adr_pc_i : in std_logic_vector (15 downto 0);`
180			`adr_sp_i : in std_logic_vector (15 downto 0);`
181			`clk_clk_i : in std_logic ;`
182			`cout_pc_i : in std_logic ;`
183			`d_alu_i : in std_logic_vector ( 7 downto 0 );`
184			`d_i : in std_logic_vector ( 7 downto 0 );`
185			`d_regs_out_i : in std_logic_vector ( 7 downto 0 );`
186			`irq_n_i : in std_logic ;`
187			`nmi_i : in std_logic ;`
188			`q_a_i : in std_logic_vector ( 7 downto 0 );`
189			`q_x_i : in std_logic_vector ( 7 downto 0 );`
190			`q_y_i : in std_logic_vector ( 7 downto 0 );`
191			`rdy_i : in std_logic ;`
192			`reg_0flag_i : in std_logic ;`
193			`reg_1flag_i : in std_logic ;`
194			`reg_6flag_i : in std_logic ;`
195			`reg_7flag_i : in std_logic ;`
196			`rst_rst_n_i : in std_logic ;`
197			`so_n_i : in std_logic ;`
198			`a_o : out std_logic_vector (15 downto 0);`
199			`adr_o : out std_logic_vector (15 downto 0);`
200			`ch_a_o : out std_logic_vector ( 7 downto 0 );`
201			`ch_b_o : out std_logic_vector ( 7 downto 0 );`
202			`d_o : out std_logic_vector ( 7 downto 0 );`
203			`d_regs_in_o : out std_logic_vector ( 7 downto 0 );`
204			`ld_o : out std_logic_vector ( 1 downto 0 );`
205			`ld_pc_o : out std_logic ;`
206			`ld_sp_o : out std_logic ;`
207			`load_regs_o : out std_logic ;`
208			`offset_o : out std_logic_vector ( 15 downto 0 );`
209			`rd_o : out std_logic ;`
210			`reg_0flag_o : out std_logic ;`
211			`reg_1flag_o : out std_logic ;`
212			`reg_3flag_o : out std_logic ;`
213			`reg_7flag_o : out std_logic ;`
214			`sync_o : out std_logic ;`
215			`wr_n_o : out std_logic ;`
216			`wr_o : out std_logic ;`
217			`sel_alu_as_o_i : inout std_logic ;`
218			`sel_alu_out_o_i : inout std_logic_vector ( 2 downto 0 );`
219			`sel_pc_as_o_i : inout std_logic ;`
220			`sel_pc_in_o_i : inout std_logic_vector ( 1 downto 0 );`
221			`sel_pc_val_o_i : inout std_logic_vector ( 1 downto 0 );`
222			`sel_rb_in_o_i : inout std_logic_vector ( 2 downto 0 );`
223			`sel_rb_out_o_i : inout std_logic_vector ( 2 downto 0 );`
224			`sel_reg_o_i : inout std_logic_vector ( 1 downto 0 );`
225			`sel_sp_as_o_i : inout std_logic ;`
226			`sel_sp_in_o_i : inout std_logic_vector ( 1 downto 0 );`
227			`sel_sp_val_o_i : inout std_logic_vector ( 1 downto 0 )`
228			`);`
229			`end component;`
230
231			`-- Optional embedded configurations`
232			`-- pragma synthesis_off`
233			`for all : ALU use entity R6502_TC.ALU;`
234			`for all : RegBank_AXY use entity R6502_TC.RegBank_AXY;`
235			`for all : Reg_PC use entity R6502_TC.Reg_PC;`
236			`for all : Reg_SP use entity R6502_TC.Reg_SP;`
237			`for all : fsm_core_V2_0 use entity R6502_TC.fsm_core_V2_0;`
238			`-- pragma synthesis_on`
239
240
241			`begin`
242
243			`-- ModuleWare code(v1.9) for instance 'U_5' of 'inv'`
244			`rst_rst_int_o_i <= not(rst_rst_n_i);`
245
246			`-- Instance port mappings.`
247			`U_3 : ALU`
248			`port map (`
249			`ch_a_i => ch_a_o_i,`
250			`ch_b_i => ch_b_o_i,`
251			`reg_0flag_core_i => reg_0flag_core_o_i,`
252			`reg_3flag_core_i => reg_3flag_core_o_i,`
253			`reg_7flag_core_i => reg_7flag_core_o_i,`
254			`sel_alu_as_i => sel_alu_as_o_i,`
255			`sel_alu_out_i => sel_alu_out_o_i,`
256			`d_alu_o => d_alu_o_i,`
257			`reg_0flag_o => reg_0flag_o_i,`
258			`reg_1flag_o => reg_1flag_o_i,`
259			`reg_6flag_o => reg_6flag_o_i,`
260			`reg_7flag_o => reg_7flag_o_i`
261			`);`
262			`U_2 : RegBank_AXY`
263			`port map (`
264			`clk_clk_i => clk_clk_i,`
265			`d_regs_in_i => d_regs_in_o_i,`
266			`load_regs_i => load_regs_o_i,`
267			`rst_rst_i => rst_rst_int_o_i,`
268			`sel_rb_in_i => sel_rb_in_o_i,`
269			`sel_rb_out_i => sel_rb_out_o_i(1 DOWNTO 0),`
270			`sel_reg_i => sel_reg_o_i,`
271			`d_regs_out_o => d_regs_out_o_i,`
272			`q_a_o => q_a_o_i,`
273			`q_x_o => q_x_o_i,`
274			`q_y_o => q_y_o_i`
275			`);`
276			`U_0 : Reg_PC`
277			`port map (`
278			`adr_i => adr_o_i,`
279			`clk_clk_i => clk_clk_i,`
280			`ld_i => ld_o_i,`
281			`ld_pc_i => ld_pc_o_i,`
282			`offset_i => offset_o_i,`
283			`rst_rst_i => rst_rst_int_o_i,`
284			`sel_pc_as_i => sel_pc_as_o_i,`
285			`sel_pc_in_i => sel_pc_in_o_i(0),`
286			`sel_pc_val_i => sel_pc_val_o_i,`
287			`adr_nxt_pc_o => adr_nxt_pc_o_i,`
288			`adr_pc_o => adr_pc_o_i,`
289			`cout_pc_o => cout_pc_o_i`
290			`);`
291			`U_1 : Reg_SP`
292			`port map (`
293			`adr_i => adr_o_i,`
294			`clk_clk_i => clk_clk_i,`
295			`ld_i => ld_o_i,`
296			`ld_sp_i => ld_sp_o_i,`
297			`rst_rst_i => rst_rst_int_o_i,`
298			`sel_sp_as_i => sel_sp_as_o_i,`
299			`sel_sp_in_i => sel_sp_in_o_i(0),`
300			`sel_sp_val_i => sel_sp_val_o_i(0),`
301			`adr_nxt_sp_o => adr_nxt_sp_o_i,`
302			`adr_sp_o => adr_sp_o_i`
303			`);`
304			`U_4 : fsm_core_V2_0`
305			`port map (`
306			`adr_nxt_pc_i => adr_nxt_pc_o_i,`
307			`adr_nxt_sp_i => adr_nxt_sp_o_i,`
308			`adr_pc_i => adr_pc_o_i,`
309			`adr_sp_i => adr_sp_o_i,`
310			`clk_clk_i => clk_clk_i,`
311			`cout_pc_i => cout_pc_o_i,`
312			`d_alu_i => d_alu_o_i,`
313			`d_i => d_i,`
314			`d_regs_out_i => d_regs_out_o_i,`
315			`irq_n_i => irq_n_i,`
316			`nmi_i => nmi_i,`
317			`q_a_i => q_a_o_i,`
318			`q_x_i => q_x_o_i,`
319			`q_y_i => q_y_o_i,`
320			`rdy_i => rdy_i,`
321			`reg_0flag_i => reg_0flag_o_i,`
322			`reg_1flag_i => reg_1flag_o_i,`
323			`reg_6flag_i => reg_6flag_o_i,`
324			`reg_7flag_i => reg_7flag_o_i,`
325			`rst_rst_n_i => rst_rst_n_i,`
326			`so_n_i => so_n_i,`
327			`a_o => a_o,`
328			`adr_o => adr_o_i,`
329			`ch_a_o => ch_a_o_i,`
330			`ch_b_o => ch_b_o_i,`
331			`d_o => d_o,`
332			`d_regs_in_o => d_regs_in_o_i,`
333			`ld_o => ld_o_i,`
334			`ld_pc_o => ld_pc_o_i,`
335			`ld_sp_o => ld_sp_o_i,`
336			`load_regs_o => load_regs_o_i,`
337			`offset_o => offset_o_i,`
338			`rd_o => rd_o,`
339			`reg_0flag_o => reg_0flag_core_o_i,`
340			`reg_1flag_o => open,`
341			`reg_3flag_o => reg_3flag_core_o_i,`
342			`reg_7flag_o => reg_7flag_core_o_i,`
343			`sync_o => sync_o,`
344			`wr_n_o => wr_n_o,`
345			`wr_o => wr_o,`
346			`sel_alu_as_o_i => sel_alu_as_o_i,`
347			`sel_alu_out_o_i => sel_alu_out_o_i,`
348			`sel_pc_as_o_i => sel_pc_as_o_i,`
349			`sel_pc_in_o_i => sel_pc_in_o_i,`
350			`sel_pc_val_o_i => sel_pc_val_o_i,`
351			`sel_rb_in_o_i => sel_rb_in_o_i,`
352			`sel_rb_out_o_i => sel_rb_out_o_i,`
353			`sel_reg_o_i => sel_reg_o_i,`
354			`sel_sp_as_o_i => sel_sp_as_o_i,`
355			`sel_sp_in_o_i => sel_sp_in_o_i,`
356			`sel_sp_val_o_i => sel_sp_val_o_i`
357			`);`
358
359			`end struct;`