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-- VHDL Entity R6502_TC.Core.symbol
--
-- Created:
--          by - eda.UNKNOWN (ENTW1)
--          at - 14:13:52 08.03.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
ENTITY Core IS
   PORT(
      clk_clk_i   : IN     std_logic;
      d_i         : IN     std_logic_vector (7 DOWNTO 0);
      irq_n_i     : IN     std_logic;
      nmi_n_i     : IN     std_logic;
      rdy_i       : IN     std_logic;
      rst_rst_n_i : IN     std_logic;
      so_n_i      : IN     std_logic;
      a_o         : OUT    std_logic_vector (15 DOWNTO 0);
      d_o         : OUT    std_logic_vector (7 DOWNTO 0);
      rd_o        : OUT    std_logic;
      sync_o      : OUT    std_logic;
      wr_n_o      : OUT    std_logic;
      wr_o        : OUT    std_logic
   );
 
-- Declarations
 
END Core ;
 
-- Jens-D. Gutschmidt     Project:  R6502_TC  
-- scantara2003@yahoo.de                      
-- COPYRIGHT (C) 2008-2010  by Jens Gutschmidt and OPENCORES.ORG                                                                                                                            
--                                                                                                                                                                                          
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version   
-- 3 of the License, or any later version.                                                                                                                                                  
--                                                                                                                                                                                          
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A                          
-- PARTICULAR PURPOSE.  See the GNU General Public License for more details.                                                                                                                
--                                                                                                                                                                                          
-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.                                                  
--                                                                                                                                                                                          
-- CVS Revisins History                                                                                                                                                                     
--                                                                                                                                                                                          
-- $Log: struct.bd,v $                                                                                                                                                                      
--   <<-- more -->>                                                                                                                                                                         
-- Title:  Core  
-- Path:  R6502_TC/Core/struct  
-- Edited:  by eda on 08 Feb 2010  
--
-- VHDL Architecture R6502_TC.Core.struct
--
-- Created:
--          by - eda.UNKNOWN (ENTW1)
--          at - 14:13:53 08.03.2010
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
 
LIBRARY R6502_TC;
 
ARCHITECTURE struct OF Core IS
 
   -- Architecture declarations
 
   -- Internal signal declarations
   SIGNAL adr_nxt_pc_o_i : std_logic_vector(15 DOWNTO 0);
   SIGNAL adr_o_i        : std_logic_vector(15 DOWNTO 0);
   SIGNAL adr_pc_o_i     : std_logic_vector(15 DOWNTO 0);
   SIGNAL adr_sp_o_i     : std_logic_vector(15 DOWNTO 0);
   SIGNAL ch_a_o_i       : std_logic_vector(7 DOWNTO 0);
   SIGNAL ch_b_o_i       : std_logic_vector(7 DOWNTO 0);
   SIGNAL d_alu_n_o_i    : std_logic;
   SIGNAL d_alu_o_i      : std_logic_vector(7 DOWNTO 0);
   SIGNAL d_alu_or_o_i   : std_logic;
   SIGNAL d_regs_in_o_i  : std_logic_vector(7 DOWNTO 0);
   SIGNAL d_regs_out_o_i : std_logic_vector(7 DOWNTO 0);
   SIGNAL ld_o_i         : std_logic_vector(1 DOWNTO 0);
   SIGNAL ld_pc_o_i      : std_logic;
   SIGNAL ld_sp_o_i      : std_logic;
   SIGNAL load_regs_o_i  : std_logic;
   SIGNAL nmi_o_i        : std_logic;
   SIGNAL offset_o_i     : std_logic_vector(15 DOWNTO 0);
   SIGNAL q_a_o_i        : std_logic_vector(7 DOWNTO 0);
   SIGNAL q_x_o_i        : std_logic_vector(7 DOWNTO 0);
   SIGNAL q_y_o_i        : std_logic_vector(7 DOWNTO 0);
   SIGNAL reg_0flag_o_i  : std_logic;
   SIGNAL reg_1flag_o_i  : std_logic;
   SIGNAL reg_7flag_o_i  : std_logic;
   SIGNAL rst_nmi_o_i    : std_logic;
   SIGNAL sel_pc_in_o_i  : std_logic;
   SIGNAL sel_pc_val_o_i : std_logic_vector(1 DOWNTO 0);
   SIGNAL sel_rb_in_o_i  : std_logic_vector(1 DOWNTO 0);
   SIGNAL sel_rb_out_o_i : std_logic_vector(1 DOWNTO 0);
   SIGNAL sel_reg_o_i    : std_logic_vector(1 DOWNTO 0);
   SIGNAL sel_sp_as_o_i  : std_logic;
   SIGNAL sel_sp_in_o_i  : std_logic;
 
 
   -- Component Declarations
   COMPONENT FSM_Execution_Unit
   PORT (
      adr_nxt_pc_i : IN     std_logic_vector (15 DOWNTO 0);
      adr_pc_i     : IN     std_logic_vector (15 DOWNTO 0);
      adr_sp_i     : IN     std_logic_vector (15 DOWNTO 0);
      clk_clk_i    : IN     std_logic ;
      d_alu_i      : IN     std_logic_vector ( 7 DOWNTO 0 );
      d_i          : IN     std_logic_vector ( 7 DOWNTO 0 );
      d_regs_out_i : IN     std_logic_vector ( 7 DOWNTO 0 );
      irq_n_i      : IN     std_logic ;
      nmi_i        : IN     std_logic ;
      q_a_i        : IN     std_logic_vector ( 7 DOWNTO 0 );
      q_x_i        : IN     std_logic_vector ( 7 DOWNTO 0 );
      q_y_i        : IN     std_logic_vector ( 7 DOWNTO 0 );
      rdy_i        : IN     std_logic ;
      reg_0flag_i  : IN     std_logic ;
      reg_1flag_i  : IN     std_logic ;
      reg_7flag_i  : IN     std_logic ;
      rst_rst_n_i  : IN     std_logic ;
      so_n_i       : IN     std_logic ;
      a_o          : OUT    std_logic_vector (15 DOWNTO 0);
      adr_o        : OUT    std_logic_vector (15 DOWNTO 0);
      ch_a_o       : OUT    std_logic_vector ( 7 DOWNTO 0 );
      ch_b_o       : OUT    std_logic_vector ( 7 DOWNTO 0 );
      d_o          : OUT    std_logic_vector ( 7 DOWNTO 0 );
      d_regs_in_o  : OUT    std_logic_vector ( 7 DOWNTO 0 );
      ld_o         : OUT    std_logic_vector ( 1 DOWNTO 0 );
      ld_pc_o      : OUT    std_logic ;
      ld_sp_o      : OUT    std_logic ;
      load_regs_o  : OUT    std_logic ;
      offset_o     : OUT    std_logic_vector ( 15 DOWNTO 0 );
      rd_o         : OUT    std_logic ;
      rst_nmi_o    : OUT    std_logic ;
      sel_pc_in_o  : OUT    std_logic ;
      sel_pc_val_o : OUT    std_logic_vector ( 1 DOWNTO 0 );
      sel_rb_in_o  : OUT    std_logic_vector ( 1 DOWNTO 0 );
      sel_rb_out_o : OUT    std_logic_vector ( 1 DOWNTO 0 );
      sel_reg_o    : OUT    std_logic_vector ( 1 DOWNTO 0 );
      sel_sp_as_o  : OUT    std_logic ;
      sel_sp_in_o  : OUT    std_logic ;
      sync_o       : OUT    std_logic ;
      wr_n_o       : OUT    std_logic ;
      wr_o         : OUT    std_logic
   );
   END COMPONENT;
   COMPONENT FSM_NMI
   PORT (
      clk_clk_i   : IN     std_logic ;
      nmi_n_i     : IN     std_logic ;
      rst_nmi_i   : IN     std_logic ;
      rst_rst_n_i : IN     std_logic ;
      nmi_o       : OUT    std_logic
   );
   END COMPONENT;
   COMPONENT RegBank_AXY
   PORT (
      clk_clk_i    : IN     std_logic ;
      d_regs_in_i  : IN     std_logic_vector (7 DOWNTO 0);
      load_regs_i  : IN     std_logic ;
      rst_rst_n_i  : IN     std_logic ;
      sel_rb_in_i  : IN     std_logic_vector (1 DOWNTO 0);
      sel_rb_out_i : IN     std_logic_vector (1 DOWNTO 0);
      sel_reg_i    : IN     std_logic_vector (1 DOWNTO 0);
      d_regs_out_o : OUT    std_logic_vector (7 DOWNTO 0);
      q_a_o        : OUT    std_logic_vector (7 DOWNTO 0);
      q_x_o        : OUT    std_logic_vector (7 DOWNTO 0);
      q_y_o        : OUT    std_logic_vector (7 DOWNTO 0)
   );
   END COMPONENT;
   COMPONENT Reg_PC
   PORT (
      adr_i        : IN     std_logic_vector (15 DOWNTO 0);
      clk_clk_i    : IN     std_logic ;
      ld_i         : IN     std_logic_vector (1 DOWNTO 0);
      ld_pc_i      : IN     std_logic ;
      offset_i     : IN     std_logic_vector (15 DOWNTO 0);
      rst_rst_n_i  : IN     std_logic ;
      sel_pc_in_i  : IN     std_logic ;
      sel_pc_val_i : IN     std_logic_vector (1 DOWNTO 0);
      adr_nxt_pc_o : OUT    std_logic_vector (15 DOWNTO 0);
      adr_pc_o     : OUT    std_logic_vector (15 DOWNTO 0)
   );
   END COMPONENT;
   COMPONENT Reg_SP
   PORT (
      adr_low_i   : IN     std_logic_vector (7 DOWNTO 0);
      clk_clk_i   : IN     std_logic ;
      ld_low_i    : IN     std_logic ;
      ld_sp_i     : IN     std_logic ;
      rst_rst_n_i : IN     std_logic ;
      sel_sp_as_i : IN     std_logic ;
      sel_sp_in_i : IN     std_logic ;
      adr_sp_o    : OUT    std_logic_vector (15 DOWNTO 0)
   );
   END COMPONENT;
 
   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : FSM_Execution_Unit USE ENTITY R6502_TC.FSM_Execution_Unit;
   FOR ALL : FSM_NMI USE ENTITY R6502_TC.FSM_NMI;
   FOR ALL : RegBank_AXY USE ENTITY R6502_TC.RegBank_AXY;
   FOR ALL : Reg_PC USE ENTITY R6502_TC.Reg_PC;
   FOR ALL : Reg_SP USE ENTITY R6502_TC.Reg_SP;
   -- pragma synthesis_on
 
 
BEGIN
 
   -- ModuleWare code(v1.9) for instance 'U_11' of 'add'
   u_11combo_proc: PROCESS (ch_a_o_i, ch_b_o_i)
   VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);
   VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);
   VARIABLE temp_sum : unsigned(8 DOWNTO 0);
   VARIABLE temp_carry : std_logic;
   BEGIN
      temp_din0 := '0' & ch_a_o_i;
      temp_din1 := '0' & ch_b_o_i;
      temp_carry := '0';
      temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
      d_alu_o_i <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);
      reg_0flag_o_i <= temp_sum(8) ;
   END PROCESS u_11combo_proc;
 
   -- ModuleWare code(v1.9) for instance 'U_8' of 'inv'
   reg_1flag_o_i <= NOT(d_alu_or_o_i);
 
   -- ModuleWare code(v1.9) for instance 'U_9' of 'inv'
   reg_7flag_o_i <= NOT(d_alu_n_o_i);
 
   -- ModuleWare code(v1.9) for instance 'U_10' of 'inv'
   d_alu_n_o_i <= NOT(d_alu_o_i(7));
 
   -- ModuleWare code(v1.9) for instance 'U_7' of 'por'
   d_alu_or_o_i <= d_alu_o_i(0) OR  d_alu_o_i(1) OR  d_alu_o_i(2) OR  d_alu_o_i(3) OR  d_alu_o_i(4) OR  d_alu_o_i(5) OR  d_alu_o_i(6) OR  d_alu_o_i(7);
 
   -- Instance port mappings.
   U_4 : FSM_Execution_Unit
      PORT MAP (
         adr_nxt_pc_i => adr_nxt_pc_o_i,
         adr_pc_i     => adr_pc_o_i,
         adr_sp_i     => adr_sp_o_i,
         clk_clk_i    => clk_clk_i,
         d_alu_i      => d_alu_o_i,
         d_i          => d_i,
         d_regs_out_i => d_regs_out_o_i,
         irq_n_i      => irq_n_i,
         nmi_i        => nmi_o_i,
         q_a_i        => q_a_o_i,
         q_x_i        => q_x_o_i,
         q_y_i        => q_y_o_i,
         rdy_i        => rdy_i,
         reg_0flag_i  => reg_0flag_o_i,
         reg_1flag_i  => reg_1flag_o_i,
         reg_7flag_i  => reg_7flag_o_i,
         rst_rst_n_i  => rst_rst_n_i,
         so_n_i       => so_n_i,
         a_o          => a_o,
         adr_o        => adr_o_i,
         ch_a_o       => ch_a_o_i,
         ch_b_o       => ch_b_o_i,
         d_o          => d_o,
         d_regs_in_o  => d_regs_in_o_i,
         ld_o         => ld_o_i,
         ld_pc_o      => ld_pc_o_i,
         ld_sp_o      => ld_sp_o_i,
         load_regs_o  => load_regs_o_i,
         offset_o     => offset_o_i,
         rd_o         => rd_o,
         rst_nmi_o    => rst_nmi_o_i,
         sel_pc_in_o  => sel_pc_in_o_i,
         sel_pc_val_o => sel_pc_val_o_i,
         sel_rb_in_o  => sel_rb_in_o_i,
         sel_rb_out_o => sel_rb_out_o_i,
         sel_reg_o    => sel_reg_o_i,
         sel_sp_as_o  => sel_sp_as_o_i,
         sel_sp_in_o  => sel_sp_in_o_i,
         sync_o       => sync_o,
         wr_n_o       => wr_n_o,
         wr_o         => wr_o
      );
   U_6 : FSM_NMI
      PORT MAP (
         clk_clk_i   => clk_clk_i,
         nmi_n_i     => nmi_n_i,
         rst_nmi_i   => rst_nmi_o_i,
         rst_rst_n_i => rst_rst_n_i,
         nmi_o       => nmi_o_i
      );
   U_2 : RegBank_AXY
      PORT MAP (
         clk_clk_i    => clk_clk_i,
         d_regs_in_i  => d_regs_in_o_i,
         load_regs_i  => load_regs_o_i,
         rst_rst_n_i  => rst_rst_n_i,
         sel_rb_in_i  => sel_rb_in_o_i,
         sel_rb_out_i => sel_rb_out_o_i,
         sel_reg_i    => sel_reg_o_i,
         d_regs_out_o => d_regs_out_o_i,
         q_a_o        => q_a_o_i,
         q_x_o        => q_x_o_i,
         q_y_o        => q_y_o_i
      );
   U_0 : Reg_PC
      PORT MAP (
         adr_i        => adr_o_i,
         clk_clk_i    => clk_clk_i,
         ld_i         => ld_o_i,
         ld_pc_i      => ld_pc_o_i,
         offset_i     => offset_o_i,
         rst_rst_n_i  => rst_rst_n_i,
         sel_pc_in_i  => sel_pc_in_o_i,
         sel_pc_val_i => sel_pc_val_o_i,
         adr_nxt_pc_o => adr_nxt_pc_o_i,
         adr_pc_o     => adr_pc_o_i
      );
   U_1 : Reg_SP
      PORT MAP (
         adr_low_i   => adr_o_i(7 DOWNTO 0),
         clk_clk_i   => clk_clk_i,
         ld_low_i    => ld_o_i(0),
         ld_sp_i     => ld_sp_o_i,
         rst_rst_n_i => rst_rst_n_i,
         sel_sp_as_i => sel_sp_as_o_i,
         sel_sp_in_i => sel_sp_in_o_i,
         adr_sp_o    => adr_sp_o_i
      );
 
END struct;

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Subversion Repositories cpu6502_true_cycle

[/] [cpu6502_true_cycle/] [trunk/] [rtl/] [vhdl/] [core.vhd] - Blame information for rev 24

Line No.	Rev	Author	Line
1	24	fpga_is_fu	`-- VHDL Entity R6502_TC.Core.symbol`
2			`--`
3			`-- Created:`
4			`-- by - eda.UNKNOWN (ENTW1)`
5			`-- at - 14:13:52 08.03.2010`
6			`--`
7			`-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)`
8			`--`
9			`LIBRARY ieee;`
10			`USE ieee.std_logic_1164.all;`
11			`USE ieee.std_logic_arith.all;`
12
13			`ENTITY Core IS`
14			`PORT(`
15			`clk_clk_i : IN std_logic;`
16			`d_i : IN std_logic_vector (7 DOWNTO 0);`
17			`irq_n_i : IN std_logic;`
18			`nmi_n_i : IN std_logic;`
19			`rdy_i : IN std_logic;`
20			`rst_rst_n_i : IN std_logic;`
21			`so_n_i : IN std_logic;`
22			`a_o : OUT std_logic_vector (15 DOWNTO 0);`
23			`d_o : OUT std_logic_vector (7 DOWNTO 0);`
24			`rd_o : OUT std_logic;`
25			`sync_o : OUT std_logic;`
26			`wr_n_o : OUT std_logic;`
27			`wr_o : OUT std_logic`
28			`);`
29
30			`-- Declarations`
31
32			`END Core ;`
33
34			`-- Jens-D. Gutschmidt Project: R6502_TC`
35			`-- scantara2003@yahoo.de`
36			`-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG`
37			`--`
38			`-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version`
39			`-- 3 of the License, or any later version.`
40			`--`
41			`-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A`
42			`-- PARTICULAR PURPOSE. See the GNU General Public License for more details.`
43			`--`
44			`-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.`
45			`--`
46			`-- CVS Revisins History`
47			`--`
48			`-- $Log: struct.bd,v $`
49			`-- <<-- more -->>`
50			`-- Title: Core`
51			`-- Path: R6502_TC/Core/struct`
52			`-- Edited: by eda on 08 Feb 2010`
53			`--`
54			`-- VHDL Architecture R6502_TC.Core.struct`
55			`--`
56			`-- Created:`
57			`-- by - eda.UNKNOWN (ENTW1)`
58			`-- at - 14:13:53 08.03.2010`
59			`--`
60			`-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)`
61			`--`
62			`LIBRARY ieee;`
63			`USE ieee.std_logic_1164.all;`
64			`USE ieee.std_logic_arith.all;`
65
66			`LIBRARY R6502_TC;`
67
68			`ARCHITECTURE struct OF Core IS`
69
70			`-- Architecture declarations`
71
72			`-- Internal signal declarations`
73			`SIGNAL adr_nxt_pc_o_i : std_logic_vector(15 DOWNTO 0);`
74			`SIGNAL adr_o_i : std_logic_vector(15 DOWNTO 0);`
75			`SIGNAL adr_pc_o_i : std_logic_vector(15 DOWNTO 0);`
76			`SIGNAL adr_sp_o_i : std_logic_vector(15 DOWNTO 0);`
77			`SIGNAL ch_a_o_i : std_logic_vector(7 DOWNTO 0);`
78			`SIGNAL ch_b_o_i : std_logic_vector(7 DOWNTO 0);`
79			`SIGNAL d_alu_n_o_i : std_logic;`
80			`SIGNAL d_alu_o_i : std_logic_vector(7 DOWNTO 0);`
81			`SIGNAL d_alu_or_o_i : std_logic;`
82			`SIGNAL d_regs_in_o_i : std_logic_vector(7 DOWNTO 0);`
83			`SIGNAL d_regs_out_o_i : std_logic_vector(7 DOWNTO 0);`
84			`SIGNAL ld_o_i : std_logic_vector(1 DOWNTO 0);`
85			`SIGNAL ld_pc_o_i : std_logic;`
86			`SIGNAL ld_sp_o_i : std_logic;`
87			`SIGNAL load_regs_o_i : std_logic;`
88			`SIGNAL nmi_o_i : std_logic;`
89			`SIGNAL offset_o_i : std_logic_vector(15 DOWNTO 0);`
90			`SIGNAL q_a_o_i : std_logic_vector(7 DOWNTO 0);`
91			`SIGNAL q_x_o_i : std_logic_vector(7 DOWNTO 0);`
92			`SIGNAL q_y_o_i : std_logic_vector(7 DOWNTO 0);`
93			`SIGNAL reg_0flag_o_i : std_logic;`
94			`SIGNAL reg_1flag_o_i : std_logic;`
95			`SIGNAL reg_7flag_o_i : std_logic;`
96			`SIGNAL rst_nmi_o_i : std_logic;`
97			`SIGNAL sel_pc_in_o_i : std_logic;`
98			`SIGNAL sel_pc_val_o_i : std_logic_vector(1 DOWNTO 0);`
99			`SIGNAL sel_rb_in_o_i : std_logic_vector(1 DOWNTO 0);`
100			`SIGNAL sel_rb_out_o_i : std_logic_vector(1 DOWNTO 0);`
101			`SIGNAL sel_reg_o_i : std_logic_vector(1 DOWNTO 0);`
102			`SIGNAL sel_sp_as_o_i : std_logic;`
103			`SIGNAL sel_sp_in_o_i : std_logic;`
104
105
106			`-- Component Declarations`
107			`COMPONENT FSM_Execution_Unit`
108			`PORT (`
109			`adr_nxt_pc_i : IN std_logic_vector (15 DOWNTO 0);`
110			`adr_pc_i : IN std_logic_vector (15 DOWNTO 0);`
111			`adr_sp_i : IN std_logic_vector (15 DOWNTO 0);`
112			`clk_clk_i : IN std_logic ;`
113			`d_alu_i : IN std_logic_vector ( 7 DOWNTO 0 );`
114			`d_i : IN std_logic_vector ( 7 DOWNTO 0 );`
115			`d_regs_out_i : IN std_logic_vector ( 7 DOWNTO 0 );`
116			`irq_n_i : IN std_logic ;`
117			`nmi_i : IN std_logic ;`
118			`q_a_i : IN std_logic_vector ( 7 DOWNTO 0 );`
119			`q_x_i : IN std_logic_vector ( 7 DOWNTO 0 );`
120			`q_y_i : IN std_logic_vector ( 7 DOWNTO 0 );`
121			`rdy_i : IN std_logic ;`
122			`reg_0flag_i : IN std_logic ;`
123			`reg_1flag_i : IN std_logic ;`
124			`reg_7flag_i : IN std_logic ;`
125			`rst_rst_n_i : IN std_logic ;`
126			`so_n_i : IN std_logic ;`
127			`a_o : OUT std_logic_vector (15 DOWNTO 0);`
128			`adr_o : OUT std_logic_vector (15 DOWNTO 0);`
129			`ch_a_o : OUT std_logic_vector ( 7 DOWNTO 0 );`
130			`ch_b_o : OUT std_logic_vector ( 7 DOWNTO 0 );`
131			`d_o : OUT std_logic_vector ( 7 DOWNTO 0 );`
132			`d_regs_in_o : OUT std_logic_vector ( 7 DOWNTO 0 );`
133			`ld_o : OUT std_logic_vector ( 1 DOWNTO 0 );`
134			`ld_pc_o : OUT std_logic ;`
135			`ld_sp_o : OUT std_logic ;`
136			`load_regs_o : OUT std_logic ;`
137			`offset_o : OUT std_logic_vector ( 15 DOWNTO 0 );`
138			`rd_o : OUT std_logic ;`
139			`rst_nmi_o : OUT std_logic ;`
140			`sel_pc_in_o : OUT std_logic ;`
141			`sel_pc_val_o : OUT std_logic_vector ( 1 DOWNTO 0 );`
142			`sel_rb_in_o : OUT std_logic_vector ( 1 DOWNTO 0 );`
143			`sel_rb_out_o : OUT std_logic_vector ( 1 DOWNTO 0 );`
144			`sel_reg_o : OUT std_logic_vector ( 1 DOWNTO 0 );`
145			`sel_sp_as_o : OUT std_logic ;`
146			`sel_sp_in_o : OUT std_logic ;`
147			`sync_o : OUT std_logic ;`
148			`wr_n_o : OUT std_logic ;`
149			`wr_o : OUT std_logic`
150			`);`
151			`END COMPONENT;`
152			`COMPONENT FSM_NMI`
153			`PORT (`
154			`clk_clk_i : IN std_logic ;`
155			`nmi_n_i : IN std_logic ;`
156			`rst_nmi_i : IN std_logic ;`
157			`rst_rst_n_i : IN std_logic ;`
158			`nmi_o : OUT std_logic`
159			`);`
160			`END COMPONENT;`
161			`COMPONENT RegBank_AXY`
162			`PORT (`
163			`clk_clk_i : IN std_logic ;`
164			`d_regs_in_i : IN std_logic_vector (7 DOWNTO 0);`
165			`load_regs_i : IN std_logic ;`
166			`rst_rst_n_i : IN std_logic ;`
167			`sel_rb_in_i : IN std_logic_vector (1 DOWNTO 0);`
168			`sel_rb_out_i : IN std_logic_vector (1 DOWNTO 0);`
169			`sel_reg_i : IN std_logic_vector (1 DOWNTO 0);`
170			`d_regs_out_o : OUT std_logic_vector (7 DOWNTO 0);`
171			`q_a_o : OUT std_logic_vector (7 DOWNTO 0);`
172			`q_x_o : OUT std_logic_vector (7 DOWNTO 0);`
173			`q_y_o : OUT std_logic_vector (7 DOWNTO 0)`
174			`);`
175			`END COMPONENT;`
176			`COMPONENT Reg_PC`
177			`PORT (`
178			`adr_i : IN std_logic_vector (15 DOWNTO 0);`
179			`clk_clk_i : IN std_logic ;`
180			`ld_i : IN std_logic_vector (1 DOWNTO 0);`
181			`ld_pc_i : IN std_logic ;`
182			`offset_i : IN std_logic_vector (15 DOWNTO 0);`
183			`rst_rst_n_i : IN std_logic ;`
184			`sel_pc_in_i : IN std_logic ;`
185			`sel_pc_val_i : IN std_logic_vector (1 DOWNTO 0);`
186			`adr_nxt_pc_o : OUT std_logic_vector (15 DOWNTO 0);`
187			`adr_pc_o : OUT std_logic_vector (15 DOWNTO 0)`
188			`);`
189			`END COMPONENT;`
190			`COMPONENT Reg_SP`
191			`PORT (`
192			`adr_low_i : IN std_logic_vector (7 DOWNTO 0);`
193			`clk_clk_i : IN std_logic ;`
194			`ld_low_i : IN std_logic ;`
195			`ld_sp_i : IN std_logic ;`
196			`rst_rst_n_i : IN std_logic ;`
197			`sel_sp_as_i : IN std_logic ;`
198			`sel_sp_in_i : IN std_logic ;`
199			`adr_sp_o : OUT std_logic_vector (15 DOWNTO 0)`
200			`);`
201			`END COMPONENT;`
202
203			`-- Optional embedded configurations`
204			`-- pragma synthesis_off`
205			`FOR ALL : FSM_Execution_Unit USE ENTITY R6502_TC.FSM_Execution_Unit;`
206			`FOR ALL : FSM_NMI USE ENTITY R6502_TC.FSM_NMI;`
207			`FOR ALL : RegBank_AXY USE ENTITY R6502_TC.RegBank_AXY;`
208			`FOR ALL : Reg_PC USE ENTITY R6502_TC.Reg_PC;`
209			`FOR ALL : Reg_SP USE ENTITY R6502_TC.Reg_SP;`
210			`-- pragma synthesis_on`
211
212
213			`BEGIN`
214
215			`-- ModuleWare code(v1.9) for instance 'U_11' of 'add'`
216			`u_11combo_proc: PROCESS (ch_a_o_i, ch_b_o_i)`
217			`VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);`
218			`VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);`
219			`VARIABLE temp_sum : unsigned(8 DOWNTO 0);`
220			`VARIABLE temp_carry : std_logic;`
221			`BEGIN`
222			`temp_din0 := '0' & ch_a_o_i;`
223			`temp_din1 := '0' & ch_b_o_i;`
224			`temp_carry := '0';`
225			`temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;`
226			`d_alu_o_i <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);`
227			`reg_0flag_o_i <= temp_sum(8) ;`
228			`END PROCESS u_11combo_proc;`
229
230			`-- ModuleWare code(v1.9) for instance 'U_8' of 'inv'`
231			`reg_1flag_o_i <= NOT(d_alu_or_o_i);`
232
233			`-- ModuleWare code(v1.9) for instance 'U_9' of 'inv'`
234			`reg_7flag_o_i <= NOT(d_alu_n_o_i);`
235
236			`-- ModuleWare code(v1.9) for instance 'U_10' of 'inv'`
237			`d_alu_n_o_i <= NOT(d_alu_o_i(7));`
238
239			`-- ModuleWare code(v1.9) for instance 'U_7' of 'por'`
240			`d_alu_or_o_i <= d_alu_o_i(0) OR d_alu_o_i(1) OR d_alu_o_i(2) OR d_alu_o_i(3) OR d_alu_o_i(4) OR d_alu_o_i(5) OR d_alu_o_i(6) OR d_alu_o_i(7);`
241
242			`-- Instance port mappings.`
243			`U_4 : FSM_Execution_Unit`
244			`PORT MAP (`
245			`adr_nxt_pc_i => adr_nxt_pc_o_i,`
246			`adr_pc_i => adr_pc_o_i,`
247			`adr_sp_i => adr_sp_o_i,`
248			`clk_clk_i => clk_clk_i,`
249			`d_alu_i => d_alu_o_i,`
250			`d_i => d_i,`
251			`d_regs_out_i => d_regs_out_o_i,`
252			`irq_n_i => irq_n_i,`
253			`nmi_i => nmi_o_i,`
254			`q_a_i => q_a_o_i,`
255			`q_x_i => q_x_o_i,`
256			`q_y_i => q_y_o_i,`
257			`rdy_i => rdy_i,`
258			`reg_0flag_i => reg_0flag_o_i,`
259			`reg_1flag_i => reg_1flag_o_i,`
260			`reg_7flag_i => reg_7flag_o_i,`
261			`rst_rst_n_i => rst_rst_n_i,`
262			`so_n_i => so_n_i,`
263			`a_o => a_o,`
264			`adr_o => adr_o_i,`
265			`ch_a_o => ch_a_o_i,`
266			`ch_b_o => ch_b_o_i,`
267			`d_o => d_o,`
268			`d_regs_in_o => d_regs_in_o_i,`
269			`ld_o => ld_o_i,`
270			`ld_pc_o => ld_pc_o_i,`
271			`ld_sp_o => ld_sp_o_i,`
272			`load_regs_o => load_regs_o_i,`
273			`offset_o => offset_o_i,`
274			`rd_o => rd_o,`
275			`rst_nmi_o => rst_nmi_o_i,`
276			`sel_pc_in_o => sel_pc_in_o_i,`
277			`sel_pc_val_o => sel_pc_val_o_i,`
278			`sel_rb_in_o => sel_rb_in_o_i,`
279			`sel_rb_out_o => sel_rb_out_o_i,`
280			`sel_reg_o => sel_reg_o_i,`
281			`sel_sp_as_o => sel_sp_as_o_i,`
282			`sel_sp_in_o => sel_sp_in_o_i,`
283			`sync_o => sync_o,`
284			`wr_n_o => wr_n_o,`
285			`wr_o => wr_o`
286			`);`
287			`U_6 : FSM_NMI`
288			`PORT MAP (`
289			`clk_clk_i => clk_clk_i,`
290			`nmi_n_i => nmi_n_i,`
291			`rst_nmi_i => rst_nmi_o_i,`
292			`rst_rst_n_i => rst_rst_n_i,`
293			`nmi_o => nmi_o_i`
294			`);`
295			`U_2 : RegBank_AXY`
296			`PORT MAP (`
297			`clk_clk_i => clk_clk_i,`
298			`d_regs_in_i => d_regs_in_o_i,`
299			`load_regs_i => load_regs_o_i,`
300			`rst_rst_n_i => rst_rst_n_i,`
301			`sel_rb_in_i => sel_rb_in_o_i,`
302			`sel_rb_out_i => sel_rb_out_o_i,`
303			`sel_reg_i => sel_reg_o_i,`
304			`d_regs_out_o => d_regs_out_o_i,`
305			`q_a_o => q_a_o_i,`
306			`q_x_o => q_x_o_i,`
307			`q_y_o => q_y_o_i`
308			`);`
309			`U_0 : Reg_PC`
310			`PORT MAP (`
311			`adr_i => adr_o_i,`
312			`clk_clk_i => clk_clk_i,`
313			`ld_i => ld_o_i,`
314			`ld_pc_i => ld_pc_o_i,`
315			`offset_i => offset_o_i,`
316			`rst_rst_n_i => rst_rst_n_i,`
317			`sel_pc_in_i => sel_pc_in_o_i,`
318			`sel_pc_val_i => sel_pc_val_o_i,`
319			`adr_nxt_pc_o => adr_nxt_pc_o_i,`
320			`adr_pc_o => adr_pc_o_i`
321			`);`
322			`U_1 : Reg_SP`
323			`PORT MAP (`
324			`adr_low_i => adr_o_i(7 DOWNTO 0),`
325			`clk_clk_i => clk_clk_i,`
326			`ld_low_i => ld_o_i(0),`
327			`ld_sp_i => ld_sp_o_i,`
328			`rst_rst_n_i => rst_rst_n_i,`
329			`sel_sp_as_i => sel_sp_as_o_i,`
330			`sel_sp_in_i => sel_sp_in_o_i,`
331			`adr_sp_o => adr_sp_o_i`
332			`);`
333
334			`END struct;`