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fpga_is_fu |
-- VHDL Entity R6502_TC.Core.symbol
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--
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-- Created:
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-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
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-- at - 19:07:10 08.04.2008
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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entity Core is
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port(
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clk_clk_i : in std_logic;
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d_i : in std_logic_vector (7 downto 0);
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irq_n_i : in std_logic;
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nmi_i : in std_logic;
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rdy_i : in std_logic;
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rst_rst_n_i : in std_logic;
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so_n_i : in std_logic;
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a_o : out std_logic_vector (15 downto 0);
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d_o : out std_logic_vector (7 downto 0);
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rd_o : out std_logic;
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sync_o : out std_logic;
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wr_n_o : out std_logic;
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wr_o : out std_logic
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);
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-- Declarations
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end Core ;
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-- Jens-D. Gutschmidt Project: R6502_TC
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-- scantara2003@yahoo.de
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-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG
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--
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version
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-- 3 of the License, or any later version.
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--
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A
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-- PARTICULAR PURPOSE. See the GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- CVS Revisins History
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--
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-- $Log: not supported by cvs2svn $
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--
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-- Title: Core of 6502
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-- Path: R6502_TC/Core/struct
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-- Edited: by eda on 08 Apr 2008
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--
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-- VHDL Architecture R6502_TC.Core.struct
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--
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-- Created:
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-- by - eda.UNKNOWN (ENTWICKL4-XP-PR)
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-- at - 19:07:10 08.04.2008
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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library R6502_TC;
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architecture struct of Core is
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-- Architecture declarations
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-- Internal signal declarations
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signal adr_nxt_pc_o_i : std_logic_vector(15 downto 0);
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signal adr_nxt_sp_o_i : std_logic_vector(15 downto 0);
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signal adr_o_i : std_logic_vector(15 downto 0);
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signal adr_pc_o_i : std_logic_vector(15 downto 0);
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signal adr_sp_o_i : std_logic_vector(15 downto 0);
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signal ch_a_o_i : std_logic_vector(7 downto 0);
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signal ch_b_o_i : std_logic_vector(7 downto 0);
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signal cout_pc_o_i : std_logic;
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signal d_alu_o_i : std_logic_vector(7 downto 0);
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signal d_regs_in_o_i : std_logic_vector(7 downto 0);
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signal d_regs_out_o_i : std_logic_vector(7 downto 0);
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signal ld_o_i : std_logic_vector(1 downto 0);
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signal ld_pc_o_i : std_logic;
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signal ld_sp_o_i : std_logic;
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signal load_regs_o_i : std_logic;
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signal offset_o_i : std_logic_vector(15 downto 0);
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signal q_a_o_i : std_logic_vector(7 downto 0);
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signal q_x_o_i : std_logic_vector(7 downto 0);
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signal q_y_o_i : std_logic_vector(7 downto 0);
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signal reg_0flag_core_o_i : std_logic;
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signal reg_0flag_o_i : std_logic;
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signal reg_1flag_o_i : std_logic;
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signal reg_3flag_core_o_i : std_logic;
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signal reg_6flag_o_i : std_logic;
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signal reg_7flag_core_o_i : std_logic;
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signal reg_7flag_o_i : std_logic;
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signal rst_rst_int_o_i : std_logic;
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signal sel_alu_as_o_i : std_logic;
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signal sel_alu_out_o_i : std_logic_vector(2 downto 0);
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signal sel_pc_as_o_i : std_logic;
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signal sel_pc_in_o_i : std_logic_vector(1 downto 0);
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signal sel_pc_val_o_i : std_logic_vector(1 downto 0);
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signal sel_rb_in_o_i : std_logic_vector(2 downto 0);
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signal sel_rb_out_o_i : std_logic_vector(2 downto 0);
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signal sel_reg_o_i : std_logic_vector(1 downto 0);
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signal sel_sp_as_o_i : std_logic;
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signal sel_sp_in_o_i : std_logic_vector(1 downto 0);
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signal sel_sp_val_o_i : std_logic_vector(1 downto 0);
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-- Component Declarations
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component ALU
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port (
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ch_a_i : in std_logic_vector (7 downto 0);
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ch_b_i : in std_logic_vector (7 downto 0);
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reg_0flag_core_i : in std_logic ;
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reg_3flag_core_i : in std_logic ;
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reg_7flag_core_i : in std_logic ;
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sel_alu_as_i : in std_logic ;
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sel_alu_out_i : in std_logic_vector (2 downto 0);
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d_alu_o : out std_logic_vector (7 downto 0);
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reg_0flag_o : out std_logic ;
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reg_1flag_o : out std_logic ;
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reg_6flag_o : out std_logic ;
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reg_7flag_o : out std_logic
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);
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end component;
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component RegBank_AXY
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port (
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clk_clk_i : in std_logic ;
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d_regs_in_i : in std_logic_vector (7 downto 0);
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load_regs_i : in std_logic ;
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rst_rst_i : in std_logic ;
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sel_rb_in_i : in std_logic_vector (2 downto 0);
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sel_rb_out_i : in std_logic_vector (1 downto 0);
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sel_reg_i : in std_logic_vector (1 downto 0);
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d_regs_out_o : out std_logic_vector (7 downto 0);
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q_a_o : out std_logic_vector (7 downto 0);
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q_x_o : out std_logic_vector (7 downto 0);
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q_y_o : out std_logic_vector (7 downto 0)
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);
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end component;
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component Reg_PC
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port (
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adr_i : in std_logic_vector (15 downto 0);
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clk_clk_i : in std_logic ;
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ld_i : in std_logic_vector (1 downto 0);
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ld_pc_i : in std_logic ;
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offset_i : in std_logic_vector (15 downto 0);
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rst_rst_i : in std_logic ;
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sel_pc_as_i : in std_logic ;
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sel_pc_in_i : in std_logic ;
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sel_pc_val_i : in std_logic_vector (1 downto 0);
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adr_nxt_pc_o : out std_logic_vector (15 downto 0);
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adr_pc_o : out std_logic_vector (15 downto 0);
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cout_pc_o : out std_logic
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);
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end component;
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component Reg_SP
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port (
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adr_i : in std_logic_vector (15 downto 0);
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clk_clk_i : in std_logic ;
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ld_i : in std_logic_vector (1 downto 0);
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ld_sp_i : in std_logic ;
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rst_rst_i : in std_logic ;
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sel_sp_as_i : in std_logic ;
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sel_sp_in_i : in std_logic ;
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sel_sp_val_i : in std_logic ;
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adr_nxt_sp_o : out std_logic_vector (15 downto 0);
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adr_sp_o : out std_logic_vector (15 downto 0)
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);
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end component;
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component fsm_core_V2_0
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port (
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adr_nxt_pc_i : in std_logic_vector (15 downto 0);
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adr_nxt_sp_i : in std_logic_vector (15 downto 0);
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adr_pc_i : in std_logic_vector (15 downto 0);
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adr_sp_i : in std_logic_vector (15 downto 0);
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clk_clk_i : in std_logic ;
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cout_pc_i : in std_logic ;
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d_alu_i : in std_logic_vector ( 7 downto 0 );
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d_i : in std_logic_vector ( 7 downto 0 );
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d_regs_out_i : in std_logic_vector ( 7 downto 0 );
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irq_n_i : in std_logic ;
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nmi_i : in std_logic ;
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q_a_i : in std_logic_vector ( 7 downto 0 );
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q_x_i : in std_logic_vector ( 7 downto 0 );
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q_y_i : in std_logic_vector ( 7 downto 0 );
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rdy_i : in std_logic ;
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reg_0flag_i : in std_logic ;
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reg_1flag_i : in std_logic ;
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reg_6flag_i : in std_logic ;
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reg_7flag_i : in std_logic ;
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rst_rst_n_i : in std_logic ;
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so_n_i : in std_logic ;
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a_o : out std_logic_vector (15 downto 0);
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adr_o : out std_logic_vector (15 downto 0);
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ch_a_o : out std_logic_vector ( 7 downto 0 );
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ch_b_o : out std_logic_vector ( 7 downto 0 );
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d_o : out std_logic_vector ( 7 downto 0 );
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d_regs_in_o : out std_logic_vector ( 7 downto 0 );
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ld_o : out std_logic_vector ( 1 downto 0 );
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ld_pc_o : out std_logic ;
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ld_sp_o : out std_logic ;
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load_regs_o : out std_logic ;
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offset_o : out std_logic_vector ( 15 downto 0 );
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rd_o : out std_logic ;
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reg_0flag_o : out std_logic ;
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reg_1flag_o : out std_logic ;
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reg_3flag_o : out std_logic ;
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reg_7flag_o : out std_logic ;
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sync_o : out std_logic ;
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wr_n_o : out std_logic ;
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wr_o : out std_logic ;
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sel_alu_as_o_i : inout std_logic ;
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sel_alu_out_o_i : inout std_logic_vector ( 2 downto 0 );
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sel_pc_as_o_i : inout std_logic ;
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sel_pc_in_o_i : inout std_logic_vector ( 1 downto 0 );
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sel_pc_val_o_i : inout std_logic_vector ( 1 downto 0 );
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sel_rb_in_o_i : inout std_logic_vector ( 2 downto 0 );
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sel_rb_out_o_i : inout std_logic_vector ( 2 downto 0 );
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sel_reg_o_i : inout std_logic_vector ( 1 downto 0 );
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sel_sp_as_o_i : inout std_logic ;
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sel_sp_in_o_i : inout std_logic_vector ( 1 downto 0 );
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sel_sp_val_o_i : inout std_logic_vector ( 1 downto 0 )
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);
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end component;
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-- Optional embedded configurations
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-- pragma synthesis_off
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for all : ALU use entity R6502_TC.ALU;
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for all : RegBank_AXY use entity R6502_TC.RegBank_AXY;
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for all : Reg_PC use entity R6502_TC.Reg_PC;
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for all : Reg_SP use entity R6502_TC.Reg_SP;
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for all : fsm_core_V2_0 use entity R6502_TC.fsm_core_V2_0;
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-- pragma synthesis_on
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begin
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242 |
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243 |
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-- ModuleWare code(v1.9) for instance 'U_5' of 'inv'
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rst_rst_int_o_i <= not(rst_rst_n_i);
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-- Instance port mappings.
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U_3 : ALU
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port map (
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ch_a_i => ch_a_o_i,
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ch_b_i => ch_b_o_i,
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reg_0flag_core_i => reg_0flag_core_o_i,
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reg_3flag_core_i => reg_3flag_core_o_i,
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reg_7flag_core_i => reg_7flag_core_o_i,
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sel_alu_as_i => sel_alu_as_o_i,
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sel_alu_out_i => sel_alu_out_o_i,
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256 |
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d_alu_o => d_alu_o_i,
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reg_0flag_o => reg_0flag_o_i,
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258 |
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reg_1flag_o => reg_1flag_o_i,
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reg_6flag_o => reg_6flag_o_i,
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reg_7flag_o => reg_7flag_o_i
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);
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262 |
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U_2 : RegBank_AXY
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263 |
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port map (
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264 |
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clk_clk_i => clk_clk_i,
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d_regs_in_i => d_regs_in_o_i,
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load_regs_i => load_regs_o_i,
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rst_rst_i => rst_rst_int_o_i,
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sel_rb_in_i => sel_rb_in_o_i,
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sel_rb_out_i => sel_rb_out_o_i(1 DOWNTO 0),
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sel_reg_i => sel_reg_o_i,
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d_regs_out_o => d_regs_out_o_i,
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q_a_o => q_a_o_i,
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q_x_o => q_x_o_i,
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274 |
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q_y_o => q_y_o_i
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275 |
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);
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276 |
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U_0 : Reg_PC
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port map (
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278 |
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adr_i => adr_o_i,
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clk_clk_i => clk_clk_i,
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280 |
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ld_i => ld_o_i,
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ld_pc_i => ld_pc_o_i,
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282 |
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offset_i => offset_o_i,
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283 |
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rst_rst_i => rst_rst_int_o_i,
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sel_pc_as_i => sel_pc_as_o_i,
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sel_pc_in_i => sel_pc_in_o_i(0),
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286 |
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sel_pc_val_i => sel_pc_val_o_i,
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adr_nxt_pc_o => adr_nxt_pc_o_i,
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288 |
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adr_pc_o => adr_pc_o_i,
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289 |
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cout_pc_o => cout_pc_o_i
|
290 |
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);
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291 |
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U_1 : Reg_SP
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292 |
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port map (
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293 |
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adr_i => adr_o_i,
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294 |
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clk_clk_i => clk_clk_i,
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295 |
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ld_i => ld_o_i,
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296 |
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ld_sp_i => ld_sp_o_i,
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297 |
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rst_rst_i => rst_rst_int_o_i,
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298 |
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sel_sp_as_i => sel_sp_as_o_i,
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299 |
|
|
sel_sp_in_i => sel_sp_in_o_i(0),
|
300 |
|
|
sel_sp_val_i => sel_sp_val_o_i(0),
|
301 |
|
|
adr_nxt_sp_o => adr_nxt_sp_o_i,
|
302 |
|
|
adr_sp_o => adr_sp_o_i
|
303 |
|
|
);
|
304 |
|
|
U_4 : fsm_core_V2_0
|
305 |
|
|
port map (
|
306 |
|
|
adr_nxt_pc_i => adr_nxt_pc_o_i,
|
307 |
|
|
adr_nxt_sp_i => adr_nxt_sp_o_i,
|
308 |
|
|
adr_pc_i => adr_pc_o_i,
|
309 |
|
|
adr_sp_i => adr_sp_o_i,
|
310 |
|
|
clk_clk_i => clk_clk_i,
|
311 |
|
|
cout_pc_i => cout_pc_o_i,
|
312 |
|
|
d_alu_i => d_alu_o_i,
|
313 |
|
|
d_i => d_i,
|
314 |
|
|
d_regs_out_i => d_regs_out_o_i,
|
315 |
|
|
irq_n_i => irq_n_i,
|
316 |
|
|
nmi_i => nmi_i,
|
317 |
|
|
q_a_i => q_a_o_i,
|
318 |
|
|
q_x_i => q_x_o_i,
|
319 |
|
|
q_y_i => q_y_o_i,
|
320 |
|
|
rdy_i => rdy_i,
|
321 |
|
|
reg_0flag_i => reg_0flag_o_i,
|
322 |
|
|
reg_1flag_i => reg_1flag_o_i,
|
323 |
|
|
reg_6flag_i => reg_6flag_o_i,
|
324 |
|
|
reg_7flag_i => reg_7flag_o_i,
|
325 |
|
|
rst_rst_n_i => rst_rst_n_i,
|
326 |
|
|
so_n_i => so_n_i,
|
327 |
|
|
a_o => a_o,
|
328 |
|
|
adr_o => adr_o_i,
|
329 |
|
|
ch_a_o => ch_a_o_i,
|
330 |
|
|
ch_b_o => ch_b_o_i,
|
331 |
|
|
d_o => d_o,
|
332 |
|
|
d_regs_in_o => d_regs_in_o_i,
|
333 |
|
|
ld_o => ld_o_i,
|
334 |
|
|
ld_pc_o => ld_pc_o_i,
|
335 |
|
|
ld_sp_o => ld_sp_o_i,
|
336 |
|
|
load_regs_o => load_regs_o_i,
|
337 |
|
|
offset_o => offset_o_i,
|
338 |
|
|
rd_o => rd_o,
|
339 |
|
|
reg_0flag_o => reg_0flag_core_o_i,
|
340 |
|
|
reg_1flag_o => open,
|
341 |
|
|
reg_3flag_o => reg_3flag_core_o_i,
|
342 |
|
|
reg_7flag_o => reg_7flag_core_o_i,
|
343 |
|
|
sync_o => sync_o,
|
344 |
|
|
wr_n_o => wr_n_o,
|
345 |
|
|
wr_o => wr_o,
|
346 |
|
|
sel_alu_as_o_i => sel_alu_as_o_i,
|
347 |
|
|
sel_alu_out_o_i => sel_alu_out_o_i,
|
348 |
|
|
sel_pc_as_o_i => sel_pc_as_o_i,
|
349 |
|
|
sel_pc_in_o_i => sel_pc_in_o_i,
|
350 |
|
|
sel_pc_val_o_i => sel_pc_val_o_i,
|
351 |
|
|
sel_rb_in_o_i => sel_rb_in_o_i,
|
352 |
|
|
sel_rb_out_o_i => sel_rb_out_o_i,
|
353 |
|
|
sel_reg_o_i => sel_reg_o_i,
|
354 |
|
|
sel_sp_as_o_i => sel_sp_as_o_i,
|
355 |
|
|
sel_sp_in_o_i => sel_sp_in_o_i,
|
356 |
|
|
sel_sp_val_o_i => sel_sp_val_o_i
|
357 |
|
|
);
|
358 |
|
|
|
359 |
|
|
end struct;
|