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-- VHDL Entity R6502_TC.FSM_Execution_Unit.symbol

--

-- Created:

--          by - eda.UNKNOWN (TEST)

--          at - 19:21:47 07.01.2009

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

--

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ENTITY FSM_Execution_Unit IS

   PORT(

      adr_nxt_pc_i : IN     std_logic_vector (15 DOWNTO 0);

      adr_pc_i     : IN     std_logic_vector (15 DOWNTO 0);

      adr_sp_i     : IN     std_logic_vector (15 DOWNTO 0);

      clk_clk_i    : IN     std_logic;

      d_alu_i      : IN     std_logic_vector ( 7 DOWNTO 0 );

      d_i          : IN     std_logic_vector ( 7 DOWNTO 0 );

      d_regs_out_i : IN     std_logic_vector ( 7 DOWNTO 0 );

      irq_n_i      : IN     std_logic;

      nmi_i        : IN     std_logic;

      q_a_i        : IN     std_logic_vector ( 7 DOWNTO 0 );

      q_x_i        : IN     std_logic_vector ( 7 DOWNTO 0 );

      q_y_i        : IN     std_logic_vector ( 7 DOWNTO 0 );

      rdy_i        : IN     std_logic;

      reg_0flag_i  : IN     std_logic;

      reg_1flag_i  : IN     std_logic;

      reg_7flag_i  : IN     std_logic;

      rst_rst_n_i  : IN     std_logic;

      so_n_i       : IN     std_logic;

      a_o          : OUT    std_logic_vector (15 DOWNTO 0);

      adr_o        : OUT    std_logic_vector (15 DOWNTO 0);

      ch_a_o       : OUT    std_logic_vector ( 7 DOWNTO 0 );

      ch_b_o       : OUT    std_logic_vector ( 7 DOWNTO 0 );

      d_o          : OUT    std_logic_vector ( 7 DOWNTO 0 );

      d_regs_in_o  : OUT    std_logic_vector ( 7 DOWNTO 0 );

      fetch_o      : OUT    std_logic;

      ld_o         : OUT    std_logic_vector ( 1 DOWNTO 0 );

      ld_pc_o      : OUT    std_logic;

      ld_sp_o      : OUT    std_logic;

      load_regs_o  : OUT    std_logic;

      offset_o     : OUT    std_logic_vector ( 15 DOWNTO 0 );

      rd_o         : OUT    std_logic;

      sel_pc_in_o  : OUT    std_logic;

      sel_pc_val_o : OUT    std_logic_vector ( 1 DOWNTO 0 );

      sel_rb_in_o  : OUT    std_logic_vector ( 1 DOWNTO 0 );

      sel_rb_out_o : OUT    std_logic_vector ( 1 DOWNTO 0 );

      sel_reg_o    : OUT    std_logic_vector ( 1 DOWNTO 0 );

      sel_sp_as_o  : OUT    std_logic;

      sel_sp_in_o  : OUT    std_logic;

      sync_o       : OUT    std_logic;

      wr_n_o       : OUT    std_logic;

      wr_o         : OUT    std_logic

   );

-- Declarations

END FSM_Execution_Unit ;

-- Jens-D. Gutschmidt     Project:  R6502_TC  

-- scantara2003@yahoo.de                      

-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG                                                                                     

--                                                                                                                                             

-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by   

-- the Free Software Foundation, either version 3 of the License, or any later version.                                                        

--                                                                                                                                             

-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of              

-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.                                  

--                                                                                                                                             

-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.     

--                                                                                                                                             

-- CVS Revisins History                                                                                                                        

--                                                                                                                                             

-- $Log: not supported by cvs2svn $                                                                                                                            

--   <<-- more -->>                                                                                                                            

-- Title:  FSM Execution Unit for all op codes  

-- Path:  R6502_TC/FSM_Execution_Unit/fsm  

-- Edited:  by eda on 07 Jan 2009  

--

-- VHDL Architecture R6502_TC.FSM_Execution_Unit.fsm

--

-- Created:

--          by - eda.UNKNOWN (TEST)

--          at - 19:21:50 07.01.2009

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

--

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ARCHITECTURE fsm OF FSM_Execution_Unit IS

   -- Architecture Declarations

   SIGNAL reg_F : std_logic_vector( 7 DOWNTO 0 );

   SIGNAL reg_sel_pc_in : std_logic;

   SIGNAL reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );

   SIGNAL reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );

   SIGNAL reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );

   SIGNAL reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );

   SIGNAL reg_sel_sp_as : std_logic;

   SIGNAL reg_sel_sp_in : std_logic;

   SIGNAL sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );

   SIGNAL sig_PC : std_logic_vector(15 DOWNTO 0);

   SIGNAL sig_RD : std_logic;

   SIGNAL sig_RWn : std_logic;

   SIGNAL sig_SYNC : std_logic;

   SIGNAL sig_WR : std_logic;

   SIGNAL zw_ALU : std_logic_vector( 8 DOWNTO 0 );

   SIGNAL zw_ALU1 : std_logic_vector( 4 DOWNTO 0 );

   SIGNAL zw_ALU2 : std_logic_vector( 4 DOWNTO 0 );

   SIGNAL zw_ALU3 : std_logic_vector( 4 DOWNTO 0 );

   SIGNAL zw_ALU4 : std_logic_vector( 4 DOWNTO 0 );

   SIGNAL zw_ALU5 : std_logic_vector( 3 DOWNTO 0 );

   SIGNAL zw_ALU6 : std_logic_vector( 3 DOWNTO 0 );

   SIGNAL zw_REG_NMI : std_logic;

   SIGNAL zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );

   SIGNAL zw_b1 : std_logic_vector( 7 DOWNTO 0 );

   SIGNAL zw_b2 : std_logic_vector( 7 DOWNTO 0 );

   SIGNAL zw_b3 : std_logic_vector( 7 DOWNTO 0 );

   SIGNAL zw_b4 : std_logic_vector( 7 DOWNTO 0 );

   SIGNAL zw_so : std_logic;

   SUBTYPE STATE_TYPE IS

      std_logic_vector(7 DOWNTO 0);

   -- Hard encoding

   CONSTANT FETCH : STATE_TYPE := "00000000";

   CONSTANT s1 : STATE_TYPE := "00000001";

   CONSTANT s2 : STATE_TYPE := "00000011";

   CONSTANT s5 : STATE_TYPE := "00000010";

   CONSTANT s3 : STATE_TYPE := "00000110";

   CONSTANT s4 : STATE_TYPE := "00000111";

   CONSTANT s12 : STATE_TYPE := "00000101";

   CONSTANT s16 : STATE_TYPE := "00000100";

   CONSTANT s17 : STATE_TYPE := "00001100";

   CONSTANT s24 : STATE_TYPE := "00001101";

   CONSTANT s25 : STATE_TYPE := "00001111";

   CONSTANT s271 : STATE_TYPE := "00001110";

   CONSTANT s273 : STATE_TYPE := "00001010";

   CONSTANT s304 : STATE_TYPE := "00001011";

   CONSTANT s307 : STATE_TYPE := "00001001";

   CONSTANT s177 : STATE_TYPE := "00001000";

   CONSTANT s180 : STATE_TYPE := "00011000";

   CONSTANT s181 : STATE_TYPE := "00011001";

   CONSTANT s182 : STATE_TYPE := "00011011";

   CONSTANT s183 : STATE_TYPE := "00011010";

   CONSTANT s184 : STATE_TYPE := "00011110";

   CONSTANT s185 : STATE_TYPE := "00011111";

   CONSTANT s186 : STATE_TYPE := "00011101";

   CONSTANT s187 : STATE_TYPE := "00011100";

   CONSTANT s188 : STATE_TYPE := "00010100";

   CONSTANT s189 : STATE_TYPE := "00010101";

   CONSTANT s190 : STATE_TYPE := "00010111";

   CONSTANT s191 : STATE_TYPE := "00010110";

   CONSTANT s192 : STATE_TYPE := "00010010";

   CONSTANT s193 : STATE_TYPE := "00010011";

   CONSTANT s377 : STATE_TYPE := "00010001";

   CONSTANT s381 : STATE_TYPE := "00010000";

   CONSTANT s378 : STATE_TYPE := "00110000";

   CONSTANT s382 : STATE_TYPE := "00110001";

   CONSTANT s379 : STATE_TYPE := "00110011";

   CONSTANT s383 : STATE_TYPE := "00110010";

   CONSTANT s384 : STATE_TYPE := "00110110";

   CONSTANT s380 : STATE_TYPE := "00110111";

   CONSTANT s385 : STATE_TYPE := "00110101";

   CONSTANT s386 : STATE_TYPE := "00110100";

   CONSTANT s387 : STATE_TYPE := "00111100";

   CONSTANT s388 : STATE_TYPE := "00111101";

   CONSTANT s389 : STATE_TYPE := "00111111";

   CONSTANT s391 : STATE_TYPE := "00111110";

   CONSTANT s392 : STATE_TYPE := "00111010";

   CONSTANT s390 : STATE_TYPE := "00111011";

   CONSTANT s393 : STATE_TYPE := "00111001";

   CONSTANT s394 : STATE_TYPE := "00111000";

   CONSTANT s395 : STATE_TYPE := "00101000";

   CONSTANT s396 : STATE_TYPE := "00101001";

   CONSTANT s397 : STATE_TYPE := "00101011";

   CONSTANT s398 : STATE_TYPE := "00101010";

   CONSTANT s399 : STATE_TYPE := "00101110";

   CONSTANT s400 : STATE_TYPE := "00101111";

   CONSTANT s401 : STATE_TYPE := "00101101";

   CONSTANT s526 : STATE_TYPE := "00101100";

   CONSTANT s527 : STATE_TYPE := "00100100";

   CONSTANT s528 : STATE_TYPE := "00100101";

   CONSTANT s529 : STATE_TYPE := "00100111";

   CONSTANT s530 : STATE_TYPE := "00100110";

   CONSTANT s531 : STATE_TYPE := "00100010";

   CONSTANT s544 : STATE_TYPE := "00100011";

   CONSTANT s545 : STATE_TYPE := "00100001";

   CONSTANT s546 : STATE_TYPE := "00100000";

   CONSTANT s547 : STATE_TYPE := "01100000";

   CONSTANT s549 : STATE_TYPE := "01100001";

   CONSTANT s550 : STATE_TYPE := "01100011";

   CONSTANT s404 : STATE_TYPE := "01100010";

   CONSTANT s556 : STATE_TYPE := "01100110";

   CONSTANT s557 : STATE_TYPE := "01100111";

   CONSTANT s579 : STATE_TYPE := "01100101";

   CONSTANT s201 : STATE_TYPE := "01100100";

   CONSTANT s202 : STATE_TYPE := "01101100";

   CONSTANT s210 : STATE_TYPE := "01101101";

   CONSTANT s211 : STATE_TYPE := "01101111";

   CONSTANT s215 : STATE_TYPE := "01101110";

   CONSTANT s217 : STATE_TYPE := "01101010";

   CONSTANT s218 : STATE_TYPE := "01101011";

   CONSTANT s222 : STATE_TYPE := "01101001";

   CONSTANT s223 : STATE_TYPE := "01101000";

   CONSTANT s224 : STATE_TYPE := "01111000";

   CONSTANT s225 : STATE_TYPE := "01111001";

   CONSTANT s226 : STATE_TYPE := "01111011";

   CONSTANT s243 : STATE_TYPE := "01111010";

   CONSTANT s244 : STATE_TYPE := "01111110";

   CONSTANT s247 : STATE_TYPE := "01111111";

   CONSTANT s344 : STATE_TYPE := "01111101";

   CONSTANT s343 : STATE_TYPE := "01111100";

   CONSTANT s250 : STATE_TYPE := "01110100";

   CONSTANT s251 : STATE_TYPE := "01110101";

   CONSTANT s351 : STATE_TYPE := "01110111";

   CONSTANT s361 : STATE_TYPE := "01110110";

   CONSTANT s360 : STATE_TYPE := "01110010";

   CONSTANT s403 : STATE_TYPE := "01110011";

   CONSTANT s406 : STATE_TYPE := "01110001";

   CONSTANT s407 : STATE_TYPE := "01110000";

   CONSTANT s409 : STATE_TYPE := "01010000";

   CONSTANT s412 : STATE_TYPE := "01010001";

   CONSTANT s413 : STATE_TYPE := "01010011";

   CONSTANT s416 : STATE_TYPE := "01010010";

   CONSTANT s418 : STATE_TYPE := "01010110";

   CONSTANT s510 : STATE_TYPE := "01010111";

   CONSTANT s553 : STATE_TYPE := "01010101";

   CONSTANT s555 : STATE_TYPE := "01010100";

   CONSTANT s558 : STATE_TYPE := "01011100";

   CONSTANT s560 : STATE_TYPE := "01011101";

   CONSTANT s561 : STATE_TYPE := "01011111";

   CONSTANT s563 : STATE_TYPE := "01011110";

   CONSTANT s564 : STATE_TYPE := "01011010";

   CONSTANT s565 : STATE_TYPE := "01011011";

   CONSTANT s566 : STATE_TYPE := "01011001";

   CONSTANT s266 : STATE_TYPE := "01011000";

   CONSTANT s301 : STATE_TYPE := "01001000";

   CONSTANT s302 : STATE_TYPE := "01001001";

   CONSTANT RES : STATE_TYPE := "01001011";

   CONSTANT s511 : STATE_TYPE := "01001010";

   CONSTANT s559 : STATE_TYPE := "01001110";

   CONSTANT s562 : STATE_TYPE := "01001111";

   CONSTANT s567 : STATE_TYPE := "01001101";

   CONSTANT s568 : STATE_TYPE := "01001100";

   CONSTANT s569 : STATE_TYPE := "01000100";

   CONSTANT s570 : STATE_TYPE := "01000101";

   CONSTANT s571 : STATE_TYPE := "01000111";

   CONSTANT s572 : STATE_TYPE := "01000110";

   CONSTANT s573 : STATE_TYPE := "01000010";

   CONSTANT s574 : STATE_TYPE := "01000011";

   CONSTANT s548 : STATE_TYPE := "01000001";

   CONSTANT s551 : STATE_TYPE := "01000000";

   CONSTANT s552 : STATE_TYPE := "11000000";

   CONSTANT s575 : STATE_TYPE := "11000001";

   CONSTANT s576 : STATE_TYPE := "11000011";

   CONSTANT s577 : STATE_TYPE := "11000010";

   CONSTANT s532 : STATE_TYPE := "11000110";

   CONSTANT s533 : STATE_TYPE := "11000111";

   CONSTANT s534 : STATE_TYPE := "11000101";

   CONSTANT s535 : STATE_TYPE := "11000100";

   CONSTANT s536 : STATE_TYPE := "11001100";

   CONSTANT s537 : STATE_TYPE := "11001101";

   -- Declare current and next state signals

   SIGNAL current_state : STATE_TYPE;

   SIGNAL next_state : STATE_TYPE;

   -- Declare any pre-registered internal signals

   SIGNAL d_o_cld : std_logic_vector ( 7 DOWNTO 0 );

   SIGNAL rd_o_cld : std_logic ;

   SIGNAL sync_o_cld : std_logic ;

   SIGNAL wr_n_o_cld : std_logic ;

   SIGNAL wr_o_cld : std_logic ;

BEGIN

   -----------------------------------------------------------------

   clocked_proc : PROCESS (

      clk_clk_i,

      rst_rst_n_i

   )

   -----------------------------------------------------------------

   BEGIN

      IF (rst_rst_n_i = '0') THEN

         current_state <= RES;

         -- Default Reset Values

         d_o_cld <= X"00";

         rd_o_cld <= '0';

         sync_o_cld <= '0';

         wr_n_o_cld <= '1';

         wr_o_cld <= '0';

         reg_F <= "00000100";

         reg_sel_pc_in <= '0';

         reg_sel_pc_val <= "00";

         reg_sel_rb_in <= "00";

         reg_sel_rb_out <= "00";

         reg_sel_reg <= "00";

         reg_sel_sp_as <= '0';

         reg_sel_sp_in <= '0';

         sig_PC <= X"0000";

         zw_REG_NMI <= '0';

         zw_REG_OP <= X"00";

         zw_b1 <= X"00";

         zw_b2 <= X"00";

         zw_b3 <= X"00";

         zw_b4 <= X"00";

         zw_so <= '0';

      ELSIF (clk_clk_i'EVENT AND clk_clk_i = '1') THEN

         current_state <= next_state;

         -- Default Assignment To Internals

         reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0);

         reg_sel_pc_in <= reg_sel_pc_in;

         reg_sel_pc_val <= reg_sel_pc_val;

         reg_sel_rb_in <= reg_sel_rb_in;

         reg_sel_rb_out <= reg_sel_rb_out;

         reg_sel_reg <= reg_sel_reg;

         reg_sel_sp_as <= reg_sel_sp_as;

         reg_sel_sp_in <= reg_sel_sp_in;

         sig_PC <= sig_PC;

         zw_REG_NMI <= zw_REG_NMI or nmi_i;

         zw_REG_OP <= zw_REG_OP;

         zw_b1 <= zw_b1;

         zw_b2 <= zw_b2;

         zw_b3 <= zw_b3;

         zw_b4 <= zw_b4;

         zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6)));

         d_o_cld <= sig_D_OUT;

         rd_o_cld <= sig_RD;

         sync_o_cld <= sig_SYNC;

         wr_n_o_cld <= sig_RWn;

         wr_o_cld <= sig_WR;

         -- Combined Actions

         CASE current_state IS

            WHEN FETCH =>

               zw_REG_OP <= d_i;

               IF ((nmi_i = '1') AND (rdy_i = '1')) THEN

                  sig_PC <= adr_nxt_pc_i;

                  zw_REG_NMI <= '0';

               ELSIF ((irq_n_i = '0' and

                      reg_F(2) = '0') AND (rdy_i = '1')) THEN

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"69" or

                      d_i = X"65" or

                      d_i = X"75" or

                      d_i = X"6D" or

                      d_i = X"7D" or

                      d_i = X"79" or

                      d_i = X"61" or

                      d_i = X"71") AND (rdy_i = '1')) THEN

                  sig_PC <= adr_nxt_pc_i;

                  reg_sel_reg <= "00";

                  reg_sel_rb_in <= "11";

                  zw_b1(0) <= reg_F(7);

               ELSIF ((d_i = X"06" or

                      d_i = X"16" or

                      d_i = X"0E" or

                      d_i = X"1E") AND (rdy_i = '1')) THEN

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"90" or

                      d_i = X"B0" or

                      d_i = X"F0" or

                      d_i = X"30" or

                      d_i = X"D0" or

                      d_i = X"10" or

                      d_i = X"50" or

                      d_i = X"70") AND (rdy_i = '1')) THEN

                  sig_PC <= adr_nxt_pc_i;

                  zw_b3 <= adr_nxt_pc_i (15 downto 8);

               ELSIF ((d_i = X"24" or

                      d_i = X"2C") AND (rdy_i = '1')) THEN

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN

               ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN

               ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN

               ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN

               ELSIF ((d_i = X"E0" or

                      d_i = X"E4" or

                      d_i = X"EC") AND (rdy_i = '1')) THEN

                  reg_sel_rb_out <= "01";

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"C0" or

                      d_i = X"C4" or

                      d_i = X"CC") AND (rdy_i = '1')) THEN

                  reg_sel_rb_out <= "10";

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"C6" or

                      d_i = X"D6" or

                      d_i = X"CE" or

                      d_i = X"DE") AND (rdy_i = '1')) THEN

                  zw_b4 <= X"FF";

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN

                  reg_sel_rb_out <= "01";

                  reg_sel_reg <= "01";

                  reg_sel_rb_in <= "11";

                  zw_b4 <= X"FF";

               ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN

                  reg_sel_rb_out <= "10";

                  reg_sel_reg <= "10";

                  reg_sel_rb_in <= "11";

                  zw_b4 <= X"FF";

               ELSIF ((d_i = X"49" or

                      d_i = X"45" or

                      d_i = X"55" or

                      d_i = X"4D" or

                      d_i = X"5D" or

                      d_i = X"59" or

                      d_i = X"41" or

                      d_i = X"51" or

                      d_i = X"09" or

                      d_i = X"05" or

                      d_i = X"15" or

                      d_i = X"0D" or

                      d_i = X"1D" or

                      d_i = X"19" or

                      d_i = X"01" or

                      d_i = X"11" or

                      d_i = X"29" or

                      d_i = X"25" or

                      d_i = X"35" or

                      d_i = X"2D" or

                      d_i = X"3D" or

                      d_i = X"39" or

                      d_i = X"21" or

                      d_i = X"31" or

                      d_i = X"C9" or

                      d_i = X"C5" or

                      d_i = X"D5" or

                      d_i = X"CD" or

                      d_i = X"DD" or

                      d_i = X"D9" or

                      d_i = X"C1" or

                      d_i = X"D1") AND (rdy_i = '1')) THEN

                  reg_sel_rb_out <= "00";

                  reg_sel_reg <= "00";

                  reg_sel_rb_in <= "11";

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"E6" or

                      d_i = X"F6" or

                      d_i = X"EE" or

                      d_i = X"FE") AND (rdy_i = '1')) THEN

                  zw_b4 <= X"01";

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN

                  reg_sel_rb_out <= "01";

                  reg_sel_reg <= "01";

                  reg_sel_rb_in <= "11";

                  zw_b4 <= X"01";

               ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN

                  reg_sel_rb_out <= "10";

                  reg_sel_reg <= "10";

                  reg_sel_rb_in <= "11";

                  zw_b4 <= X"01";

               ELSIF ((d_i = X"4C" or

                      d_i = X"6C") AND (rdy_i = '1')) THEN

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"A9" or

                      d_i = X"A5" or

                      d_i = X"B5" or

                      d_i = X"AD" or

                      d_i = X"BD" or

                      d_i = X"B9" or

                      d_i = X"A1" or

                      d_i = X"B1") AND (rdy_i = '1')) THEN

                  reg_sel_reg <= "00";

                  reg_sel_rb_in <= "11";

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"A2" or

                      d_i = X"A6" or

                      d_i = X"B6" or

                      d_i = X"AE" or

                      d_i = X"BE") AND (rdy_i = '1')) THEN

                  reg_sel_reg <= "01";

                  reg_sel_rb_in <= "11";

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"A0" or

                      d_i = X"A4" or

                      d_i = X"B4" or

                      d_i = X"AC" or

                      d_i = X"BC") AND (rdy_i = '1')) THEN

                  reg_sel_reg <= "10";

                  reg_sel_rb_in <= "11";

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"46" or

                      d_i = X"56" or

                      d_i = X"4E" or

                      d_i = X"5E") AND (rdy_i = '1')) THEN

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN

               ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN

                  reg_sel_sp_in <= '0';

                  reg_sel_sp_as <= '0';

                  reg_sel_reg <= "00";

                  reg_sel_rb_in <= "11";

               ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN

                  reg_sel_sp_in <= '0';

                  reg_sel_sp_as <= '0';

               ELSIF ((d_i = X"26" or

                      d_i = X"36" or

                      d_i = X"2E" or

                      d_i = X"3E") AND (rdy_i = '1')) THEN

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"66" or

                      d_i = X"76" or

                      d_i = X"6E" or

                      d_i = X"7E") AND (rdy_i = '1')) THEN

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN

                  sig_PC <= adr_nxt_pc_i;

               ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN

                  sig_PC <= adr_nxt_pc_i;

                  reg_sel_sp_in <= '0';

                  reg_sel_sp_as <= '0';

               ELSIF ((d_i = X"E9" or

                      d_i = X"E5" or

                      d_i = X"F5" or

                      d_i = X"ED" or

                      d_i = X"FD" or

                      d_i = X"F9" or

                      d_i = X"E1" or

                      d_i = X"F1") AND (rdy_i = '1')) THEN

                  sig_PC <= adr_nxt_pc_i;

                  reg_sel_reg <= "00";

                  reg_sel_rb_in <= "11";

                  zw_b1(0) <= reg_F(7);

               ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN

               ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN

               ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN

               ELSIF ((d_i = X"85" or

                      d_i = X"95" or

                      d_i = X"8D" or

                      d_i = X"9D" or

                      d_i = X"99" or

                      d_i = X"81" or

                      d_i = X"91") AND (rdy_i = '1')) THEN