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-- VHDL Entity R6502_TC.FSM_Execution_Unit.symbol

--

-- Created:

--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)

--          at - 11:47:40 23.02.2009

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

--

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

entity FSM_Execution_Unit is

   port(

      adr_nxt_pc_i : in     std_logic_vector (15 downto 0);

      adr_pc_i     : in     std_logic_vector (15 downto 0);

      adr_sp_i     : in     std_logic_vector (15 downto 0);

      clk_clk_i    : in     std_logic;

      d_alu_i      : in     std_logic_vector ( 7 downto 0 );

      d_i          : in     std_logic_vector ( 7 downto 0 );

      d_regs_out_i : in     std_logic_vector ( 7 downto 0 );

      irq_n_i      : in     std_logic;

      nmi_i        : in     std_logic;

      q_a_i        : in     std_logic_vector ( 7 downto 0 );

      q_x_i        : in     std_logic_vector ( 7 downto 0 );

      q_y_i        : in     std_logic_vector ( 7 downto 0 );

      rdy_i        : in     std_logic;

      reg_0flag_i  : in     std_logic;

      reg_1flag_i  : in     std_logic;

      reg_7flag_i  : in     std_logic;

      rst_rst_n_i  : in     std_logic;

      so_n_i       : in     std_logic;

      a_o          : out    std_logic_vector (15 downto 0);

      adr_o        : out    std_logic_vector (15 downto 0);

      ch_a_o       : out    std_logic_vector ( 7 downto 0 );

      ch_b_o       : out    std_logic_vector ( 7 downto 0 );

      d_o          : out    std_logic_vector ( 7 downto 0 );

      d_regs_in_o  : out    std_logic_vector ( 7 downto 0 );

      fetch_o      : out    std_logic;

      ld_o         : out    std_logic_vector ( 1 downto 0 );

      ld_pc_o      : out    std_logic;

      ld_sp_o      : out    std_logic;

      load_regs_o  : out    std_logic;

      offset_o     : out    std_logic_vector ( 15 downto 0 );

      rd_o         : out    std_logic;

      sel_pc_in_o  : out    std_logic;

      sel_pc_val_o : out    std_logic_vector ( 1 downto 0 );

      sel_rb_in_o  : out    std_logic_vector ( 1 downto 0 );

      sel_rb_out_o : out    std_logic_vector ( 1 downto 0 );

      sel_reg_o    : out    std_logic_vector ( 1 downto 0 );

      sel_sp_as_o  : out    std_logic;

      sel_sp_in_o  : out    std_logic;

      sync_o       : out    std_logic;

      wr_o         : out    std_logic

   );

-- Declarations

end FSM_Execution_Unit ;

-- Jens-D. Gutschmidt     Project:  R6502_TC  

-- scantara2003@yahoo.de                      

-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG                                                                                

--                                                                                                                                             

-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by   

-- the Free Software Foundation, either version 3 of the License, or any later version.                                                        

--                                                                                                                                             

-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of              

-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.                                  

--                                                                                                                                             

-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.     

--                                                                                                                                             

-- CVS Revisins History                                                                                                                        

--                                                                                                                                             

-- $Log: not supported by cvs2svn $                                                                                                                            

--   <<-- more -->>                                                                                                                            

-- Title:  FSM Execution Unit for all op codes  

-- Path:  R6502_TC/FSM_Execution_Unit/fsm  

-- Edited:  by eda on 23 Feb 2009  

--

-- VHDL Architecture R6502_TC.FSM_Execution_Unit.fsm

--

-- Created:

--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)

--          at - 11:47:41 23.02.2009

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

--

library ieee;

use ieee.std_logic_1164.ALL;

use ieee.std_logic_arith.ALL;

architecture fsm of FSM_Execution_Unit is

   -- Architecture Declarations

   signal reg_F : std_logic_vector( 7 DOWNTO 0 );

   signal reg_sel_pc_in : std_logic;

   signal reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );

   signal reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );

   signal reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );

   signal reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );

   signal reg_sel_sp_as : std_logic;

   signal reg_sel_sp_in : std_logic;

   signal sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );

   signal sig_PC : std_logic_vector(15 DOWNTO 0);

   signal sig_SYNC : std_logic;

   signal sig_WR : std_logic;

   signal zw_ALU : std_logic_vector( 8 DOWNTO 0 );

   signal zw_ALU1 : std_logic_vector( 4 DOWNTO 0 );

   signal zw_ALU2 : std_logic_vector( 4 DOWNTO 0 );

   signal zw_ALU3 : std_logic_vector( 4 DOWNTO 0 );

   signal zw_ALU4 : std_logic_vector( 4 DOWNTO 0 );

   signal zw_ALU5 : std_logic_vector( 3 DOWNTO 0 );

   signal zw_ALU6 : std_logic_vector( 3 DOWNTO 0 );

   signal zw_REG_NMI : std_logic;

   signal zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b1 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b2 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b3 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_b4 : std_logic_vector( 7 DOWNTO 0 );

   signal zw_so : std_logic;

   subtype state_type is

      std_logic_vector(7 downto 0);

   -- Hard encoding

   constant FETCH : state_type := "00000000";

   constant G10_1 : state_type := "00000001";

   constant G10_2 : state_type := "00000010";

   constant G10_3 : state_type := "00000011";

   constant G10_4 : state_type := "00000100";

   constant G10_5 : state_type := "00000101";

   constant G10_6 : state_type := "00000110";

   constant G10_7 : state_type := "00000111";

   constant G10_e1 : state_type := "00001000";

   constant G10_e2 : state_type := "00001001";

   constant G10_e3 : state_type := "00001010";

   constant G11_1 : state_type := "00001011";

   constant G11_2 : state_type := "00001100";

   constant G11_3 : state_type := "00001101";

   constant G11_4 : state_type := "00001110";

   constant G11_5 : state_type := "00001111";

   constant G11_6 : state_type := "00010000";

   constant G11_7 : state_type := "00010001";

   constant G11_e : state_type := "00010010";

   constant G12_1 : state_type := "00010011";

   constant G12_e1 : state_type := "00010100";

   constant G12_e2 : state_type := "00010101";

   constant G13_1 : state_type := "00010110";

   constant G13_2 : state_type := "00010111";

   constant G13_e : state_type := "00011000";

   constant G14_1 : state_type := "00011001";

   constant G14_2 : state_type := "00011010";

   constant G14_3 : state_type := "00011011";

   constant G14_4 : state_type := "00011100";

   constant G14_5 : state_type := "00011101";

   constant G14_6 : state_type := "00011110";

   constant G14_7 : state_type := "00011111";

   constant G14_e : state_type := "00100000";

   constant G15_1 : state_type := "00100001";

   constant G15_2 : state_type := "00100010";

   constant G15_3 : state_type := "00100011";

   constant G15_4 : state_type := "00100100";

   constant G15_5 : state_type := "00100101";

   constant G15_6 : state_type := "00100110";

   constant G15_7 : state_type := "00100111";

   constant G15_e1 : state_type := "00101000";

   constant G15_e2 : state_type := "00101001";

   constant G15_e3 : state_type := "00101010";

   constant G16_1 : state_type := "00101011";

   constant G16_2 : state_type := "00101100";

   constant G16_3 : state_type := "00101101";

   constant G16_4 : state_type := "00101110";

   constant G16_5 : state_type := "00101111";

   constant G16_6 : state_type := "00110000";

   constant G16_7 : state_type := "00110001";

   constant G16_e1 : state_type := "00110010";

   constant G16_e2 : state_type := "00110011";

   constant G16_e3 : state_type := "00110100";

   constant G17_1 : state_type := "00110101";

   constant G17_10 : state_type := "00110110";

   constant G17_2 : state_type := "00110111";

   constant G17_3 : state_type := "00111000";

   constant G17_4 : state_type := "00111001";

   constant G17_5 : state_type := "00111010";

   constant G17_6 : state_type := "00111011";

   constant G17_7 : state_type := "00111100";

   constant G17_8 : state_type := "00111101";

   constant G17_9 : state_type := "00111110";

   constant G17_e : state_type := "00111111";

   constant G18_1 : state_type := "01000000";

   constant G18_2 : state_type := "01000001";

   constant G18_3 : state_type := "01000010";

   constant G18_4 : state_type := "01000011";

   constant G18_5 : state_type := "01000100";

   constant G18_e : state_type := "01000101";

   constant G19_1 : state_type := "01000110";

   constant G1_1 : state_type := "01000111";

   constant G20_1 : state_type := "01001000";

   constant G20_2 : state_type := "01001001";

   constant G20_3 : state_type := "01001010";

   constant G20_e : state_type := "01001011";

   constant G21_1 : state_type := "01001100";

   constant G21_2 : state_type := "01001101";

   constant G21_3 : state_type := "01001110";

   constant G21_4 : state_type := "01001111";

   constant G21_e : state_type := "01010000";

   constant G22_1 : state_type := "01010001";

   constant G22_e : state_type := "01010010";

   constant G23_1 : state_type := "01010011";

   constant G23_e : state_type := "01010100";

   constant G24_1 : state_type := "01010101";

   constant G24_2 : state_type := "01010110";

   constant G24_e : state_type := "01010111";

   constant G25_1 : state_type := "01011000";

   constant G25_2 : state_type := "01011001";

   constant G25_e : state_type := "01011010";

   constant G26_1 : state_type := "01011011";

   constant G26_2 : state_type := "01011100";

   constant G26_3 : state_type := "01011101";

   constant G26_4 : state_type := "01011110";

   constant G26_e : state_type := "01011111";

   constant G27_1 : state_type := "01100000";

   constant G27_2 : state_type := "01100001";

   constant G27_3 : state_type := "01100010";

   constant G27_4 : state_type := "01100011";

   constant G27_e : state_type := "01100100";

   constant G28_1 : state_type := "01100101";

   constant G28_2 : state_type := "01100110";

   constant G28_3 : state_type := "01100111";

   constant G28_4 : state_type := "01101000";

   constant G28_5 : state_type := "01101001";

   constant G28_e : state_type := "01101010";

   constant G29_1 : state_type := "01101011";

   constant G29_2 : state_type := "01101100";

   constant G29_3 : state_type := "01101101";

   constant G29_4 : state_type := "01101110";

   constant G29_5 : state_type := "01101111";

   constant G29_e : state_type := "01110000";

   constant G2_1 : state_type := "01110001";

   constant G30_1 : state_type := "01110010";

   constant G30_2 : state_type := "01110011";

   constant G30_3 : state_type := "01110100";

   constant G30_4 : state_type := "01110101";

   constant G30_5 : state_type := "01110110";

   constant G30_e : state_type := "01110111";

   constant G31_1 : state_type := "01111000";

   constant G32_1 : state_type := "01111001";

   constant G33_1 : state_type := "01111010";

   constant G34_1 : state_type := "01111011";

   constant G3_1 : state_type := "01111100";

   constant G4_1 : state_type := "01111101";

   constant G5_1 : state_type := "01111110";

   constant G6_1 : state_type := "01111111";

   constant G7_1 : state_type := "10000000";

   constant G8_1 : state_type := "10000001";

   constant G9_1 : state_type := "10000010";

   constant RES : state_type := "10000011";

   -- Declare current and next state signals

   signal current_state : state_type;

   signal next_state : state_type;

   -- Declare any pre-registered internal signals

   signal d_o_cld : std_logic_vector ( 7 downto 0 );

   signal rd_o_cld : std_logic ;

   signal sync_o_cld : std_logic ;

   signal wr_o_cld : std_logic ;

begin

   -----------------------------------------------------------------

   clocked_proc : process (

      clk_clk_i,

      rst_rst_n_i

   )

   -----------------------------------------------------------------

   begin

      if (rst_rst_n_i = '0') then

         current_state <= RES;

         -- Default Reset Values

         d_o_cld <= X"00";

         rd_o_cld <= '0';

         sync_o_cld <= '0';

         wr_o_cld <= '0';

         reg_F <= "00000100";

         reg_sel_pc_in <= '0';

         reg_sel_pc_val <= "00";

         reg_sel_rb_in <= "00";

         reg_sel_rb_out <= "00";

         reg_sel_reg <= "00";

         reg_sel_sp_as <= '0';

         reg_sel_sp_in <= '0';

         sig_PC <= X"0000";

         zw_REG_NMI <= '0';

         zw_REG_OP <= X"00";

         zw_b1 <= X"00";

         zw_b2 <= X"00";

         zw_b3 <= X"00";

         zw_b4 <= X"00";

         zw_so <= '0';

      elsif (clk_clk_i'event and clk_clk_i = '1') then

         current_state <= next_state;

         -- Default Assignment To Internals

         reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0);

         reg_sel_pc_in <= reg_sel_pc_in;

         reg_sel_pc_val <= reg_sel_pc_val;

         reg_sel_rb_in <= reg_sel_rb_in;

         reg_sel_rb_out <= reg_sel_rb_out;

         reg_sel_reg <= reg_sel_reg;

         reg_sel_sp_as <= reg_sel_sp_as;

         reg_sel_sp_in <= reg_sel_sp_in;

         sig_PC <= sig_PC;

         zw_REG_NMI <= zw_REG_NMI or nmi_i;

         zw_REG_OP <= zw_REG_OP;

         zw_b1 <= zw_b1;

         zw_b2 <= zw_b2;

         zw_b3 <= zw_b3;

         zw_b4 <= zw_b4;

         zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6)));

         d_o_cld <= sig_D_OUT;

         rd_o_cld <= NOT(sig_WR);

         sync_o_cld <= sig_SYNC;

         wr_o_cld <= sig_WR;

         -- Combined Actions

         case current_state is

            when FETCH =>

               zw_REG_OP <= d_i;

               if ((nmi_i = '1') and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

                  zw_REG_NMI <= '0';

               elsif ((irq_n_i = '0' and

                      reg_F(2) = '0') and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"69" or

                      d_i = X"65" or

                      d_i = X"75" or

                      d_i = X"6D" or

                      d_i = X"7D" or

                      d_i = X"79" or

                      d_i = X"61" or

                      d_i = X"71") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

                  reg_sel_reg <= "00";

                  reg_sel_rb_in <= "11";

                  zw_b1(0) <= reg_F(7);

               elsif ((d_i = X"06" or

                      d_i = X"16" or

                      d_i = X"0E" or

                      d_i = X"1E") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"90" or

                      d_i = X"B0" or

                      d_i = X"F0" or

                      d_i = X"30" or

                      d_i = X"D0" or

                      d_i = X"10" or

                      d_i = X"50" or

                      d_i = X"70") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

                  zw_b3 <= adr_nxt_pc_i (15 downto 8);

               elsif ((d_i = X"24" or

                      d_i = X"2C") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"00") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"18") and (rdy_i = '1')) then

               elsif ((d_i = X"D8") and (rdy_i = '1')) then

               elsif ((d_i = X"58") and (rdy_i = '1')) then

               elsif ((d_i = X"B8") and (rdy_i = '1')) then

               elsif ((d_i = X"E0" or

                      d_i = X"E4" or

                      d_i = X"EC") and (rdy_i = '1')) then

                  reg_sel_rb_out <= "01";

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"C0" or

                      d_i = X"C4" or

                      d_i = X"CC") and (rdy_i = '1')) then

                  reg_sel_rb_out <= "10";

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"C6" or

                      d_i = X"D6" or

                      d_i = X"CE" or

                      d_i = X"DE") and (rdy_i = '1')) then

                  zw_b4 <= X"FF";

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"CA") and (rdy_i = '1')) then

                  reg_sel_rb_out <= "01";

                  reg_sel_reg <= "01";

                  reg_sel_rb_in <= "11";

                  zw_b4 <= X"FF";

               elsif ((d_i = X"88") and (rdy_i = '1')) then

                  reg_sel_rb_out <= "10";

                  reg_sel_reg <= "10";

                  reg_sel_rb_in <= "11";

                  zw_b4 <= X"FF";

               elsif ((d_i = X"49" or

                      d_i = X"45" or

                      d_i = X"55" or

                      d_i = X"4D" or

                      d_i = X"5D" or

                      d_i = X"59" or

                      d_i = X"41" or

                      d_i = X"51" or

                      d_i = X"09" or

                      d_i = X"05" or

                      d_i = X"15" or

                      d_i = X"0D" or

                      d_i = X"1D" or

                      d_i = X"19" or

                      d_i = X"01" or

                      d_i = X"11" or

                      d_i = X"29" or

                      d_i = X"25" or

                      d_i = X"35" or

                      d_i = X"2D" or

                      d_i = X"3D" or

                      d_i = X"39" or

                      d_i = X"21" or

                      d_i = X"31" or

                      d_i = X"C9" or

                      d_i = X"C5" or

                      d_i = X"D5" or

                      d_i = X"CD" or

                      d_i = X"DD" or

                      d_i = X"D9" or

                      d_i = X"C1" or

                      d_i = X"D1") and (rdy_i = '1')) then

                  reg_sel_rb_out <= "00";

                  reg_sel_reg <= "00";

                  reg_sel_rb_in <= "11";

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"E6" or

                      d_i = X"F6" or

                      d_i = X"EE" or

                      d_i = X"FE") and (rdy_i = '1')) then

                  zw_b4 <= X"01";

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"E8") and (rdy_i = '1')) then

                  reg_sel_rb_out <= "01";

                  reg_sel_reg <= "01";

                  reg_sel_rb_in <= "11";

                  zw_b4 <= X"01";

               elsif ((d_i = X"C8") and (rdy_i = '1')) then

                  reg_sel_rb_out <= "10";

                  reg_sel_reg <= "10";

                  reg_sel_rb_in <= "11";

                  zw_b4 <= X"01";

               elsif ((d_i = X"4C" or

                      d_i = X"6C") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"20") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"A9" or

                      d_i = X"A5" or

                      d_i = X"B5" or

                      d_i = X"AD" or

                      d_i = X"BD" or

                      d_i = X"B9" or

                      d_i = X"A1" or

                      d_i = X"B1") and (rdy_i = '1')) then

                  reg_sel_reg <= "00";

                  reg_sel_rb_in <= "11";

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"A2" or

                      d_i = X"A6" or

                      d_i = X"B6" or

                      d_i = X"AE" or

                      d_i = X"BE") and (rdy_i = '1')) then

                  reg_sel_reg <= "01";

                  reg_sel_rb_in <= "11";

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"A0" or

                      d_i = X"A4" or

                      d_i = X"B4" or

                      d_i = X"AC" or

                      d_i = X"BC") and (rdy_i = '1')) then

                  reg_sel_reg <= "10";

                  reg_sel_rb_in <= "11";

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"46" or

                      d_i = X"56" or

                      d_i = X"4E" or

                      d_i = X"5E") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"EA") and (rdy_i = '1')) then

               elsif ((d_i = X"48") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"08") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"68") and (rdy_i = '1')) then

                  reg_sel_sp_in <= '0';

                  reg_sel_sp_as <= '0';

                  reg_sel_reg <= "00";

                  reg_sel_rb_in <= "11";

               elsif ((d_i = X"28") and (rdy_i = '1')) then

                  reg_sel_sp_in <= '0';

                  reg_sel_sp_as <= '0';

               elsif ((d_i = X"26" or

                      d_i = X"36" or

                      d_i = X"2E" or

                      d_i = X"3E") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"66" or

                      d_i = X"76" or

                      d_i = X"6E" or

                      d_i = X"7E") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"40") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

                  reg_sel_sp_in <= '0';

                  reg_sel_sp_as <= '0';

               elsif ((d_i = X"60") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

                  reg_sel_sp_in <= '0';

                  reg_sel_sp_as <= '0';

               elsif ((d_i = X"E9" or

                      d_i = X"E5" or

                      d_i = X"F5" or

                      d_i = X"ED" or

                      d_i = X"FD" or

                      d_i = X"F9" or

                      d_i = X"E1" or

                      d_i = X"F1") and (rdy_i = '1')) then

                  sig_PC <= adr_nxt_pc_i;

                  reg_sel_reg <= "00";

                  reg_sel_rb_in <= "11";

                  zw_b1(0) <= reg_F(7);

               elsif ((d_i = X"38") and (rdy_i = '1')) then

               elsif ((d_i = X"F8") and (rdy_i = '1')) then

               elsif ((d_i = X"78") and (rdy_i = '1')) then

               elsif ((d_i = X"85" or

                      d_i = X"95" or

                      d_i = X"8D" or

                      d_i = X"9D" or

                      d_i = X"99" or

                      d_i = X"81" or

                      d_i = X"91") and (rdy_i = '1')) then

                  reg_sel_rb_out <= "00";

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"86" or

                      d_i = X"96" or

                      d_i = X"8E") and (rdy_i = '1')) then

                  reg_sel_rb_out <= "01";

                  sig_PC <= adr_nxt_pc_i;

               elsif ((d_i = X"84" or

                      d_i = X"94" or