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[/] [cpu6502_true_cycle/] [trunk/] [rtl/] [vhdl/] [fsm_execution_unit.vhd] - Blame information for rev 24

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1 24 fpga_is_fu
-- VHDL Entity R6502_TC.FSM_Execution_Unit.symbol
2
--
3
-- Created:
4
--          by - eda.UNKNOWN (ENTW1)
5
--          at - 15:57:20 20.02.2010
6
--
7
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
8
--
9
LIBRARY ieee;
10
USE ieee.std_logic_1164.all;
11
USE ieee.std_logic_arith.all;
12
 
13
ENTITY FSM_Execution_Unit IS
14
   PORT(
15
      adr_nxt_pc_i : IN     std_logic_vector (15 DOWNTO 0);
16
      adr_pc_i     : IN     std_logic_vector (15 DOWNTO 0);
17
      adr_sp_i     : IN     std_logic_vector (15 DOWNTO 0);
18
      clk_clk_i    : IN     std_logic;
19
      d_alu_i      : IN     std_logic_vector ( 7 DOWNTO 0 );
20
      d_i          : IN     std_logic_vector ( 7 DOWNTO 0 );
21
      d_regs_out_i : IN     std_logic_vector ( 7 DOWNTO 0 );
22
      irq_n_i      : IN     std_logic;
23
      nmi_i        : IN     std_logic;
24
      q_a_i        : IN     std_logic_vector ( 7 DOWNTO 0 );
25
      q_x_i        : IN     std_logic_vector ( 7 DOWNTO 0 );
26
      q_y_i        : IN     std_logic_vector ( 7 DOWNTO 0 );
27
      rdy_i        : IN     std_logic;
28
      reg_0flag_i  : IN     std_logic;
29
      reg_1flag_i  : IN     std_logic;
30
      reg_7flag_i  : IN     std_logic;
31
      rst_rst_n_i  : IN     std_logic;
32
      so_n_i       : IN     std_logic;
33
      a_o          : OUT    std_logic_vector (15 DOWNTO 0);
34
      adr_o        : OUT    std_logic_vector (15 DOWNTO 0);
35
      ch_a_o       : OUT    std_logic_vector ( 7 DOWNTO 0 );
36
      ch_b_o       : OUT    std_logic_vector ( 7 DOWNTO 0 );
37
      d_o          : OUT    std_logic_vector ( 7 DOWNTO 0 );
38
      d_regs_in_o  : OUT    std_logic_vector ( 7 DOWNTO 0 );
39
      ld_o         : OUT    std_logic_vector ( 1 DOWNTO 0 );
40
      ld_pc_o      : OUT    std_logic;
41
      ld_sp_o      : OUT    std_logic;
42
      load_regs_o  : OUT    std_logic;
43
      offset_o     : OUT    std_logic_vector ( 15 DOWNTO 0 );
44
      rd_o         : OUT    std_logic;
45
      rst_nmi_o    : OUT    std_logic;
46
      sel_pc_in_o  : OUT    std_logic;
47
      sel_pc_val_o : OUT    std_logic_vector ( 1 DOWNTO 0 );
48
      sel_rb_in_o  : OUT    std_logic_vector ( 1 DOWNTO 0 );
49
      sel_rb_out_o : OUT    std_logic_vector ( 1 DOWNTO 0 );
50
      sel_reg_o    : OUT    std_logic_vector ( 1 DOWNTO 0 );
51
      sel_sp_as_o  : OUT    std_logic;
52
      sel_sp_in_o  : OUT    std_logic;
53
      sync_o       : OUT    std_logic;
54
      wr_n_o       : OUT    std_logic;
55
      wr_o         : OUT    std_logic
56
   );
57
 
58
-- Declarations
59
 
60
END FSM_Execution_Unit ;
61
 
62
-- Jens-D. Gutschmidt     Project:  R6502_TC  
63
 
64
-- scantara2003@yahoo.de                      
65
 
66
-- COPYRIGHT (C) 2008-2010 by Jens Gutschmidt and OPENCORES.ORG                                                                                
67
 
68
--                                                                                                                                             
69
 
70
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by   
71
 
72
-- the Free Software Foundation, either version 3 of the License, or any later version.                                                        
73
 
74
--                                                                                                                                             
75
 
76
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of              
77
 
78
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.                                  
79
 
80
--                                                                                                                                             
81
 
82
-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.     
83
 
84
--                                                                                                                                             
85
 
86
-- CVS Revisins History                                                                                                                        
87
 
88
--                                                                                                                                             
89
 
90
-- $Log: fsm.sm,v $                                                                                                                            
91
 
92
--   <<-- more -->>                                                                                                                            
93
 
94
-- Title:  FSM Execution Unit for all op codes  
95
 
96
-- Path:  R6502_TC/FSM_Execution_Unit/fsm  
97
 
98
-- Edited:  by eda on 20 Feb 2010  
99
 
100
--
101
-- VHDL Architecture R6502_TC.FSM_Execution_Unit.fsm
102
--
103
-- Created:
104
--          by - eda.UNKNOWN (ENTW1)
105
--          at - 15:57:21 20.02.2010
106
--
107
-- Generated by Mentor Graphics' HDL Designer(TM) 2009.1 (Build 12)
108
--
109
LIBRARY ieee;
110
USE ieee.std_logic_1164.all;
111
USE ieee.std_logic_arith.all;
112
 
113
ARCHITECTURE fsm OF FSM_Execution_Unit IS
114
 
115
   -- Architecture Declarations
116
   SIGNAL reg_F : std_logic_vector( 7 DOWNTO 0 );
117
   SIGNAL reg_sel_pc_in : std_logic;
118
   SIGNAL reg_sel_pc_val : std_logic_vector( 1 DOWNTO 0 );
119
   SIGNAL reg_sel_rb_in : std_logic_vector( 1 DOWNTO 0 );
120
   SIGNAL reg_sel_rb_out : std_logic_vector( 1 DOWNTO 0 );
121
   SIGNAL reg_sel_reg : std_logic_vector( 1 DOWNTO 0 );
122
   SIGNAL reg_sel_sp_as : std_logic;
123
   SIGNAL reg_sel_sp_in : std_logic;
124
   SIGNAL sig_D_OUT : std_logic_vector( 7 DOWNTO 0 );
125
   SIGNAL sig_PC : std_logic_vector(15 DOWNTO 0);
126
   SIGNAL sig_RD : std_logic;
127
   SIGNAL sig_RWn : std_logic;
128
   SIGNAL sig_SYNC : std_logic;
129
   SIGNAL sig_WR : std_logic;
130
   SIGNAL zw_ALU : std_logic_vector( 8 DOWNTO 0 );
131
   SIGNAL zw_ALU1 : std_logic_vector( 4 DOWNTO 0 );
132
   SIGNAL zw_ALU2 : std_logic_vector( 4 DOWNTO 0 );
133
   SIGNAL zw_ALU3 : std_logic_vector( 4 DOWNTO 0 );
134
   SIGNAL zw_ALU4 : std_logic_vector( 4 DOWNTO 0 );
135
   SIGNAL zw_ALU5 : std_logic_vector( 3 DOWNTO 0 );
136
   SIGNAL zw_ALU6 : std_logic_vector( 3 DOWNTO 0 );
137
   SIGNAL zw_REG_OP : std_logic_vector( 7 DOWNTO 0 );
138
   SIGNAL zw_b1 : std_logic_vector( 7 DOWNTO 0 );
139
   SIGNAL zw_b2 : std_logic_vector( 7 DOWNTO 0 );
140
   SIGNAL zw_b3 : std_logic_vector( 7 DOWNTO 0 );
141
   SIGNAL zw_b4 : std_logic_vector( 7 DOWNTO 0 );
142
   SIGNAL zw_so : std_logic;
143
 
144
   SUBTYPE STATE_TYPE IS
145
      std_logic_vector(7 DOWNTO 0);
146
 
147
   -- Hard encoding
148
   CONSTANT FETCH : STATE_TYPE := "00000000";
149
   CONSTANT s1 : STATE_TYPE := "00000001";
150
   CONSTANT s2 : STATE_TYPE := "00000011";
151
   CONSTANT s5 : STATE_TYPE := "00000010";
152
   CONSTANT s3 : STATE_TYPE := "00000110";
153
   CONSTANT s4 : STATE_TYPE := "00000111";
154
   CONSTANT s12 : STATE_TYPE := "00000101";
155
   CONSTANT s16 : STATE_TYPE := "00000100";
156
   CONSTANT s17 : STATE_TYPE := "00001100";
157
   CONSTANT s24 : STATE_TYPE := "00001101";
158
   CONSTANT s25 : STATE_TYPE := "00001111";
159
   CONSTANT s271 : STATE_TYPE := "00001110";
160
   CONSTANT s273 : STATE_TYPE := "00001010";
161
   CONSTANT s304 : STATE_TYPE := "00001011";
162
   CONSTANT s307 : STATE_TYPE := "00001001";
163
   CONSTANT s177 : STATE_TYPE := "00001000";
164
   CONSTANT s180 : STATE_TYPE := "00011000";
165
   CONSTANT s181 : STATE_TYPE := "00011001";
166
   CONSTANT s182 : STATE_TYPE := "00011011";
167
   CONSTANT s183 : STATE_TYPE := "00011010";
168
   CONSTANT s184 : STATE_TYPE := "00011110";
169
   CONSTANT s185 : STATE_TYPE := "00011111";
170
   CONSTANT s186 : STATE_TYPE := "00011101";
171
   CONSTANT s187 : STATE_TYPE := "00011100";
172
   CONSTANT s188 : STATE_TYPE := "00010100";
173
   CONSTANT s189 : STATE_TYPE := "00010101";
174
   CONSTANT s190 : STATE_TYPE := "00010111";
175
   CONSTANT s191 : STATE_TYPE := "00010110";
176
   CONSTANT s192 : STATE_TYPE := "00010010";
177
   CONSTANT s193 : STATE_TYPE := "00010011";
178
   CONSTANT s377 : STATE_TYPE := "00010001";
179
   CONSTANT s381 : STATE_TYPE := "00010000";
180
   CONSTANT s378 : STATE_TYPE := "00110000";
181
   CONSTANT s382 : STATE_TYPE := "00110001";
182
   CONSTANT s379 : STATE_TYPE := "00110011";
183
   CONSTANT s383 : STATE_TYPE := "00110010";
184
   CONSTANT s384 : STATE_TYPE := "00110110";
185
   CONSTANT s380 : STATE_TYPE := "00110111";
186
   CONSTANT s385 : STATE_TYPE := "00110101";
187
   CONSTANT s386 : STATE_TYPE := "00110100";
188
   CONSTANT s387 : STATE_TYPE := "00111100";
189
   CONSTANT s388 : STATE_TYPE := "00111101";
190
   CONSTANT s389 : STATE_TYPE := "00111111";
191
   CONSTANT s391 : STATE_TYPE := "00111110";
192
   CONSTANT s392 : STATE_TYPE := "00111010";
193
   CONSTANT s390 : STATE_TYPE := "00111011";
194
   CONSTANT s393 : STATE_TYPE := "00111001";
195
   CONSTANT s394 : STATE_TYPE := "00111000";
196
   CONSTANT s395 : STATE_TYPE := "00101000";
197
   CONSTANT s396 : STATE_TYPE := "00101001";
198
   CONSTANT s397 : STATE_TYPE := "00101011";
199
   CONSTANT s398 : STATE_TYPE := "00101010";
200
   CONSTANT s399 : STATE_TYPE := "00101110";
201
   CONSTANT s400 : STATE_TYPE := "00101111";
202
   CONSTANT s401 : STATE_TYPE := "00101101";
203
   CONSTANT s526 : STATE_TYPE := "00101100";
204
   CONSTANT s527 : STATE_TYPE := "00100100";
205
   CONSTANT s528 : STATE_TYPE := "00100101";
206
   CONSTANT s529 : STATE_TYPE := "00100111";
207
   CONSTANT s530 : STATE_TYPE := "00100110";
208
   CONSTANT s531 : STATE_TYPE := "00100010";
209
   CONSTANT s544 : STATE_TYPE := "00100011";
210
   CONSTANT s545 : STATE_TYPE := "00100001";
211
   CONSTANT s546 : STATE_TYPE := "00100000";
212
   CONSTANT s547 : STATE_TYPE := "01100000";
213
   CONSTANT s549 : STATE_TYPE := "01100001";
214
   CONSTANT s550 : STATE_TYPE := "01100011";
215
   CONSTANT s404 : STATE_TYPE := "01100010";
216
   CONSTANT s556 : STATE_TYPE := "01100110";
217
   CONSTANT s557 : STATE_TYPE := "01100111";
218
   CONSTANT s579 : STATE_TYPE := "01100101";
219
   CONSTANT s201 : STATE_TYPE := "01100100";
220
   CONSTANT s202 : STATE_TYPE := "01101100";
221
   CONSTANT s210 : STATE_TYPE := "01101101";
222
   CONSTANT s211 : STATE_TYPE := "01101111";
223
   CONSTANT s215 : STATE_TYPE := "01101110";
224
   CONSTANT s217 : STATE_TYPE := "01101010";
225
   CONSTANT s218 : STATE_TYPE := "01101011";
226
   CONSTANT s222 : STATE_TYPE := "01101001";
227
   CONSTANT s223 : STATE_TYPE := "01101000";
228
   CONSTANT s224 : STATE_TYPE := "01111000";
229
   CONSTANT s225 : STATE_TYPE := "01111001";
230
   CONSTANT s226 : STATE_TYPE := "01111011";
231
   CONSTANT s243 : STATE_TYPE := "01111010";
232
   CONSTANT s244 : STATE_TYPE := "01111110";
233
   CONSTANT s247 : STATE_TYPE := "01111111";
234
   CONSTANT s344 : STATE_TYPE := "01111101";
235
   CONSTANT s343 : STATE_TYPE := "01111100";
236
   CONSTANT s250 : STATE_TYPE := "01110100";
237
   CONSTANT s251 : STATE_TYPE := "01110101";
238
   CONSTANT s351 : STATE_TYPE := "01110111";
239
   CONSTANT s361 : STATE_TYPE := "01110110";
240
   CONSTANT s360 : STATE_TYPE := "01110010";
241
   CONSTANT s403 : STATE_TYPE := "01110011";
242
   CONSTANT s406 : STATE_TYPE := "01110001";
243
   CONSTANT s407 : STATE_TYPE := "01110000";
244
   CONSTANT s409 : STATE_TYPE := "01010000";
245
   CONSTANT s412 : STATE_TYPE := "01010001";
246
   CONSTANT s413 : STATE_TYPE := "01010011";
247
   CONSTANT s416 : STATE_TYPE := "01010010";
248
   CONSTANT s418 : STATE_TYPE := "01010110";
249
   CONSTANT s510 : STATE_TYPE := "01010111";
250
   CONSTANT s553 : STATE_TYPE := "01010101";
251
   CONSTANT s555 : STATE_TYPE := "01010100";
252
   CONSTANT s558 : STATE_TYPE := "01011100";
253
   CONSTANT s560 : STATE_TYPE := "01011101";
254
   CONSTANT s561 : STATE_TYPE := "01011111";
255
   CONSTANT s563 : STATE_TYPE := "01011110";
256
   CONSTANT s564 : STATE_TYPE := "01011010";
257
   CONSTANT s565 : STATE_TYPE := "01011011";
258
   CONSTANT s566 : STATE_TYPE := "01011001";
259
   CONSTANT s266 : STATE_TYPE := "01011000";
260
   CONSTANT s301 : STATE_TYPE := "01001000";
261
   CONSTANT s302 : STATE_TYPE := "01001001";
262
   CONSTANT RES : STATE_TYPE := "01001011";
263
   CONSTANT s511 : STATE_TYPE := "01001010";
264
   CONSTANT s559 : STATE_TYPE := "01001110";
265
   CONSTANT s562 : STATE_TYPE := "01001111";
266
   CONSTANT s567 : STATE_TYPE := "01001101";
267
   CONSTANT s568 : STATE_TYPE := "01001100";
268
   CONSTANT s569 : STATE_TYPE := "01000100";
269
   CONSTANT s570 : STATE_TYPE := "01000101";
270
   CONSTANT s571 : STATE_TYPE := "01000111";
271
   CONSTANT s572 : STATE_TYPE := "01000110";
272
   CONSTANT s573 : STATE_TYPE := "01000010";
273
   CONSTANT s574 : STATE_TYPE := "01000011";
274
   CONSTANT s548 : STATE_TYPE := "01000001";
275
   CONSTANT s551 : STATE_TYPE := "01000000";
276
   CONSTANT s552 : STATE_TYPE := "11000000";
277
   CONSTANT s575 : STATE_TYPE := "11000001";
278
   CONSTANT s576 : STATE_TYPE := "11000011";
279
   CONSTANT s577 : STATE_TYPE := "11000010";
280
   CONSTANT s578 : STATE_TYPE := "11000110";
281
 
282
   -- Declare current and next state signals
283
   SIGNAL current_state : STATE_TYPE;
284
   SIGNAL next_state : STATE_TYPE;
285
 
286
   -- Declare any pre-registered internal signals
287
   SIGNAL d_o_cld : std_logic_vector ( 7 DOWNTO 0 );
288
   SIGNAL rd_o_cld : std_logic ;
289
   SIGNAL sync_o_cld : std_logic ;
290
   SIGNAL wr_n_o_cld : std_logic ;
291
   SIGNAL wr_o_cld : std_logic ;
292
 
293
BEGIN
294
 
295
   -----------------------------------------------------------------
296
   clocked_proc : PROCESS (
297
      clk_clk_i,
298
      rst_rst_n_i
299
   )
300
   -----------------------------------------------------------------
301
   BEGIN
302
      IF (rst_rst_n_i = '0') THEN
303
         current_state <= RES;
304
         -- Default Reset Values
305
         d_o_cld <= X"00";
306
         rd_o_cld <= '0';
307
         sync_o_cld <= '0';
308
         wr_n_o_cld <= '1';
309
         wr_o_cld <= '0';
310
         reg_F <= "00000100";
311
         reg_sel_pc_in <= '0';
312
         reg_sel_pc_val <= "00";
313
         reg_sel_rb_in <= "00";
314
         reg_sel_rb_out <= "00";
315
         reg_sel_reg <= "00";
316
         reg_sel_sp_as <= '0';
317
         reg_sel_sp_in <= '0';
318
         sig_PC <= X"0000";
319
         zw_REG_OP <= X"00";
320
         zw_b1 <= X"00";
321
         zw_b2 <= X"00";
322
         zw_b3 <= X"00";
323
         zw_b4 <= X"00";
324
         zw_so <= '0';
325
      ELSIF (clk_clk_i'EVENT AND clk_clk_i = '1') THEN
326
         current_state <= next_state;
327
         -- Default Assignment To Internals
328
         reg_F <= reg_F(7) & (zw_so OR reg_F(6)) & reg_F(5 downto 0);
329
         reg_sel_pc_in <= reg_sel_pc_in;
330
         reg_sel_pc_val <= reg_sel_pc_val;
331
         reg_sel_rb_in <= reg_sel_rb_in;
332
         reg_sel_rb_out <= reg_sel_rb_out;
333
         reg_sel_reg <= reg_sel_reg;
334
         reg_sel_sp_as <= reg_sel_sp_as;
335
         reg_sel_sp_in <= reg_sel_sp_in;
336
         sig_PC <= sig_PC;
337
         zw_REG_OP <= zw_REG_OP;
338
         zw_b1 <= zw_b1;
339
         zw_b2 <= zw_b2;
340
         zw_b3 <= zw_b3;
341
         zw_b4 <= zw_b4;
342
         zw_so <= (zw_so OR (NOT(so_n_i))) AND (NOT(reg_F(6)));
343
         d_o_cld <= sig_D_OUT;
344
         rd_o_cld <= sig_RD;
345
         sync_o_cld <= sig_SYNC;
346
         wr_n_o_cld <= sig_RWn;
347
         wr_o_cld <= sig_WR;
348
 
349
         -- Combined Actions
350
         CASE current_state IS
351
            WHEN FETCH =>
352
               zw_REG_OP <= d_i;
353
               IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
354
                  sig_PC <= adr_sp_i;
355
               ELSIF ((irq_n_i = '0' and
356
                      reg_F(2) = '0') AND (rdy_i = '1')) THEN
357
                  sig_PC <= adr_sp_i;
358
               ELSIF ((d_i = X"69" or
359
                      d_i = X"65" or
360
                      d_i = X"75" or
361
                      d_i = X"6D" or
362
                      d_i = X"7D" or
363
                      d_i = X"79" or
364
                      d_i = X"61" or
365
                      d_i = X"71") AND (rdy_i = '1')) THEN
366
                  sig_PC <= adr_nxt_pc_i;
367
                  reg_sel_reg <= "00";
368
                  reg_sel_rb_in <= "11";
369
                  zw_b1(0) <= reg_F(7);
370
               ELSIF ((d_i = X"06" or
371
                      d_i = X"16" or
372
                      d_i = X"0E" or
373
                      d_i = X"1E") AND (rdy_i = '1')) THEN
374
                  sig_PC <= adr_nxt_pc_i;
375
               ELSIF ((d_i = X"90" or
376
                      d_i = X"B0" or
377
                      d_i = X"F0" or
378
                      d_i = X"30" or
379
                      d_i = X"D0" or
380
                      d_i = X"10" or
381
                      d_i = X"50" or
382
                      d_i = X"70") AND (rdy_i = '1')) THEN
383
                  sig_PC <= adr_nxt_pc_i;
384
                  zw_b3 <= adr_nxt_pc_i (15 downto 8);
385
               ELSIF ((d_i = X"24" or
386
                      d_i = X"2C") AND (rdy_i = '1')) THEN
387
                  sig_PC <= adr_nxt_pc_i;
388
               ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
389
                  sig_PC <= adr_nxt_pc_i;
390
               ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
391
               ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
392
               ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
393
               ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
394
               ELSIF ((d_i = X"E0" or
395
                      d_i = X"E4" or
396
                      d_i = X"EC") AND (rdy_i = '1')) THEN
397
                  reg_sel_rb_out <= "01";
398
                  sig_PC <= adr_nxt_pc_i;
399
               ELSIF ((d_i = X"C0" or
400
                      d_i = X"C4" or
401
                      d_i = X"CC") AND (rdy_i = '1')) THEN
402
                  reg_sel_rb_out <= "10";
403
                  sig_PC <= adr_nxt_pc_i;
404
               ELSIF ((d_i = X"C6" or
405
                      d_i = X"D6" or
406
                      d_i = X"CE" or
407
                      d_i = X"DE") AND (rdy_i = '1')) THEN
408
                  zw_b4 <= X"FF";
409
                  sig_PC <= adr_nxt_pc_i;
410
               ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
411
                  reg_sel_rb_out <= "01";
412
                  reg_sel_reg <= "01";
413
                  reg_sel_rb_in <= "11";
414
                  zw_b4 <= X"FF";
415
               ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
416
                  reg_sel_rb_out <= "10";
417
                  reg_sel_reg <= "10";
418
                  reg_sel_rb_in <= "11";
419
                  zw_b4 <= X"FF";
420
               ELSIF ((d_i = X"49" or
421
                      d_i = X"45" or
422
                      d_i = X"55" or
423
                      d_i = X"4D" or
424
                      d_i = X"5D" or
425
                      d_i = X"59" or
426
                      d_i = X"41" or
427
                      d_i = X"51" or
428
                      d_i = X"09" or
429
                      d_i = X"05" or
430
                      d_i = X"15" or
431
                      d_i = X"0D" or
432
                      d_i = X"1D" or
433
                      d_i = X"19" or
434
                      d_i = X"01" or
435
                      d_i = X"11" or
436
                      d_i = X"29" or
437
                      d_i = X"25" or
438
                      d_i = X"35" or
439
                      d_i = X"2D" or
440
                      d_i = X"3D" or
441
                      d_i = X"39" or
442
                      d_i = X"21" or
443
                      d_i = X"31" or
444
                      d_i = X"C9" or
445
                      d_i = X"C5" or
446
                      d_i = X"D5" or
447
                      d_i = X"CD" or
448
                      d_i = X"DD" or
449
                      d_i = X"D9" or
450
                      d_i = X"C1" or
451
                      d_i = X"D1") AND (rdy_i = '1')) THEN
452
                  reg_sel_rb_out <= "00";
453
                  reg_sel_reg <= "00";
454
                  reg_sel_rb_in <= "11";
455
                  sig_PC <= adr_nxt_pc_i;
456
               ELSIF ((d_i = X"E6" or
457
                      d_i = X"F6" or
458
                      d_i = X"EE" or
459
                      d_i = X"FE") AND (rdy_i = '1')) THEN
460
                  zw_b4 <= X"01";
461
                  sig_PC <= adr_nxt_pc_i;
462
               ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
463
                  reg_sel_rb_out <= "01";
464
                  reg_sel_reg <= "01";
465
                  reg_sel_rb_in <= "11";
466
                  zw_b4 <= X"01";
467
               ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
468
                  reg_sel_rb_out <= "10";
469
                  reg_sel_reg <= "10";
470
                  reg_sel_rb_in <= "11";
471
                  zw_b4 <= X"01";
472
               ELSIF ((d_i = X"4C" or
473
                      d_i = X"6C") AND (rdy_i = '1')) THEN
474
                  sig_PC <= adr_nxt_pc_i;
475
               ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
476
                  sig_PC <= adr_nxt_pc_i;
477
               ELSIF ((d_i = X"A9" or
478
                      d_i = X"A5" or
479
                      d_i = X"B5" or
480
                      d_i = X"AD" or
481
                      d_i = X"BD" or
482
                      d_i = X"B9" or
483
                      d_i = X"A1" or
484
                      d_i = X"B1") AND (rdy_i = '1')) THEN
485
                  reg_sel_reg <= "00";
486
                  reg_sel_rb_in <= "11";
487
                  sig_PC <= adr_nxt_pc_i;
488
               ELSIF ((d_i = X"A2" or
489
                      d_i = X"A6" or
490
                      d_i = X"B6" or
491
                      d_i = X"AE" or
492
                      d_i = X"BE") AND (rdy_i = '1')) THEN
493
                  reg_sel_reg <= "01";
494
                  reg_sel_rb_in <= "11";
495
                  sig_PC <= adr_nxt_pc_i;
496
               ELSIF ((d_i = X"A0" or
497
                      d_i = X"A4" or
498
                      d_i = X"B4" or
499
                      d_i = X"AC" or
500
                      d_i = X"BC") AND (rdy_i = '1')) THEN
501
                  reg_sel_reg <= "10";
502
                  reg_sel_rb_in <= "11";
503
                  sig_PC <= adr_nxt_pc_i;
504
               ELSIF ((d_i = X"46" or
505
                      d_i = X"56" or
506
                      d_i = X"4E" or
507
                      d_i = X"5E") AND (rdy_i = '1')) THEN
508
                  sig_PC <= adr_nxt_pc_i;
509
               ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
510
               ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
511
                  sig_PC <= adr_nxt_pc_i;
512
               ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
513
                  sig_PC <= adr_nxt_pc_i;
514
               ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
515
                  reg_sel_sp_in <= '0';
516
                  reg_sel_sp_as <= '0';
517
 
518
                  reg_sel_reg <= "00";
519
                  reg_sel_rb_in <= "11";
520
               ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
521
                  reg_sel_sp_in <= '0';
522
                  reg_sel_sp_as <= '0';
523
               ELSIF ((d_i = X"26" or
524
                      d_i = X"36" or
525
                      d_i = X"2E" or
526
                      d_i = X"3E") AND (rdy_i = '1')) THEN
527
                  sig_PC <= adr_nxt_pc_i;
528
               ELSIF ((d_i = X"66" or
529
                      d_i = X"76" or
530
                      d_i = X"6E" or
531
                      d_i = X"7E") AND (rdy_i = '1')) THEN
532
                  sig_PC <= adr_nxt_pc_i;
533
               ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
534
                  sig_PC <= adr_nxt_pc_i;
535
                  reg_sel_sp_in <= '0';
536
                  reg_sel_sp_as <= '0';
537
               ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
538
                  sig_PC <= adr_nxt_pc_i;
539
                  reg_sel_sp_in <= '0';
540
                  reg_sel_sp_as <= '0';
541
               ELSIF ((d_i = X"E9" or
542
                      d_i = X"E5" or
543
                      d_i = X"F5" or
544
                      d_i = X"ED" or
545
                      d_i = X"FD" or
546
                      d_i = X"F9" or
547
                      d_i = X"E1" or
548
                      d_i = X"F1") AND (rdy_i = '1')) THEN
549
                  sig_PC <= adr_nxt_pc_i;
550
                  reg_sel_reg <= "00";
551
                  reg_sel_rb_in <= "11";
552
                  zw_b1(0) <= reg_F(7);
553
               ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
554
               ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
555
               ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
556
               ELSIF ((d_i = X"85" or
557
                      d_i = X"95" or
558
                      d_i = X"8D" or
559
                      d_i = X"9D" or
560
                      d_i = X"99" or
561
                      d_i = X"81" or
562
                      d_i = X"91") AND (rdy_i = '1')) THEN
563
                  reg_sel_rb_out <= "00";
564
                  sig_PC <= adr_nxt_pc_i;
565
               ELSIF ((d_i = X"86" or
566
                      d_i = X"96" or
567
                      d_i = X"8E") AND (rdy_i = '1')) THEN
568
                  reg_sel_rb_out <= "01";
569
                  sig_PC <= adr_nxt_pc_i;
570
               ELSIF ((d_i = X"84" or
571
                      d_i = X"94" or
572
                      d_i = X"8C") AND (rdy_i = '1')) THEN
573
                  reg_sel_rb_out <= "10";
574
                  sig_PC <= adr_nxt_pc_i;
575
               ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
576
                  reg_sel_rb_out <= "00";
577
                  reg_sel_reg <= "01";
578
                  reg_sel_rb_in <= "00";
579
                  reg_sel_sp_in <= '1';
580
                  reg_sel_sp_as <= '0';
581
               ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
582
                  reg_sel_rb_out <= "00";
583
                  reg_sel_reg <= "00";
584
                  reg_sel_rb_in <= "11";
585
               ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
586
                  reg_sel_rb_out <= "00";
587
                  reg_sel_reg <= "00";
588
                  reg_sel_rb_in <= "11";
589
               ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
590
                  reg_sel_rb_out <= "00";
591
                  reg_sel_reg <= "00";
592
                  reg_sel_rb_in <= "11";
593
               ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
594
                  reg_sel_rb_out <= "00";
595
                  reg_sel_reg <= "00";
596
                  reg_sel_rb_in <= "11";
597
               ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
598
                  reg_sel_rb_out <= "00";
599
                  reg_sel_reg <= "10";
600
                  reg_sel_rb_in <= "00";
601
                  reg_sel_sp_in <= '1';
602
                  reg_sel_sp_as <= '0';
603
               ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
604
                  reg_sel_rb_out <= "10";
605
                  reg_sel_reg <= "00";
606
                  reg_sel_rb_in <= "01";
607
                  reg_sel_sp_in <= '1';
608
                  reg_sel_sp_as <= '0';
609
               ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
610
                  reg_sel_rb_out <= "01";
611
                  reg_sel_reg <= "01";
612
                  reg_sel_rb_in <= "11";
613
                  reg_sel_sp_in <= '1';
614
                  reg_sel_sp_as <= '0';
615
               ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
616
                  reg_sel_rb_out <= "01";
617
                  reg_sel_reg <= "00";
618
                  reg_sel_rb_in <= "10";
619
                  reg_sel_sp_in <= '1';
620
                  reg_sel_sp_as <= '0';
621
               ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
622
                  reg_sel_rb_out <= "01";
623
                  reg_sel_reg <= "11";
624
                  reg_sel_rb_in <= "11";
625
                  reg_sel_sp_in <= '1';
626
                  reg_sel_sp_as <= '0';
627
               END IF;
628
            WHEN s1 =>
629
               IF (rdy_i = '1') THEN
630
                  sig_PC <= adr_pc_i;
631
                  reg_sel_pc_in <= '0';
632
                  reg_sel_pc_val <= "00";
633
                  reg_sel_sp_in <= '0';
634
                  reg_sel_sp_as <= '1';
635
               END IF;
636
            WHEN s2 =>
637
               IF (rdy_i = '1') THEN
638
                  sig_PC <= adr_pc_i;
639
                  reg_F(0) <= '1';
640
                  reg_sel_pc_in <= '0';
641
                  reg_sel_pc_val <= "00";
642
                  reg_sel_sp_in <= '0';
643
                  reg_sel_sp_as <= '1';
644
               END IF;
645
            WHEN s5 =>
646
               IF (rdy_i = '1') THEN
647
                  sig_PC <= adr_pc_i;
648
                  reg_F(3) <= '1';
649
                  reg_sel_pc_in <= '0';
650
                  reg_sel_pc_val <= "00";
651
                  reg_sel_sp_in <= '0';
652
                  reg_sel_sp_as <= '1';
653
               END IF;
654
            WHEN s3 =>
655
               sig_PC <= adr_pc_i;
656
               IF (rdy_i = '1') THEN
657
                  sig_PC <= adr_pc_i;
658
                  reg_F(2) <= '1';
659
                  reg_sel_pc_in <= '0';
660
                  reg_sel_pc_val <= "00";
661
                  reg_sel_sp_in <= '0';
662
                  reg_sel_sp_as <= '1';
663
               END IF;
664
            WHEN s4 =>
665
               IF (rdy_i = '1' and
666
                   zw_REG_OP = X"9A") THEN
667
                  sig_PC <= adr_pc_i;
668
                  reg_sel_pc_in <= '0';
669
                  reg_sel_pc_val <= "00";
670
                  reg_sel_sp_in <= '0';
671
                  reg_sel_sp_as <= '1';
672
               ELSIF (rdy_i = '1' and
673
                      zw_REG_OP = X"BA") THEN
674
                  sig_PC <= adr_pc_i;
675
                  reg_F(7) <= reg_7flag_i;
676
                  reg_F(1) <= reg_1flag_i;
677
                  reg_sel_pc_in <= '0';
678
                  reg_sel_pc_val <= "00";
679
                  reg_sel_sp_in <= '0';
680
                  reg_sel_sp_as <= '1';
681
               ELSIF (rdy_i = '1') THEN
682
                  sig_PC <= adr_pc_i;
683
                  reg_F(7) <= reg_7flag_i;
684
                  reg_F(1) <= reg_1flag_i;
685
                  reg_sel_pc_in <= '0';
686
                  reg_sel_pc_val <= "00";
687
                  reg_sel_sp_in <= '0';
688
                  reg_sel_sp_as <= '1';
689
               END IF;
690
            WHEN s12 =>
691
               IF (rdy_i = '1') THEN
692
                  sig_PC <= adr_pc_i;
693
                  reg_F(0) <= '0';
694
                  reg_sel_pc_in <= '0';
695
                  reg_sel_pc_val <= "00";
696
                  reg_sel_sp_in <= '0';
697
                  reg_sel_sp_as <= '1';
698
               END IF;
699
            WHEN s16 =>
700
               IF (rdy_i = '1') THEN
701
                  sig_PC <= adr_pc_i;
702
                  reg_F(3) <= '0';
703
                  reg_sel_pc_in <= '0';
704
                  reg_sel_pc_val <= "00";
705
                  reg_sel_sp_in <= '0';
706
                  reg_sel_sp_as <= '1';
707
               END IF;
708
            WHEN s17 =>
709
               IF (rdy_i = '1') THEN
710
                  sig_PC <= adr_pc_i;
711
                  reg_F(2) <= '0';
712
                  reg_sel_pc_in <= '0';
713
                  reg_sel_pc_val <= "00";
714
                  reg_sel_sp_in <= '0';
715
                  reg_sel_sp_as <= '1';
716
               END IF;
717
            WHEN s24 =>
718
               IF (rdy_i = '1') THEN
719
                  sig_PC <= adr_pc_i;
720
                  reg_F(6) <= '0';
721
                  reg_sel_pc_in <= '0';
722
                  reg_sel_pc_val <= "00";
723
                  reg_sel_sp_in <= '0';
724
                  reg_sel_sp_as <= '1';
725
               END IF;
726
            WHEN s25 =>
727
               IF (rdy_i = '1') THEN
728
                  sig_PC <= adr_pc_i;
729
                  reg_F(7) <= reg_7flag_i;
730
                  reg_F(1) <= reg_1flag_i;
731
                  reg_sel_pc_in <= '0';
732
                  reg_sel_pc_val <= "00";
733
                  reg_sel_sp_in <= '0';
734
                  reg_sel_sp_as <= '1';
735
               END IF;
736
            WHEN s271 =>
737
               IF (rdy_i = '1' and
738
                   zw_REG_OP = X"4C") THEN
739
                  sig_PC <= adr_nxt_pc_i;
740
                  reg_sel_pc_in <= '1';
741
 
742
                  reg_sel_pc_val <= "11";
743
                  zw_b1 <= d_i;
744
               ELSIF (rdy_i = '1' and
745
                      zw_REG_OP = X"6C") THEN
746
                  sig_PC <= adr_nxt_pc_i;
747
                  reg_sel_pc_in <= '1';
748
 
749
                  reg_sel_pc_val <= "00";
750
                  zw_b1 <= d_i;
751
               END IF;
752
            WHEN s273 =>
753
               IF (rdy_i = '1') THEN
754
                  sig_PC <= d_i & zw_b1;
755
                  reg_sel_pc_in <= '0';
756
 
757
                  reg_sel_pc_val <= "00";
758
                  zw_b2 <= d_i;
759
               END IF;
760
            WHEN s304 =>
761
               IF (rdy_i = '1') THEN
762
                  sig_PC <= zw_b2 & adr_pc_i(7 downto 0);
763
                  reg_sel_pc_in <= '1';
764
 
765
                  reg_sel_pc_val <= "11";
766
                  zw_b1 <= d_i;
767
               END IF;
768
            WHEN s307 =>
769
               IF (rdy_i = '1') THEN
770
                  sig_PC <= d_i & zw_b1;
771
                  reg_sel_pc_in <= '0';
772
                  reg_sel_pc_val <= "00";
773
                  reg_sel_sp_in <= '0';
774
                  reg_sel_sp_as <= '1';
775
               END IF;
776
            WHEN s177 =>
777
               IF (rdy_i = '1' and
778
                   (zw_REG_OP = X"85" OR
779
                   zw_REG_OP = X"86" OR
780
                   zw_REG_OP = X"84")) THEN
781
                  sig_PC <= X"00" & d_i;
782
               ELSIF (rdy_i = '1' and
783
                      (zw_REG_OP = X"95" OR
784
                      zw_REG_OP = X"94")) THEN
785
                  sig_PC <= X"00" & d_i;
786
                  zw_b1 <= d_alu_i;
787
               ELSIF (rdy_i = '1' and
788
                      (zw_REG_OP = X"8D" OR
789
                      zw_REG_OP = X"8E" OR
790
                      zw_REG_OP = X"8C")) THEN
791
                  sig_PC <= adr_nxt_pc_i;
792
                  zw_b1 <= d_i;
793
               ELSIF (rdy_i = '1' and
794
                      zw_REG_OP = X"9D") THEN
795
                  sig_PC <= adr_nxt_pc_i;
796
                  zw_b1 <= d_alu_i;
797
                  zw_b2(0) <= reg_0flag_i;
798
               ELSIF (rdy_i = '1' and
799
                      zw_REG_OP = X"99") THEN
800
                  sig_PC <= adr_nxt_pc_i;
801
                  zw_b1 <= d_alu_i;
802
                  zw_b2(0) <= reg_0flag_i;
803
               ELSIF (rdy_i = '1' and
804
                      zw_REG_OP = X"91") THEN
805
                  sig_PC <= X"00" & d_i;
806
                  zw_b1 <= d_alu_i;
807
               ELSIF (rdy_i = '1' and
808
                      zw_REG_OP = X"81") THEN
809
                  sig_PC <= X"00" & d_i;
810
                  zw_b1 <= d_alu_i;
811
               ELSIF (rdy_i = '1' and
812
                      zw_REG_OP = X"96") THEN
813
                  sig_PC <= X"00" & d_i;
814
                  zw_b1 <= d_alu_i;
815
               END IF;
816
            WHEN s180 =>
817
               IF (rdy_i = '1') THEN
818
                  sig_PC <= d_i & zw_b1;
819
                  zw_b3 <= d_alu_i;
820
               END IF;
821
            WHEN s181 =>
822
               IF (rdy_i = '1') THEN
823
                  sig_PC <= X"00" & zw_b1;
824
                  zw_b1 <= d_alu_i;
825
                  zw_b2(0) <= reg_0flag_i;
826
               END IF;
827
            WHEN s182 =>
828
               IF (rdy_i = '1') THEN
829
                  sig_PC <= d_i & zw_b1;
830
                  zw_b3 <= d_alu_i;
831
               END IF;
832
            WHEN s183 =>
833
               IF (rdy_i = '1') THEN
834
                  sig_PC <= d_i & zw_b1;
835
               END IF;
836
            WHEN s184 =>
837
               sig_PC <= adr_pc_i;
838
               reg_sel_pc_in <= '0';
839
               reg_sel_pc_val <= "00";
840
               reg_sel_sp_in <= '0';
841
               reg_sel_sp_as <= '1';
842
            WHEN s185 =>
843
               IF (rdy_i = '1') THEN
844
                  sig_PC <= X"00" & zw_b1;
845
               END IF;
846
            WHEN s186 =>
847
               IF (rdy_i = '1') THEN
848
                  sig_PC <= X"00" & zw_b1;
849
               END IF;
850
            WHEN s187 =>
851
               sig_PC <= adr_pc_i;
852
               reg_sel_pc_in <= '0';
853
               reg_sel_pc_val <= "00";
854
               reg_sel_sp_in <= '0';
855
               reg_sel_sp_as <= '1';
856
            WHEN s188 =>
857
               IF (rdy_i = '1') THEN
858
                  sig_PC <= X"00" & d_alu_i;
859
                  zw_b1 <= d_i;
860
               END IF;
861
            WHEN s189 =>
862
               IF (rdy_i = '1') THEN
863
                  sig_PC <= d_i & zw_b1;
864
                  zw_b3 <= d_alu_i;
865
               END IF;
866
            WHEN s190 =>
867
               sig_PC <= adr_pc_i;
868
               reg_sel_pc_in <= '0';
869
               reg_sel_pc_val <= "00";
870
               reg_sel_sp_in <= '0';
871
               reg_sel_sp_as <= '1';
872
            WHEN s191 =>
873
               sig_PC <= zw_b3 & zw_b1;
874
            WHEN s192 =>
875
               sig_PC <= d_i & zw_b1;
876
            WHEN s193 =>
877
               sig_PC <= adr_pc_i;
878
               reg_sel_pc_in <= '0';
879
               reg_sel_pc_val <= "00";
880
               reg_sel_sp_in <= '0';
881
               reg_sel_sp_as <= '1';
882
            WHEN s377 =>
883
               IF (rdy_i = '1') THEN
884
                  sig_PC <= adr_sp_i;
885
               END IF;
886
            WHEN s381 =>
887
               sig_PC <= adr_pc_i;
888
               reg_sel_pc_in <= '0';
889
               reg_sel_pc_val <= "00";
890
               reg_sel_sp_in <= '0';
891
               reg_sel_sp_as <= '1';
892
            WHEN s378 =>
893
               IF (rdy_i = '1') THEN
894
                  sig_PC <= adr_sp_i;
895
               END IF;
896
            WHEN s382 =>
897
               sig_PC <= adr_pc_i;
898
               reg_sel_pc_in <= '0';
899
               reg_sel_pc_val <= "00";
900
               reg_sel_sp_in <= '0';
901
               reg_sel_sp_as <= '1';
902
            WHEN s383 =>
903
               IF (rdy_i = '1') THEN
904
                  sig_PC <= adr_sp_i;
905
               END IF;
906
            WHEN s384 =>
907
               IF (rdy_i = '1') THEN
908
                  sig_PC <= adr_pc_i;
909
                  reg_F(7) <= reg_7flag_i;
910
                  reg_F(1) <= reg_1flag_i;
911
                  reg_sel_pc_in <= '0';
912
                  reg_sel_pc_val <= "00";
913
                  reg_sel_sp_in <= '0';
914
                  reg_sel_sp_as <= '1';
915
               END IF;
916
            WHEN s385 =>
917
               IF (rdy_i = '1') THEN
918
                  sig_PC <= adr_sp_i;
919
               END IF;
920
            WHEN s386 =>
921
               IF (rdy_i = '1') THEN
922
                  sig_PC <= adr_pc_i;
923
                  reg_F <= d_i;
924
                  reg_sel_pc_in <= '0';
925
                  reg_sel_pc_val <= "00";
926
                  reg_sel_sp_in <= '0';
927
                  reg_sel_sp_as <= '1';
928
               END IF;
929
            WHEN s387 =>
930
               IF (rdy_i = '1') THEN
931
                  sig_PC <= adr_sp_i;
932
               END IF;
933
            WHEN s388 =>
934
               IF (rdy_i = '1') THEN
935
                  sig_PC <= adr_sp_i;
936
               END IF;
937
            WHEN s389 =>
938
               IF (rdy_i = '1') THEN
939
                  sig_PC <= adr_sp_i;
940
                  reg_F <= d_i;
941
                  reg_sel_pc_in <= '1';
942
 
943
                  reg_sel_pc_val <= "11";
944
               END IF;
945
            WHEN s391 =>
946
               IF (rdy_i = '1') THEN
947
                  sig_PC <= adr_sp_i;
948
                  zw_b1 <= d_i;
949
               END IF;
950
            WHEN s392 =>
951
               IF (rdy_i = '1') THEN
952
                  sig_PC <= d_i & zw_b1;
953
                  reg_sel_pc_in <= '0';
954
                  reg_sel_pc_val <= "00";
955
                  reg_sel_sp_in <= '0';
956
                  reg_sel_sp_as <= '1';
957
               END IF;
958
            WHEN s390 =>
959
               IF (rdy_i = '1') THEN
960
                  sig_PC <= adr_sp_i;
961
               END IF;
962
            WHEN s393 =>
963
               IF (rdy_i = '1') THEN
964
                  sig_PC <= adr_sp_i;
965
               END IF;
966
            WHEN s394 =>
967
               IF (rdy_i = '1') THEN
968
                  sig_PC <= adr_sp_i;
969
                  zw_b1 <= d_i;
970
                  reg_sel_pc_in <= '1';
971
 
972
                  reg_sel_pc_val <= "00";
973
               END IF;
974
            WHEN s395 =>
975
               IF (rdy_i = '1') THEN
976
                  sig_PC <= d_i & zw_b1;
977
               END IF;
978
            WHEN s396 =>
979
               IF (rdy_i = '1') THEN
980
                  sig_PC <= adr_pc_i;
981
                  reg_sel_pc_in <= '0';
982
                  reg_sel_pc_val <= "00";
983
                  reg_sel_sp_in <= '0';
984
                  reg_sel_sp_as <= '1';
985
               END IF;
986
            WHEN s397 =>
987
               IF (rdy_i = '1') THEN
988
                  sig_PC <= adr_sp_i;
989
                  zw_b1 <= d_i;
990
               END IF;
991
            WHEN s399 =>
992
               sig_PC <= adr_sp_i;
993
            WHEN s400 =>
994
               sig_PC <= adr_pc_i;
995
               reg_sel_pc_in <= '1';
996
 
997
               reg_sel_pc_val <= "11";
998
            WHEN s401 =>
999
               IF (rdy_i = '1') THEN
1000
                  sig_PC <= d_i & zw_b1 (7 downto 0);
1001
                  reg_sel_pc_in <= '0';
1002
                  reg_sel_pc_val <= "00";
1003
                  reg_sel_sp_in <= '0';
1004
                  reg_sel_sp_as <= '1';
1005
               END IF;
1006
            WHEN s526 =>
1007
               IF (rdy_i = '1') THEN
1008
                  sig_PC <= adr_sp_i;
1009
               END IF;
1010
            WHEN s527 =>
1011
               sig_PC <= adr_sp_i;
1012
            WHEN s528 =>
1013
               sig_PC <= adr_sp_i;
1014
            WHEN s529 =>
1015
               sig_PC <= X"FFFE";
1016
            WHEN s530 =>
1017
               IF (rdy_i = '1') THEN
1018
                  sig_PC <= d_i & zw_b1;
1019
                  reg_F(2) <= '1';
1020
                  reg_sel_pc_in <= '0';
1021
                  reg_sel_pc_val <= "00";
1022
                  reg_sel_sp_in <= '0';
1023
                  reg_sel_sp_as <= '1';
1024
               END IF;
1025
            WHEN s531 =>
1026
               IF (rdy_i = '1') THEN
1027
                  sig_PC <= X"FFFF";
1028
                  reg_sel_pc_in <= '1';
1029
 
1030
                  reg_sel_pc_val <= "11";
1031
                  zw_b1 <= d_i;
1032
               END IF;
1033
            WHEN s544 =>
1034
               sig_PC <= adr_sp_i;
1035
            WHEN s545 =>
1036
               sig_PC <= adr_sp_i;
1037
               reg_sel_pc_in <= '0';
1038
 
1039
               reg_sel_pc_val <= "00";
1040
            WHEN s546 =>
1041
               sig_PC <= adr_pc_i;
1042
            WHEN s547 =>
1043
               IF (rdy_i = '1') THEN
1044
                  sig_PC <= adr_pc_i;
1045
                  zw_b1 <= d_i;
1046
                  reg_sel_pc_in <= '1';
1047
 
1048
                  reg_sel_pc_val <= "11";
1049
               END IF;
1050
            WHEN s549 =>
1051
               IF (rdy_i = '1') THEN
1052
                  sig_PC  <= d_i & zw_b1;
1053
                  reg_sel_pc_in <= '0';
1054
                  reg_sel_pc_val <= "00";
1055
                  reg_sel_sp_in <= '0';
1056
                  reg_sel_sp_as <= '1';
1057
               END IF;
1058
            WHEN s550 =>
1059
               sig_PC <= adr_sp_i;
1060
               reg_sel_pc_in <= '1';
1061
 
1062
               reg_sel_pc_val <= "00";
1063
            WHEN s404 =>
1064
               IF (rdy_i = '1') THEN
1065
                  sig_PC <= adr_pc_i;
1066
                  reg_F(0) <= q_a_i(7);
1067
                  reg_F(7) <= reg_7flag_i;
1068
                  reg_F(1) <= reg_1flag_i;
1069
                  reg_sel_pc_in <= '0';
1070
                  reg_sel_pc_val <= "00";
1071
                  reg_sel_sp_in <= '0';
1072
                  reg_sel_sp_as <= '1';
1073
               END IF;
1074
            WHEN s556 =>
1075
               IF (rdy_i = '1') THEN
1076
                  sig_PC <= adr_pc_i;
1077
                  reg_F(0) <= q_a_i(0);
1078
                  reg_F(7) <= reg_7flag_i;
1079
                  reg_F(1) <= reg_1flag_i;
1080
                  reg_sel_pc_in <= '0';
1081
                  reg_sel_pc_val <= "00";
1082
                  reg_sel_sp_in <= '0';
1083
                  reg_sel_sp_as <= '1';
1084
               END IF;
1085
            WHEN s557 =>
1086
               IF (rdy_i = '1') THEN
1087
                  sig_PC <= adr_pc_i;
1088
                  reg_F(0) <= q_a_i(7);
1089
                  reg_F(0) <= q_a_i(7);
1090
                  reg_F(7) <= reg_7flag_i;
1091
                  reg_F(1) <= reg_1flag_i;
1092
                  reg_sel_pc_in <= '0';
1093
                  reg_sel_pc_val <= "00";
1094
                  reg_sel_sp_in <= '0';
1095
                  reg_sel_sp_as <= '1';
1096
               END IF;
1097
            WHEN s579 =>
1098
               IF (rdy_i = '1') THEN
1099
                  sig_PC <= adr_pc_i;
1100
                  reg_F(0) <= q_a_i(0);
1101
                  reg_F(7) <= reg_7flag_i;
1102
                  reg_F(1) <= reg_1flag_i;
1103
                  reg_sel_pc_in <= '0';
1104
                  reg_sel_pc_val <= "00";
1105
                  reg_sel_sp_in <= '0';
1106
                  reg_sel_sp_as <= '1';
1107
               END IF;
1108
            WHEN s201 =>
1109
               IF (rdy_i = '1' and
1110
                   (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
1111
                   zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
1112
                   zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
1113
                   zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
1114
                  sig_PC <= X"00" & d_i;
1115
               ELSIF ((rdy_i = '1' and
1116
                      (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
1117
                      zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
1118
                      zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
1119
                      zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
1120
                      zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
1121
                  sig_PC <= adr_nxt_pc_i;
1122
                  reg_F(7) <= reg_7flag_i;
1123
                  reg_F(1) <= reg_1flag_i;
1124
                  reg_sel_pc_in <= '0';
1125
                  reg_sel_pc_val <= "00";
1126
                  reg_sel_sp_in <= '0';
1127
                  reg_sel_sp_as <= '1';
1128
               ELSIF ((rdy_i = '1' and
1129
                      (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
1130
                      zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
1131
                      zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
1132
                      zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
1133
                      zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
1134
                  sig_PC <= adr_nxt_pc_i;
1135
                  reg_F(7) <= reg_7flag_i;
1136
                  reg_F(1) <= reg_1flag_i;
1137
                  reg_sel_pc_in <= '0';
1138
                  reg_sel_pc_val <= "00";
1139
                  reg_sel_sp_in <= '0';
1140
                  reg_sel_sp_as <= '1';
1141
               ELSIF ((rdy_i = '1' and
1142
                      (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
1143
                      zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
1144
                      zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
1145
                      zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
1146
                       zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
1147
                  sig_PC <= adr_nxt_pc_i;
1148
                  reg_F(7) <= reg_7flag_i;
1149
                  reg_F(1) <= reg_1flag_i;
1150
                  reg_sel_pc_in <= '0';
1151
                  reg_sel_pc_val <= "00";
1152
                  reg_sel_sp_in <= '0';
1153
                  reg_sel_sp_as <= '1';
1154
               ELSIF ((rdy_i = '1' and
1155
                      (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
1156
                      zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
1157
                      zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
1158
                      zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
1159
                      zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
1160
                       zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
1161
                       zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
1162
                       zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
1163
                  sig_PC <= adr_nxt_pc_i;
1164
                  reg_F(7) <= zw_ALU(7);
1165
                  reg_F(0) <= zw_ALU(8);
1166
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
1167
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
1168
                  (zw_ALU(0)));
1169
                  reg_sel_pc_in <= '0';
1170
                  reg_sel_pc_val <= "00";
1171
                  reg_sel_sp_in <= '0';
1172
                  reg_sel_sp_as <= '1';
1173
               ELSIF (rdy_i = '1' and
1174
                      (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
1175
                      zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
1176
                  sig_PC <= adr_nxt_pc_i;
1177
                  reg_F(7) <= reg_7flag_i;
1178
                  reg_F(1) <= reg_1flag_i;
1179
                  reg_sel_pc_in <= '0';
1180
                  reg_sel_pc_val <= "00";
1181
                  reg_sel_sp_in <= '0';
1182
                  reg_sel_sp_as <= '1';
1183
               ELSIF (rdy_i = '1' and
1184
                      (zw_REG_OP = X"B5" OR
1185
                      zw_REG_OP = X"B4" OR
1186
                      zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
1187
                      zw_REG_OP = X"35" OR
1188
                      zw_REG_OP = X"D5")) THEN
1189
                  sig_PC <= X"00" & d_i;
1190
                  zw_b1 <= d_alu_i;
1191
               ELSIF (rdy_i = '1' and
1192
                      (zw_REG_OP = X"AD" OR
1193
                      zw_REG_OP = X"AE" OR
1194
                      zw_REG_OP = X"AC" OR
1195
                      zw_REG_OP = X"4D" OR
1196
                      zw_REG_OP = X"0D" OR
1197
                      zw_REG_OP = X"2D" OR
1198
                      zw_REG_OP = X"CD" OR
1199
                      zw_REG_OP = X"EC" OR
1200
                      zw_REG_OP = X"CC")) THEN
1201
                  sig_PC <= adr_nxt_pc_i;
1202
                  zw_b1 <= d_i;
1203
               ELSIF (rdy_i = '1' and
1204
                      (zw_REG_OP = X"BD" OR
1205
                      zw_REG_OP = X"BC" OR
1206
                      zw_REG_OP = X"5D" OR
1207
                      zw_REG_OP = X"1D" OR
1208
                      zw_REG_OP = X"3D" OR
1209
                      zw_REG_OP = X"DD")) THEN
1210
                  sig_PC <= adr_nxt_pc_i;
1211
                  zw_b1 <= d_alu_i;
1212
                  zw_b2(0) <= reg_0flag_i;
1213
               ELSIF (rdy_i = '1' and
1214
                      (zw_REG_OP = X"B9" OR
1215
                      zw_REG_OP = X"BE" OR
1216
                      zw_REG_OP = X"59" OR
1217
                      zw_REG_OP = X"19" OR
1218
                      zw_REG_OP = X"39" OR
1219
                      zw_REG_OP = X"D9")) THEN
1220
                  sig_PC <= adr_nxt_pc_i;
1221
                  zw_b1 <= d_alu_i;
1222
                  zw_b2(0) <= reg_0flag_i;
1223
               ELSIF (rdy_i = '1' and
1224
                      (zw_REG_OP = X"B1" OR
1225
                      zw_REG_OP = X"51" OR
1226
                      zw_REG_OP = X"11" OR
1227
                      zw_REG_OP = X"31" OR
1228
                      zw_REG_OP = X"D1")) THEN
1229
                  sig_PC <= X"00" & d_i;
1230
                  zw_b1 <= d_alu_i;
1231
               ELSIF (rdy_i = '1' and
1232
                      (zw_REG_OP = X"A1" OR
1233
                      zw_REG_OP = X"41" OR
1234
                      zw_REG_OP = X"01" OR
1235
                      zw_REG_OP = X"21" OR
1236
                      zw_REG_OP = X"C1")) THEN
1237
                  sig_PC <= X"00" & d_i;
1238
                  zw_b1 <= d_alu_i;
1239
               ELSIF (rdy_i = '1' and
1240
                      zw_REG_OP = X"B6") THEN
1241
                  sig_PC <= X"00" & d_i;
1242
                  zw_b1 <= d_alu_i;
1243
               END IF;
1244
            WHEN s202 =>
1245
               IF (rdy_i = '1') THEN
1246
                  sig_PC <= d_i & zw_b1;
1247
               END IF;
1248
            WHEN s210 =>
1249
               IF (rdy_i = '1') THEN
1250
                  sig_PC <= d_i & zw_b1;
1251
                  zw_b3 <= d_alu_i;
1252
               END IF;
1253
            WHEN s211 =>
1254
               IF (rdy_i = '1') THEN
1255
                  sig_PC <= d_i & zw_b1;
1256
                  zw_b3 <= d_alu_i;
1257
               END IF;
1258
            WHEN s215 =>
1259
               IF (rdy_i = '1') THEN
1260
                  sig_PC <= X"00" & zw_b1;
1261
                  zw_b1 <= d_alu_i;
1262
                  zw_b2(0) <= reg_0flag_i;
1263
               END IF;
1264
            WHEN s217 =>
1265
               IF (rdy_i = '1') THEN
1266
                  sig_PC <= X"00" & zw_b1;
1267
               END IF;
1268
            WHEN s218 =>
1269
               IF (rdy_i = '1') THEN
1270
                  sig_PC <= X"00" & zw_b1;
1271
               END IF;
1272
            WHEN s222 =>
1273
               IF (rdy_i = '1') THEN
1274
                  sig_PC <= X"00" & d_alu_i;
1275
                  zw_b1 <= d_i;
1276
               END IF;
1277
            WHEN s223 =>
1278
               IF (rdy_i = '1') THEN
1279
                  sig_PC <= d_i & zw_b1;
1280
                  zw_b3 <= d_alu_i;
1281
               END IF;
1282
            WHEN s224 =>
1283
               IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
1284
                   zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
1285
                   zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
1286
                   zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
1287
                  sig_PC <= adr_pc_i;
1288
                  reg_F(7) <= reg_7flag_i;
1289
                  reg_F(1) <= reg_1flag_i;
1290
                  reg_sel_pc_in <= '0';
1291
                  reg_sel_pc_val <= "00";
1292
                  reg_sel_sp_in <= '0';
1293
                  reg_sel_sp_as <= '1';
1294
               ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
1295
                      zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
1296
                      zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
1297
                      zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
1298
                  sig_PC <= adr_pc_i;
1299
                  reg_F(7) <= reg_7flag_i;
1300
                  reg_F(1) <= reg_1flag_i;
1301
                  reg_sel_pc_in <= '0';
1302
                  reg_sel_pc_val <= "00";
1303
                  reg_sel_sp_in <= '0';
1304
                  reg_sel_sp_as <= '1';
1305
               ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
1306
                      zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
1307
                      zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
1308
                       zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
1309
                  sig_PC <= adr_pc_i;
1310
                  reg_F(7) <= reg_7flag_i;
1311
                  reg_F(1) <= reg_1flag_i;
1312
                  reg_sel_pc_in <= '0';
1313
                  reg_sel_pc_val <= "00";
1314
                  reg_sel_sp_in <= '0';
1315
                  reg_sel_sp_as <= '1';
1316
               ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
1317
                      zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
1318
                      zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
1319
                      zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
1320
                       zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
1321
                       zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
1322
                       zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
1323
                  sig_PC <= adr_pc_i;
1324
                  reg_F(7) <= zw_ALU(7);
1325
                  reg_F(0) <= zw_ALU(8);
1326
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
1327
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
1328
                  (zw_ALU(0)));
1329
                  reg_sel_pc_in <= '0';
1330
                  reg_sel_pc_val <= "00";
1331
                  reg_sel_sp_in <= '0';
1332
                  reg_sel_sp_as <= '1';
1333
               ELSIF (rdy_i = '1') THEN
1334
                  sig_PC <= adr_pc_i;
1335
                  reg_F(7) <= reg_7flag_i;
1336
                  reg_F(1) <= reg_1flag_i;
1337
                  reg_sel_pc_in <= '0';
1338
                  reg_sel_pc_val <= "00";
1339
                  reg_sel_sp_in <= '0';
1340
                  reg_sel_sp_as <= '1';
1341
               END IF;
1342
            WHEN s225 =>
1343
               IF ((rdy_i = '1' AND
1344
                   zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
1345
                   zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
1346
                   zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
1347
                   zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
1348
                  sig_PC <= adr_pc_i;
1349
                  reg_F(7) <= reg_7flag_i;
1350
                  reg_F(1) <= reg_1flag_i;
1351
                  reg_sel_pc_in <= '0';
1352
                  reg_sel_pc_val <= "00";
1353
                  reg_sel_sp_in <= '0';
1354
                  reg_sel_sp_as <= '1';
1355
               ELSIF ((rdy_i = '1' AND
1356
                      zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
1357
                      zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
1358
                      zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
1359
                      zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
1360
                  sig_PC <= adr_pc_i;
1361
                  reg_F(7) <= reg_7flag_i;
1362
                  reg_F(1) <= reg_1flag_i;
1363
                  reg_sel_pc_in <= '0';
1364
                  reg_sel_pc_val <= "00";
1365
                  reg_sel_sp_in <= '0';
1366
                  reg_sel_sp_as <= '1';
1367
               ELSIF ((rdy_i = '1' AND
1368
                      zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
1369
                      zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
1370
                      zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
1371
                       zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
1372
                  sig_PC <= adr_pc_i;
1373
                  reg_F(7) <= reg_7flag_i;
1374
                  reg_F(1) <= reg_1flag_i;
1375
                  reg_sel_pc_in <= '0';
1376
                  reg_sel_pc_val <= "00";
1377
                  reg_sel_sp_in <= '0';
1378
                  reg_sel_sp_as <= '1';
1379
               ELSIF ((rdy_i = '1' AND
1380
                      zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
1381
                      zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
1382
                      zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
1383
                      zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
1384
                       zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
1385
                       zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
1386
                       zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
1387
                  sig_PC <= adr_pc_i;
1388
                  reg_F(7) <= zw_ALU(7);
1389
                  reg_F(0) <= zw_ALU(8);
1390
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
1391
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
1392
                  (zw_ALU(0)));
1393
                  reg_sel_pc_in <= '0';
1394
                  reg_sel_pc_val <= "00";
1395
                  reg_sel_sp_in <= '0';
1396
                  reg_sel_sp_as <= '1';
1397
               ELSIF (rdy_i = '1' AND
1398
                      zw_b2(0) = '0') THEN
1399
                  sig_PC <= adr_pc_i;
1400
                  reg_F(7) <= reg_7flag_i;
1401
                  reg_F(1) <= reg_1flag_i;
1402
                  reg_sel_pc_in <= '0';
1403
                  reg_sel_pc_val <= "00";
1404
                  reg_sel_sp_in <= '0';
1405
                  reg_sel_sp_as <= '1';
1406
               ELSIF (rdy_i = '1') THEN
1407
                  sig_PC <= zw_b3 & zw_b1;
1408
               END IF;
1409
            WHEN s226 =>
1410
               IF (rdy_i = '1' and
1411
                   (zw_REG_OP = X"C6" OR
1412
                   zw_REG_OP = X"E6")) THEN
1413
                  sig_PC <= X"00" & d_i;
1414
               ELSIF (rdy_i = '1' and
1415
                      (zw_REG_OP = X"D6" OR
1416
                      zw_REG_OP = X"F6")) THEN
1417
                  sig_PC <= X"00" & d_i;
1418
                  zw_b1 <= d_alu_i;
1419
               ELSIF (rdy_i = '1' and
1420
                      (zw_REG_OP = X"CE" OR
1421
                      zw_REG_OP = X"EE")) THEN
1422
                  sig_PC <= adr_nxt_pc_i;
1423
                  zw_b1 <= d_i;
1424
               ELSIF (rdy_i = '1' and
1425
                      (zw_REG_OP = X"DE" OR
1426
                      zw_REG_OP = X"FE")) THEN
1427
                  sig_PC <= adr_nxt_pc_i;
1428
                  zw_b1 <= d_alu_i;
1429
                  zw_b2(0) <= reg_0flag_i;
1430
               END IF;
1431
            WHEN s243 =>
1432
               IF (rdy_i = '1') THEN
1433
                  sig_PC <= d_i & zw_b1;
1434
               END IF;
1435
            WHEN s244 =>
1436
               IF (rdy_i = '1') THEN
1437
                  sig_PC <= d_i & zw_b1;
1438
                  zw_b3 <= d_alu_i;
1439
               END IF;
1440
            WHEN s247 =>
1441
               IF (rdy_i = '1') THEN
1442
                  sig_PC <= X"00" & zw_b1;
1443
               END IF;
1444
            WHEN s344 =>
1445
               IF (rdy_i = '1') THEN
1446
                  sig_PC <= zw_b3 & zw_b1;
1447
               END IF;
1448
            WHEN s343 =>
1449
               IF (rdy_i = '1') THEN
1450
                  zw_b1 <= d_alu_i;
1451
               END IF;
1452
            WHEN s251 =>
1453
               sig_PC <= adr_pc_i;
1454
               reg_F(7) <= reg_7flag_i;
1455
               reg_F(1) <= reg_1flag_i;
1456
               reg_sel_pc_in <= '0';
1457
               reg_sel_pc_val <= "00";
1458
               reg_sel_sp_in <= '0';
1459
               reg_sel_sp_as <= '1';
1460
            WHEN s351 =>
1461
               IF (rdy_i = '1' and
1462
                   zw_REG_OP = X"24") THEN
1463
                  sig_PC <= X"00" & d_i;
1464
               ELSIF (rdy_i = '1' and
1465
                      zw_REG_OP = X"2C") THEN
1466
                  sig_PC <= adr_nxt_pc_i;
1467
                  zw_b1 <= d_i;
1468
               END IF;
1469
            WHEN s361 =>
1470
               IF (rdy_i = '1') THEN
1471
                  sig_PC <= adr_pc_i;
1472
                  reg_F(7) <= d_i(7);
1473
                  reg_F(6) <= d_i(6);
1474
                  reg_F(1) <= reg_1flag_i;
1475
                  reg_sel_pc_in <= '0';
1476
                  reg_sel_pc_val <= "00";
1477
                  reg_sel_sp_in <= '0';
1478
                  reg_sel_sp_as <= '1';
1479
               END IF;
1480
            WHEN s360 =>
1481
               IF (rdy_i = '1') THEN
1482
                  sig_PC <= d_i & zw_b1;
1483
               END IF;
1484
            WHEN s403 =>
1485
               IF (rdy_i = '1' and
1486
                   (zw_REG_OP = X"1E" or
1487
                   zw_REG_OP = X"7E" or
1488
                   zw_REG_OP = X"3E" or
1489
                   zw_REG_OP = X"5E")) THEN
1490
                  sig_PC <= adr_nxt_pc_i;
1491
                  zw_b1 <= d_alu_i;
1492
                  zw_b2(0) <= reg_0flag_i;
1493
               ELSIF (rdy_i = '1' and
1494
                      (zw_REG_OP = X"06" or
1495
                      zw_REG_OP = X"66" or
1496
                      zw_REG_OP = X"26" or
1497
                      zw_REG_OP = X"46")) THEN
1498
                  sig_PC <= X"00" & d_i;
1499
               ELSIF (rdy_i = '1' and
1500
                      (zw_REG_OP = X"16" or
1501
                      zw_REG_OP = X"76" or
1502
                      zw_REG_OP = X"36" or
1503
                      zw_REG_OP = X"56")) THEN
1504
                  sig_PC <= X"00" & d_i;
1505
                  zw_b1 <= d_alu_i;
1506
               ELSIF (rdy_i = '1' and
1507
                      (zw_REG_OP = X"0E" or
1508
                      zw_REG_OP = X"6E" or
1509
                      zw_REG_OP = X"2E" or
1510
                      zw_REG_OP = X"4E")) THEN
1511
                  sig_PC <= adr_nxt_pc_i;
1512
                  zw_b1 <= d_i;
1513
               END IF;
1514
            WHEN s406 =>
1515
               IF (rdy_i = '1') THEN
1516
                  sig_PC <= d_i & zw_b1;
1517
               END IF;
1518
            WHEN s407 =>
1519
               IF (rdy_i = '1') THEN
1520
                  sig_PC <= d_i & zw_b1;
1521
                  zw_b3 <= d_alu_i;
1522
               END IF;
1523
            WHEN s409 =>
1524
               IF (rdy_i = '1') THEN
1525
                  sig_PC <= X"00" & zw_b1;
1526
               END IF;
1527
            WHEN s412 =>
1528
               IF (rdy_i = '1') THEN
1529
                  sig_PC <= zw_b3 & zw_b1;
1530
               END IF;
1531
            WHEN s416 =>
1532
               IF (rdy_i = '1' and
1533
                   (zw_REG_OP = X"06" or
1534
                   zw_REG_OP = X"16" or
1535
                   zw_REG_OP = X"0E" or
1536
                   zw_REG_OP = X"1E")) THEN
1537
                  zw_b1 <= d_i(6 downto 0) & '0';
1538
                  zw_b2(0) <= d_i(7);
1539
               ELSIF (rdy_i = '1' and
1540
                      (zw_REG_OP = X"46" or
1541
                      zw_REG_OP = X"56" or
1542
                      zw_REG_OP = X"4E" or
1543
                      zw_REG_OP = X"5E")) THEN
1544
                  zw_b1 <= '0' & d_i(7 downto 1);
1545
                  zw_b2(0) <= d_i(0);
1546
               ELSIF (rdy_i = '1' and
1547
                      (zw_REG_OP = X"26" or
1548
                      zw_REG_OP = X"36" or
1549
                      zw_REG_OP = X"2E" or
1550
                      zw_REG_OP = X"3E")) THEN
1551
                  zw_b1 <= d_i(6 downto 0) & reg_F(0);
1552
                  zw_b2(0) <= d_i(7);
1553
               ELSIF (rdy_i = '1' and
1554
                      (zw_REG_OP = X"66" or
1555
                      zw_REG_OP = X"76" or
1556
                      zw_REG_OP = X"6E" or
1557
                      zw_REG_OP = X"7E")) THEN
1558
                  zw_b1 <= reg_F(0) & d_i(7 downto 1);
1559
                  zw_b2(0) <= d_i(0);
1560
               END IF;
1561
            WHEN s418 =>
1562
               sig_PC <= adr_pc_i;
1563
               reg_F(0) <= zw_b2(0);
1564
               reg_F(7) <= reg_7flag_i;
1565
               reg_F(1) <= reg_1flag_i;
1566
               reg_sel_pc_in <= '0';
1567
               reg_sel_pc_val <= "00";
1568
               reg_sel_sp_in <= '0';
1569
               reg_sel_sp_as <= '1';
1570
            WHEN s510 =>
1571
               IF (rdy_i = '1' and
1572
                   zw_REG_OP = X"65") THEN
1573
                  sig_PC <= X"00" & d_i;
1574
               ELSIF (rdy_i = '1' and
1575
                      zw_REG_OP = X"69" and
1576
                      reg_F(3) = '0') THEN
1577
                  sig_PC <= adr_nxt_pc_i;
1578
 
1579
                  reg_F(7) <= zw_ALU(7);
1580
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
1581
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
1582
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
1583
                  (zw_ALU(0)));
1584
                  reg_F(0) <= zw_ALU(8);
1585
                  reg_sel_pc_in <= '0';
1586
                  reg_sel_pc_val <= "00";
1587
                  reg_sel_sp_in <= '0';
1588
                  reg_sel_sp_as <= '1';
1589
               ELSIF (rdy_i = '1' and
1590
                      zw_REG_OP = X"75") THEN
1591
                  sig_PC <= X"00" & d_i;
1592
                  zw_b1 <= d_alu_i;
1593
               ELSIF (rdy_i = '1' and
1594
                      zw_REG_OP = X"6D") THEN
1595
                  sig_PC <= adr_nxt_pc_i;
1596
                  zw_b1 <= d_i;
1597
               ELSIF (rdy_i = '1' and
1598
                      zw_REG_OP = X"7D") THEN
1599
                  sig_PC <= adr_nxt_pc_i;
1600
                  zw_b1 <= d_alu_i;
1601
                  zw_b2(0) <= reg_0flag_i;
1602
               ELSIF (rdy_i = '1' and
1603
                      zw_REG_OP = X"79") THEN
1604
                  sig_PC <= adr_nxt_pc_i;
1605
                  zw_b1 <= d_alu_i;
1606
                  zw_b2(0) <= reg_0flag_i;
1607
               ELSIF (rdy_i = '1' and
1608
                      zw_REG_OP = X"71") THEN
1609
                  sig_PC <= X"00" & d_i;
1610
                  zw_b1 <= d_alu_i;
1611
               ELSIF (rdy_i = '1' and
1612
                      zw_REG_OP = X"61") THEN
1613
                  sig_PC <= X"00" & d_i;
1614
                  zw_b1 <= d_alu_i;
1615
               ELSIF (rdy_i = '1' and
1616
                      zw_REG_OP = X"69" and
1617
                      reg_F(3) = '1') THEN
1618
                  sig_PC <= adr_nxt_pc_i;
1619
 
1620
                  reg_F(7) <= zw_ALU(7);
1621
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
1622
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
1623
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
1624
                  (zw_ALU(0)));
1625
                  reg_F(0) <= zw_ALU4(4);
1626
                  reg_sel_pc_in <= '0';
1627
                  reg_sel_pc_val <= "00";
1628
                  reg_sel_sp_in <= '0';
1629
                  reg_sel_sp_as <= '1';
1630
               END IF;
1631
            WHEN s553 =>
1632
               IF (rdy_i = '1') THEN
1633
                  sig_PC <= d_i & zw_b1;
1634
               END IF;
1635
            WHEN s555 =>
1636
               IF (rdy_i = '1') THEN
1637
                  sig_PC <= d_i & zw_b1;
1638
                  zw_b3 <= d_alu_i;
1639
               END IF;
1640
            WHEN s558 =>
1641
               IF (rdy_i = '1') THEN
1642
                  sig_PC <= X"00" & zw_b1;
1643
                  zw_b1 <= d_alu_i;
1644
                  zw_b2(0) <= reg_0flag_i;
1645
               END IF;
1646
            WHEN s560 =>
1647
               IF (rdy_i = '1') THEN
1648
                  sig_PC <= X"00" & zw_b1;
1649
               END IF;
1650
            WHEN s561 =>
1651
               IF (rdy_i = '1') THEN
1652
                  sig_PC <= X"00" & zw_b1;
1653
               END IF;
1654
            WHEN s563 =>
1655
               IF (rdy_i = '1') THEN
1656
                  sig_PC <= X"00" & d_alu_i;
1657
                  zw_b1 <= d_i;
1658
               END IF;
1659
            WHEN s564 =>
1660
               IF (rdy_i = '1' AND
1661
                   zw_b2(0) = '0' and
1662
                   reg_F(3) = '0') THEN
1663
                  sig_PC <= adr_pc_i;
1664
 
1665
                  reg_F(7) <= zw_ALU(7);
1666
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
1667
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
1668
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
1669
                  (zw_ALU(0)));
1670
                  reg_F(0) <= zw_ALU(8);
1671
                  reg_sel_pc_in <= '0';
1672
                  reg_sel_pc_val <= "00";
1673
                  reg_sel_sp_in <= '0';
1674
                  reg_sel_sp_as <= '1';
1675
               ELSIF (rdy_i = '1' AND
1676
                      zw_b2(0) = '0' and
1677
                      reg_F(3) = '1') THEN
1678
                  sig_PC <= adr_pc_i;
1679
 
1680
                  reg_F(7) <= zw_ALU(7);
1681
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
1682
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
1683
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
1684
                  (zw_ALU(0)));
1685
                  reg_F(0) <= zw_ALU4(4);
1686
                  reg_sel_pc_in <= '0';
1687
                  reg_sel_pc_val <= "00";
1688
                  reg_sel_sp_in <= '0';
1689
                  reg_sel_sp_as <= '1';
1690
               ELSIF (rdy_i = '1') THEN
1691
                  sig_PC <= zw_b3 & zw_b1;
1692
               END IF;
1693
            WHEN s565 =>
1694
               IF (rdy_i = '1' and
1695
                   reg_F(3) = '0') THEN
1696
                  sig_PC <= adr_pc_i;
1697
 
1698
                  reg_F(7) <= zw_ALU(7);
1699
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
1700
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
1701
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
1702
                  (zw_ALU(0)));
1703
                  reg_F(0) <= zw_ALU(8);
1704
                  reg_sel_pc_in <= '0';
1705
                  reg_sel_pc_val <= "00";
1706
                  reg_sel_sp_in <= '0';
1707
                  reg_sel_sp_as <= '1';
1708
               ELSIF (rdy_i = '1' and
1709
                      reg_F(3) = '1') THEN
1710
                  sig_PC <= adr_pc_i;
1711
 
1712
                  reg_F(7) <= zw_ALU(7);
1713
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
1714
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
1715
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
1716
                  (zw_ALU(0)));
1717
                  reg_F(0) <= zw_ALU4(4);
1718
                  reg_sel_pc_in <= '0';
1719
                  reg_sel_pc_val <= "00";
1720
                  reg_sel_sp_in <= '0';
1721
                  reg_sel_sp_as <= '1';
1722
               END IF;
1723
            WHEN s566 =>
1724
               IF (rdy_i = '1') THEN
1725
                  sig_PC <= d_i & zw_b1;
1726
                  zw_b3 <= d_alu_i;
1727
               END IF;
1728
            WHEN s266 =>
1729
               IF (rdy_i = '1' and (
1730
                   (reg_F(0) = '1' and zw_REG_OP = X"90") or
1731
                   (reg_F(0) = '0' and zw_REG_OP = X"B0") or
1732
                   (reg_F(1) = '0' and zw_REG_OP = X"F0") or
1733
                   (reg_F(7) = '0' and zw_REG_OP = X"30") or
1734
                   (reg_F(1) = '1' and zw_REG_OP = X"D0") or
1735
                   (reg_F(7) = '1' and zw_REG_OP = X"10") or
1736
                   (reg_F(6) = '1' and zw_REG_OP = X"50") or
1737
                   (reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
1738
                  sig_PC <= adr_nxt_pc_i;
1739
                  reg_sel_pc_in <= '0';
1740
                  reg_sel_pc_val <= "00";
1741
                  reg_sel_sp_in <= '0';
1742
                  reg_sel_sp_as <= '1';
1743
               ELSIF (rdy_i = '1') THEN
1744
                  sig_PC <= adr_nxt_pc_i;
1745
                  reg_sel_pc_in <= '0';
1746
 
1747
                  reg_sel_pc_val <= "10";
1748
                  zw_b2 <= d_i;
1749
               END IF;
1750
            WHEN s301 =>
1751
               IF (rdy_i = '1' and
1752
                   zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
1753
                  sig_PC <= adr_nxt_pc_i;
1754
                  reg_sel_pc_in <= '0';
1755
                  reg_sel_pc_val <= "00";
1756
                  reg_sel_sp_in <= '0';
1757
                  reg_sel_sp_as <= '1';
1758
               ELSIF (rdy_i = '1') THEN
1759
                  sig_PC <= zw_b3 & adr_nxt_pc_i (7 downto 0);
1760
               END IF;
1761
            WHEN s302 =>
1762
               IF (rdy_i = '1') THEN
1763
                  sig_PC <= adr_pc_i;
1764
                  reg_sel_pc_in <= '0';
1765
                  reg_sel_pc_val <= "00";
1766
                  reg_sel_sp_in <= '0';
1767
                  reg_sel_sp_as <= '1';
1768
               END IF;
1769
            WHEN RES =>
1770
               reg_sel_pc_in <= '0';
1771
               reg_sel_pc_val <= "00";
1772
               sig_PC <= adr_nxt_pc_i;
1773
               reg_sel_pc_in <= '0';
1774
 
1775
               reg_sel_pc_val <= "00";
1776
               reg_sel_sp_in <= '0';
1777
               reg_sel_sp_as <= '1';
1778
            WHEN s511 =>
1779
               IF (rdy_i = '1' and
1780
                   zw_REG_OP = X"E5") THEN
1781
                  sig_PC <= X"00" & d_i;
1782
               ELSIF (rdy_i = '1' and
1783
                      zw_REG_OP = X"E9" and
1784
                      reg_F(3) = '0') THEN
1785
                  sig_PC <= adr_nxt_pc_i;
1786
 
1787
                  reg_F(7) <= zw_ALU(7);
1788
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
1789
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
1790
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
1791
                  (zw_ALU(0)));
1792
                  reg_F(0) <= zw_ALU(8);
1793
                  reg_sel_pc_in <= '0';
1794
                  reg_sel_pc_val <= "00";
1795
                  reg_sel_sp_in <= '0';
1796
                  reg_sel_sp_as <= '1';
1797
               ELSIF (rdy_i = '1' and
1798
                      zw_REG_OP = X"F5") THEN
1799
                  sig_PC <= X"00" & d_i;
1800
                  zw_b1 <= d_alu_i;
1801
               ELSIF (rdy_i = '1' and
1802
                      zw_REG_OP = X"ED") THEN
1803
                  sig_PC <= adr_nxt_pc_i;
1804
                  zw_b1 <= d_i;
1805
               ELSIF (rdy_i = '1' and
1806
                      zw_REG_OP = X"FD") THEN
1807
                  sig_PC <= adr_nxt_pc_i;
1808
                  zw_b1 <= d_alu_i;
1809
                  zw_b2(0) <= reg_0flag_i;
1810
               ELSIF (rdy_i = '1' and
1811
                      zw_REG_OP = X"F9") THEN
1812
                  sig_PC <= adr_nxt_pc_i;
1813
                  zw_b1 <= d_alu_i;
1814
                  zw_b2(0) <= reg_0flag_i;
1815
               ELSIF (rdy_i = '1' and
1816
                      zw_REG_OP = X"F1") THEN
1817
                  sig_PC <= X"00" & d_i;
1818
                  zw_b1 <= d_alu_i;
1819
               ELSIF (rdy_i = '1' and
1820
                      zw_REG_OP = X"E1") THEN
1821
                  sig_PC <= X"00" & d_i;
1822
                  zw_b1 <= d_alu_i;
1823
               ELSIF (rdy_i = '1' and
1824
                      zw_REG_OP = X"E9" and
1825
                      reg_F(3) = '1') THEN
1826
                  sig_PC <= adr_nxt_pc_i;
1827
 
1828
                  reg_F(7) <= zw_ALU(7);
1829
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
1830
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
1831
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
1832
                  (zw_ALU(0)));
1833
                  reg_F(0) <= zw_ALU2(4);
1834
                  reg_sel_pc_in <= '0';
1835
                  reg_sel_pc_val <= "00";
1836
                  reg_sel_sp_in <= '0';
1837
                  reg_sel_sp_as <= '1';
1838
               END IF;
1839
            WHEN s559 =>
1840
               IF (rdy_i = '1') THEN
1841
                  sig_PC <= d_i & zw_b1;
1842
               END IF;
1843
            WHEN s562 =>
1844
               IF (rdy_i = '1') THEN
1845
                  sig_PC <= d_i & zw_b1;
1846
                  zw_b3 <= d_alu_i;
1847
               END IF;
1848
            WHEN s567 =>
1849
               IF (rdy_i = '1') THEN
1850
                  sig_PC <= d_i & zw_b1;
1851
                  zw_b3 <= d_alu_i;
1852
               END IF;
1853
            WHEN s568 =>
1854
               IF (rdy_i = '1') THEN
1855
                  sig_PC <= X"00" & zw_b1;
1856
                  zw_b1 <= d_alu_i;
1857
                  zw_b2(0) <= reg_0flag_i;
1858
               END IF;
1859
            WHEN s569 =>
1860
               IF (rdy_i = '1') THEN
1861
                  sig_PC <= X"00" & zw_b1;
1862
               END IF;
1863
            WHEN s570 =>
1864
               IF (rdy_i = '1') THEN
1865
                  sig_PC <= X"00" & zw_b1;
1866
               END IF;
1867
            WHEN s571 =>
1868
               IF (rdy_i = '1') THEN
1869
                  sig_PC <= d_i & zw_b1;
1870
                  zw_b3 <= d_alu_i;
1871
               END IF;
1872
            WHEN s572 =>
1873
               IF (rdy_i = '1') THEN
1874
                  sig_PC <= X"00" & d_alu_i;
1875
                  zw_b1 <= d_i;
1876
               END IF;
1877
            WHEN s573 =>
1878
               IF (rdy_i = '1' AND
1879
                   zw_b2(0) = '0' and
1880
                   reg_F(3) = '0') THEN
1881
                  sig_PC <= adr_pc_i;
1882
 
1883
                  reg_F(7) <= zw_ALU(7);
1884
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
1885
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
1886
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
1887
                  (zw_ALU(0)));
1888
                  reg_F(0) <= zw_ALU(8);
1889
                  reg_sel_pc_in <= '0';
1890
                  reg_sel_pc_val <= "00";
1891
                  reg_sel_sp_in <= '0';
1892
                  reg_sel_sp_as <= '1';
1893
               ELSIF (rdy_i = '1' AND
1894
                      zw_b2(0) = '0' and
1895
                      reg_F(3) = '1') THEN
1896
                  sig_PC <= adr_pc_i;
1897
 
1898
                  reg_F(7) <= zw_ALU(7);
1899
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
1900
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
1901
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
1902
                  (zw_ALU(0)));
1903
                  reg_F(0) <= zw_ALU2(4);
1904
                  reg_sel_pc_in <= '0';
1905
                  reg_sel_pc_val <= "00";
1906
                  reg_sel_sp_in <= '0';
1907
                  reg_sel_sp_as <= '1';
1908
               ELSIF (rdy_i = '1') THEN
1909
                  sig_PC <= zw_b3 & zw_b1;
1910
               END IF;
1911
            WHEN s574 =>
1912
               IF (rdy_i = '1' and
1913
                   reg_F(3) = '0') THEN
1914
                  sig_PC <= adr_pc_i;
1915
 
1916
                  reg_F(7) <= zw_ALU(7);
1917
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
1918
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
1919
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
1920
                  (zw_ALU(0)));
1921
                  reg_F(0) <= zw_ALU(8);
1922
                  reg_sel_pc_in <= '0';
1923
                  reg_sel_pc_val <= "00";
1924
                  reg_sel_sp_in <= '0';
1925
                  reg_sel_sp_as <= '1';
1926
               ELSIF (rdy_i = '1' and
1927
                      reg_F(3) = '1') THEN
1928
                  sig_PC <= adr_pc_i;
1929
 
1930
                  reg_F(7) <= zw_ALU(7);
1931
                  reg_F(6) <= zw_b1(0) XOR zw_ALU(7);
1932
                  reg_F(1) <= NOT ((zw_ALU(7)) OR (zw_ALU(6)) OR (zw_ALU(5)) OR
1933
                  (zw_ALU(4)) OR (zw_ALU(3)) OR (zw_ALU(2)) OR (zw_ALU(1)) OR
1934
                  (zw_ALU(0)));
1935
                  reg_F(0) <= zw_ALU2(4);
1936
                  reg_sel_pc_in <= '0';
1937
                  reg_sel_pc_val <= "00";
1938
                  reg_sel_sp_in <= '0';
1939
                  reg_sel_sp_as <= '1';
1940
               END IF;
1941
            WHEN s548 =>
1942
               IF (rdy_i = '1') THEN
1943
                  sig_PC <= adr_sp_i;
1944
               END IF;
1945
            WHEN s551 =>
1946
               sig_PC <= adr_sp_i;
1947
            WHEN s552 =>
1948
               sig_PC <= adr_sp_i;
1949
            WHEN s575 =>
1950
               IF (rdy_i = '1') THEN
1951
                  sig_PC <= X"FFFF";
1952
                  reg_sel_pc_in <= '1';
1953
                  reg_sel_pc_val <= "11";
1954
                  reg_F(2) <= '1';
1955
                  zw_b1 <= d_i;
1956
               END IF;
1957
            WHEN s576 =>
1958
               IF (NMI_i = '1') THEN
1959
                  sig_PC <= X"FFFA";
1960
               ELSE
1961
                  sig_PC <= X"FFFE";
1962
               END IF;
1963
            WHEN s577 =>
1964
               IF (rdy_i = '1') THEN
1965
                  sig_PC <= d_i & zw_b1;
1966
                  reg_sel_pc_in <= '0';
1967
                  reg_sel_pc_val <= "00";
1968
                  reg_sel_sp_in <= '0';
1969
                  reg_sel_sp_as <= '1';
1970
               END IF;
1971
            WHEN s578 =>
1972
               IF (rdy_i = '1') THEN
1973
                  sig_PC <= X"FFFB";
1974
                  reg_sel_pc_in <= '1';
1975
                  reg_sel_pc_val <= "11";
1976
                  reg_F(2) <= '1';
1977
                  zw_b1 <= d_i;
1978
               END IF;
1979
            WHEN OTHERS =>
1980
               NULL;
1981
         END CASE;
1982
      END IF;
1983
   END PROCESS clocked_proc;
1984
 
1985
   -----------------------------------------------------------------
1986
   nextstate_proc : PROCESS (
1987
      adr_nxt_pc_i,
1988
      current_state,
1989
      d_i,
1990
      irq_n_i,
1991
      nmi_i,
1992
      rdy_i,
1993
      reg_F,
1994
      zw_REG_OP,
1995
      zw_b2,
1996
      zw_b3
1997
   )
1998
   -----------------------------------------------------------------
1999
   BEGIN
2000
      CASE current_state IS
2001
         WHEN FETCH =>
2002
            IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
2003
               next_state <= s548;
2004
            ELSIF ((irq_n_i = '0' and
2005
                   reg_F(2) = '0') AND (rdy_i = '1')) THEN
2006
               next_state <= s548;
2007
            ELSIF ((d_i = X"69" or
2008
                   d_i = X"65" or
2009
                   d_i = X"75" or
2010
                   d_i = X"6D" or
2011
                   d_i = X"7D" or
2012
                   d_i = X"79" or
2013
                   d_i = X"61" or
2014
                   d_i = X"71") AND (rdy_i = '1')) THEN
2015
               next_state <= s510;
2016
            ELSIF ((d_i = X"06" or
2017
                   d_i = X"16" or
2018
                   d_i = X"0E" or
2019
                   d_i = X"1E") AND (rdy_i = '1')) THEN
2020
               next_state <= s403;
2021
            ELSIF ((d_i = X"90" or
2022
                   d_i = X"B0" or
2023
                   d_i = X"F0" or
2024
                   d_i = X"30" or
2025
                   d_i = X"D0" or
2026
                   d_i = X"10" or
2027
                   d_i = X"50" or
2028
                   d_i = X"70") AND (rdy_i = '1')) THEN
2029
               next_state <= s266;
2030
            ELSIF ((d_i = X"24" or
2031
                   d_i = X"2C") AND (rdy_i = '1')) THEN
2032
               next_state <= s351;
2033
            ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
2034
               next_state <= s526;
2035
            ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
2036
               next_state <= s12;
2037
            ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
2038
               next_state <= s16;
2039
            ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
2040
               next_state <= s17;
2041
            ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
2042
               next_state <= s24;
2043
            ELSIF ((d_i = X"E0" or
2044
                   d_i = X"E4" or
2045
                   d_i = X"EC") AND (rdy_i = '1')) THEN
2046
               next_state <= s201;
2047
            ELSIF ((d_i = X"C0" or
2048
                   d_i = X"C4" or
2049
                   d_i = X"CC") AND (rdy_i = '1')) THEN
2050
               next_state <= s201;
2051
            ELSIF ((d_i = X"C6" or
2052
                   d_i = X"D6" or
2053
                   d_i = X"CE" or
2054
                   d_i = X"DE") AND (rdy_i = '1')) THEN
2055
               next_state <= s226;
2056
            ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
2057
               next_state <= s25;
2058
            ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
2059
               next_state <= s25;
2060
            ELSIF ((d_i = X"49" or
2061
                   d_i = X"45" or
2062
                   d_i = X"55" or
2063
                   d_i = X"4D" or
2064
                   d_i = X"5D" or
2065
                   d_i = X"59" or
2066
                   d_i = X"41" or
2067
                   d_i = X"51" or
2068
                   d_i = X"09" or
2069
                   d_i = X"05" or
2070
                   d_i = X"15" or
2071
                   d_i = X"0D" or
2072
                   d_i = X"1D" or
2073
                   d_i = X"19" or
2074
                   d_i = X"01" or
2075
                   d_i = X"11" or
2076
                   d_i = X"29" or
2077
                   d_i = X"25" or
2078
                   d_i = X"35" or
2079
                   d_i = X"2D" or
2080
                   d_i = X"3D" or
2081
                   d_i = X"39" or
2082
                   d_i = X"21" or
2083
                   d_i = X"31" or
2084
                   d_i = X"C9" or
2085
                   d_i = X"C5" or
2086
                   d_i = X"D5" or
2087
                   d_i = X"CD" or
2088
                   d_i = X"DD" or
2089
                   d_i = X"D9" or
2090
                   d_i = X"C1" or
2091
                   d_i = X"D1") AND (rdy_i = '1')) THEN
2092
               next_state <= s201;
2093
            ELSIF ((d_i = X"E6" or
2094
                   d_i = X"F6" or
2095
                   d_i = X"EE" or
2096
                   d_i = X"FE") AND (rdy_i = '1')) THEN
2097
               next_state <= s226;
2098
            ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
2099
               next_state <= s25;
2100
            ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
2101
               next_state <= s25;
2102
            ELSIF ((d_i = X"4C" or
2103
                   d_i = X"6C") AND (rdy_i = '1')) THEN
2104
               next_state <= s271;
2105
            ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
2106
               next_state <= s397;
2107
            ELSIF ((d_i = X"A9" or
2108
                   d_i = X"A5" or
2109
                   d_i = X"B5" or
2110
                   d_i = X"AD" or
2111
                   d_i = X"BD" or
2112
                   d_i = X"B9" or
2113
                   d_i = X"A1" or
2114
                   d_i = X"B1") AND (rdy_i = '1')) THEN
2115
               next_state <= s201;
2116
            ELSIF ((d_i = X"A2" or
2117
                   d_i = X"A6" or
2118
                   d_i = X"B6" or
2119
                   d_i = X"AE" or
2120
                   d_i = X"BE") AND (rdy_i = '1')) THEN
2121
               next_state <= s201;
2122
            ELSIF ((d_i = X"A0" or
2123
                   d_i = X"A4" or
2124
                   d_i = X"B4" or
2125
                   d_i = X"AC" or
2126
                   d_i = X"BC") AND (rdy_i = '1')) THEN
2127
               next_state <= s201;
2128
            ELSIF ((d_i = X"46" or
2129
                   d_i = X"56" or
2130
                   d_i = X"4E" or
2131
                   d_i = X"5E") AND (rdy_i = '1')) THEN
2132
               next_state <= s403;
2133
            ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
2134
               next_state <= s1;
2135
            ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
2136
               next_state <= s377;
2137
            ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
2138
               next_state <= s378;
2139
            ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
2140
               next_state <= s379;
2141
            ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
2142
               next_state <= s380;
2143
            ELSIF ((d_i = X"26" or
2144
                   d_i = X"36" or
2145
                   d_i = X"2E" or
2146
                   d_i = X"3E") AND (rdy_i = '1')) THEN
2147
               next_state <= s403;
2148
            ELSIF ((d_i = X"66" or
2149
                   d_i = X"76" or
2150
                   d_i = X"6E" or
2151
                   d_i = X"7E") AND (rdy_i = '1')) THEN
2152
               next_state <= s403;
2153
            ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
2154
               next_state <= s387;
2155
            ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
2156
               next_state <= s390;
2157
            ELSIF ((d_i = X"E9" or
2158
                   d_i = X"E5" or
2159
                   d_i = X"F5" or
2160
                   d_i = X"ED" or
2161
                   d_i = X"FD" or
2162
                   d_i = X"F9" or
2163
                   d_i = X"E1" or
2164
                   d_i = X"F1") AND (rdy_i = '1')) THEN
2165
               next_state <= s511;
2166
            ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
2167
               next_state <= s2;
2168
            ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
2169
               next_state <= s5;
2170
            ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
2171
               next_state <= s3;
2172
            ELSIF ((d_i = X"85" or
2173
                   d_i = X"95" or
2174
                   d_i = X"8D" or
2175
                   d_i = X"9D" or
2176
                   d_i = X"99" or
2177
                   d_i = X"81" or
2178
                   d_i = X"91") AND (rdy_i = '1')) THEN
2179
               next_state <= s177;
2180
            ELSIF ((d_i = X"86" or
2181
                   d_i = X"96" or
2182
                   d_i = X"8E") AND (rdy_i = '1')) THEN
2183
               next_state <= s177;
2184
            ELSIF ((d_i = X"84" or
2185
                   d_i = X"94" or
2186
                   d_i = X"8C") AND (rdy_i = '1')) THEN
2187
               next_state <= s177;
2188
            ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
2189
               next_state <= s4;
2190
            ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
2191
               next_state <= s404;
2192
            ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
2193
               next_state <= s556;
2194
            ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
2195
               next_state <= s557;
2196
            ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
2197
               next_state <= s579;
2198
            ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
2199
               next_state <= s4;
2200
            ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
2201
               next_state <= s4;
2202
            ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
2203
               next_state <= s4;
2204
            ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
2205
               next_state <= s4;
2206
            ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
2207
               next_state <= s4;
2208
            ELSIF (rdy_i = '1') THEN
2209
               next_state <= s1;
2210
            ELSE
2211
               next_state <= FETCH;
2212
            END IF;
2213
         WHEN s1 =>
2214
            IF (rdy_i = '1') THEN
2215
               next_state <= FETCH;
2216
            ELSE
2217
               next_state <= s1;
2218
            END IF;
2219
         WHEN s2 =>
2220
            IF (rdy_i = '1') THEN
2221
               next_state <= FETCH;
2222
            ELSE
2223
               next_state <= s2;
2224
            END IF;
2225
         WHEN s5 =>
2226
            IF (rdy_i = '1') THEN
2227
               next_state <= FETCH;
2228
            ELSE
2229
               next_state <= s5;
2230
            END IF;
2231
         WHEN s3 =>
2232
            IF (rdy_i = '1') THEN
2233
               next_state <= FETCH;
2234
            ELSE
2235
               next_state <= s3;
2236
            END IF;
2237
         WHEN s4 =>
2238
            IF (rdy_i = '1' and
2239
                zw_REG_OP = X"9A") THEN
2240
               next_state <= FETCH;
2241
            ELSIF (rdy_i = '1' and
2242
                   zw_REG_OP = X"BA") THEN
2243
               next_state <= FETCH;
2244
            ELSIF (rdy_i = '1') THEN
2245
               next_state <= FETCH;
2246
            ELSE
2247
               next_state <= s4;
2248
            END IF;
2249
         WHEN s12 =>
2250
            IF (rdy_i = '1') THEN
2251
               next_state <= FETCH;
2252
            ELSE
2253
               next_state <= s12;
2254
            END IF;
2255
         WHEN s16 =>
2256
            IF (rdy_i = '1') THEN
2257
               next_state <= FETCH;
2258
            ELSE
2259
               next_state <= s16;
2260
            END IF;
2261
         WHEN s17 =>
2262
            IF (rdy_i = '1') THEN
2263
               next_state <= FETCH;
2264
            ELSE
2265
               next_state <= s17;
2266
            END IF;
2267
         WHEN s24 =>
2268
            IF (rdy_i = '1') THEN
2269
               next_state <= FETCH;
2270
            ELSE
2271
               next_state <= s24;
2272
            END IF;
2273
         WHEN s25 =>
2274
            IF (rdy_i = '1') THEN
2275
               next_state <= FETCH;
2276
            ELSE
2277
               next_state <= s25;
2278
            END IF;
2279
         WHEN s271 =>
2280
            IF (rdy_i = '1' and
2281
                zw_REG_OP = X"4C") THEN
2282
               next_state <= s307;
2283
            ELSIF (rdy_i = '1' and
2284
                   zw_REG_OP = X"6C") THEN
2285
               next_state <= s273;
2286
            ELSE
2287
               next_state <= s271;
2288
            END IF;
2289
         WHEN s273 =>
2290
            IF (rdy_i = '1') THEN
2291
               next_state <= s304;
2292
            ELSE
2293
               next_state <= s273;
2294
            END IF;
2295
         WHEN s304 =>
2296
            IF (rdy_i = '1') THEN
2297
               next_state <= s307;
2298
            ELSE
2299
               next_state <= s304;
2300
            END IF;
2301
         WHEN s307 =>
2302
            IF (rdy_i = '1') THEN
2303
               next_state <= FETCH;
2304
            ELSE
2305
               next_state <= s307;
2306
            END IF;
2307
         WHEN s177 =>
2308
            IF (rdy_i = '1' and
2309
                (zw_REG_OP = X"85" OR
2310
                zw_REG_OP = X"86" OR
2311
                zw_REG_OP = X"84")) THEN
2312
               next_state <= s184;
2313
            ELSIF (rdy_i = '1' and
2314
                   (zw_REG_OP = X"95" OR
2315
                   zw_REG_OP = X"94")) THEN
2316
               next_state <= s185;
2317
            ELSIF (rdy_i = '1' and
2318
                   (zw_REG_OP = X"8D" OR
2319
                   zw_REG_OP = X"8E" OR
2320
                   zw_REG_OP = X"8C")) THEN
2321
               next_state <= s183;
2322
            ELSIF (rdy_i = '1' and
2323
                   zw_REG_OP = X"9D") THEN
2324
               next_state <= s182;
2325
            ELSIF (rdy_i = '1' and
2326
                   zw_REG_OP = X"99") THEN
2327
               next_state <= s180;
2328
            ELSIF (rdy_i = '1' and
2329
                   zw_REG_OP = X"91") THEN
2330
               next_state <= s181;
2331
            ELSIF (rdy_i = '1' and
2332
                   zw_REG_OP = X"81") THEN
2333
               next_state <= s186;
2334
            ELSIF (rdy_i = '1' and
2335
                   zw_REG_OP = X"96") THEN
2336
               next_state <= s185;
2337
            ELSE
2338
               next_state <= s177;
2339
            END IF;
2340
         WHEN s180 =>
2341
            IF (rdy_i = '1') THEN
2342
               next_state <= s191;
2343
            ELSE
2344
               next_state <= s180;
2345
            END IF;
2346
         WHEN s181 =>
2347
            IF (rdy_i = '1') THEN
2348
               next_state <= s189;
2349
            ELSE
2350
               next_state <= s181;
2351
            END IF;
2352
         WHEN s182 =>
2353
            IF (rdy_i = '1') THEN
2354
               next_state <= s191;
2355
            ELSE
2356
               next_state <= s182;
2357
            END IF;
2358
         WHEN s183 =>
2359
            IF (rdy_i = '1') THEN
2360
               next_state <= s187;
2361
            ELSE
2362
               next_state <= s183;
2363
            END IF;
2364
         WHEN s184 =>
2365
            next_state <= FETCH;
2366
         WHEN s185 =>
2367
            IF (rdy_i = '1') THEN
2368
               next_state <= s190;
2369
            ELSE
2370
               next_state <= s185;
2371
            END IF;
2372
         WHEN s186 =>
2373
            IF (rdy_i = '1') THEN
2374
               next_state <= s188;
2375
            ELSE
2376
               next_state <= s186;
2377
            END IF;
2378
         WHEN s187 =>
2379
            next_state <= FETCH;
2380
         WHEN s188 =>
2381
            IF (rdy_i = '1') THEN
2382
               next_state <= s192;
2383
            ELSE
2384
               next_state <= s188;
2385
            END IF;
2386
         WHEN s189 =>
2387
            IF (rdy_i = '1') THEN
2388
               next_state <= s191;
2389
            ELSE
2390
               next_state <= s189;
2391
            END IF;
2392
         WHEN s190 =>
2393
            next_state <= FETCH;
2394
         WHEN s191 =>
2395
            next_state <= s193;
2396
         WHEN s192 =>
2397
            next_state <= s193;
2398
         WHEN s193 =>
2399
            next_state <= FETCH;
2400
         WHEN s377 =>
2401
            IF (rdy_i = '1') THEN
2402
               next_state <= s381;
2403
            ELSE
2404
               next_state <= s377;
2405
            END IF;
2406
         WHEN s381 =>
2407
            next_state <= FETCH;
2408
         WHEN s378 =>
2409
            IF (rdy_i = '1') THEN
2410
               next_state <= s382;
2411
            ELSE
2412
               next_state <= s378;
2413
            END IF;
2414
         WHEN s382 =>
2415
            next_state <= FETCH;
2416
         WHEN s379 =>
2417
            IF (rdy_i = '1') THEN
2418
               next_state <= s383;
2419
            ELSE
2420
               next_state <= s379;
2421
            END IF;
2422
         WHEN s383 =>
2423
            IF (rdy_i = '1') THEN
2424
               next_state <= s384;
2425
            ELSE
2426
               next_state <= s383;
2427
            END IF;
2428
         WHEN s384 =>
2429
            IF (rdy_i = '1') THEN
2430
               next_state <= FETCH;
2431
            ELSE
2432
               next_state <= s384;
2433
            END IF;
2434
         WHEN s380 =>
2435
            IF (rdy_i = '1') THEN
2436
               next_state <= s385;
2437
            ELSE
2438
               next_state <= s380;
2439
            END IF;
2440
         WHEN s385 =>
2441
            IF (rdy_i = '1') THEN
2442
               next_state <= s386;
2443
            ELSE
2444
               next_state <= s385;
2445
            END IF;
2446
         WHEN s386 =>
2447
            IF (rdy_i = '1') THEN
2448
               next_state <= FETCH;
2449
            ELSE
2450
               next_state <= s386;
2451
            END IF;
2452
         WHEN s387 =>
2453
            IF (rdy_i = '1') THEN
2454
               next_state <= s388;
2455
            ELSE
2456
               next_state <= s387;
2457
            END IF;
2458
         WHEN s388 =>
2459
            IF (rdy_i = '1') THEN
2460
               next_state <= s389;
2461
            ELSE
2462
               next_state <= s388;
2463
            END IF;
2464
         WHEN s389 =>
2465
            IF (rdy_i = '1') THEN
2466
               next_state <= s391;
2467
            ELSE
2468
               next_state <= s389;
2469
            END IF;
2470
         WHEN s391 =>
2471
            IF (rdy_i = '1') THEN
2472
               next_state <= s392;
2473
            ELSE
2474
               next_state <= s391;
2475
            END IF;
2476
         WHEN s392 =>
2477
            IF (rdy_i = '1') THEN
2478
               next_state <= FETCH;
2479
            ELSE
2480
               next_state <= s392;
2481
            END IF;
2482
         WHEN s390 =>
2483
            IF (rdy_i = '1') THEN
2484
               next_state <= s393;
2485
            ELSE
2486
               next_state <= s390;
2487
            END IF;
2488
         WHEN s393 =>
2489
            IF (rdy_i = '1') THEN
2490
               next_state <= s394;
2491
            ELSE
2492
               next_state <= s393;
2493
            END IF;
2494
         WHEN s394 =>
2495
            IF (rdy_i = '1') THEN
2496
               next_state <= s395;
2497
            ELSE
2498
               next_state <= s394;
2499
            END IF;
2500
         WHEN s395 =>
2501
            IF (rdy_i = '1') THEN
2502
               next_state <= s396;
2503
            ELSE
2504
               next_state <= s395;
2505
            END IF;
2506
         WHEN s396 =>
2507
            IF (rdy_i = '1') THEN
2508
               next_state <= FETCH;
2509
            ELSE
2510
               next_state <= s396;
2511
            END IF;
2512
         WHEN s397 =>
2513
            IF (rdy_i = '1') THEN
2514
               next_state <= s398;
2515
            ELSE
2516
               next_state <= s397;
2517
            END IF;
2518
         WHEN s398 =>
2519
            IF (rdy_i = '1') THEN
2520
               next_state <= s399;
2521
            ELSE
2522
               next_state <= s398;
2523
            END IF;
2524
         WHEN s399 =>
2525
            next_state <= s400;
2526
         WHEN s400 =>
2527
            next_state <= s401;
2528
         WHEN s401 =>
2529
            IF (rdy_i = '1') THEN
2530
               next_state <= FETCH;
2531
            ELSE
2532
               next_state <= s401;
2533
            END IF;
2534
         WHEN s526 =>
2535
            IF (rdy_i = '1') THEN
2536
               next_state <= s527;
2537
            ELSE
2538
               next_state <= s526;
2539
            END IF;
2540
         WHEN s527 =>
2541
            next_state <= s528;
2542
         WHEN s528 =>
2543
            next_state <= s529;
2544
         WHEN s529 =>
2545
            next_state <= s531;
2546
         WHEN s530 =>
2547
            IF (rdy_i = '1') THEN
2548
               next_state <= FETCH;
2549
            ELSE
2550
               next_state <= s530;
2551
            END IF;
2552
         WHEN s531 =>
2553
            IF (rdy_i = '1') THEN
2554
               next_state <= s530;
2555
            ELSE
2556
               next_state <= s531;
2557
            END IF;
2558
         WHEN s544 =>
2559
            next_state <= s550;
2560
         WHEN s545 =>
2561
            next_state <= s546;
2562
         WHEN s546 =>
2563
            next_state <= s547;
2564
         WHEN s547 =>
2565
            IF (rdy_i = '1') THEN
2566
               next_state <= s549;
2567
            ELSE
2568
               next_state <= s547;
2569
            END IF;
2570
         WHEN s549 =>
2571
            IF (rdy_i = '1') THEN
2572
               next_state <= FETCH;
2573
            ELSE
2574
               next_state <= s549;
2575
            END IF;
2576
         WHEN s550 =>
2577
            next_state <= s545;
2578
         WHEN s404 =>
2579
            IF (rdy_i = '1') THEN
2580
               next_state <= FETCH;
2581
            ELSE
2582
               next_state <= s404;
2583
            END IF;
2584
         WHEN s556 =>
2585
            IF (rdy_i = '1') THEN
2586
               next_state <= FETCH;
2587
            ELSE
2588
               next_state <= s556;
2589
            END IF;
2590
         WHEN s557 =>
2591
            IF (rdy_i = '1') THEN
2592
               next_state <= FETCH;
2593
            ELSE
2594
               next_state <= s557;
2595
            END IF;
2596
         WHEN s579 =>
2597
            IF (rdy_i = '1') THEN
2598
               next_state <= FETCH;
2599
            ELSE
2600
               next_state <= s579;
2601
            END IF;
2602
         WHEN s201 =>
2603
            IF (rdy_i = '1' and
2604
                (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
2605
                zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
2606
                zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
2607
                zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
2608
               next_state <= s224;
2609
            ELSIF ((rdy_i = '1' and
2610
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
2611
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
2612
                   zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
2613
                   zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
2614
                   zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
2615
               next_state <= FETCH;
2616
            ELSIF ((rdy_i = '1' and
2617
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
2618
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
2619
                   zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
2620
                   zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
2621
                   zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
2622
               next_state <= FETCH;
2623
            ELSIF ((rdy_i = '1' and
2624
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
2625
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
2626
                   zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
2627
                   zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
2628
                    zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
2629
               next_state <= FETCH;
2630
            ELSIF ((rdy_i = '1' and
2631
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
2632
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
2633
                   zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
2634
                   zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
2635
                   zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
2636
                    zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
2637
                    zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
2638
                    zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
2639
               next_state <= FETCH;
2640
            ELSIF (rdy_i = '1' and
2641
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
2642
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
2643
               next_state <= FETCH;
2644
            ELSIF (rdy_i = '1' and
2645
                   (zw_REG_OP = X"B5" OR
2646
                   zw_REG_OP = X"B4" OR
2647
                   zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
2648
                   zw_REG_OP = X"35" OR
2649
                   zw_REG_OP = X"D5")) THEN
2650
               next_state <= s217;
2651
            ELSIF (rdy_i = '1' and
2652
                   (zw_REG_OP = X"AD" OR
2653
                   zw_REG_OP = X"AE" OR
2654
                   zw_REG_OP = X"AC" OR
2655
                   zw_REG_OP = X"4D" OR
2656
                   zw_REG_OP = X"0D" OR
2657
                   zw_REG_OP = X"2D" OR
2658
                   zw_REG_OP = X"CD" OR
2659
                   zw_REG_OP = X"EC" OR
2660
                   zw_REG_OP = X"CC")) THEN
2661
               next_state <= s202;
2662
            ELSIF (rdy_i = '1' and
2663
                   (zw_REG_OP = X"BD" OR
2664
                   zw_REG_OP = X"BC" OR
2665
                   zw_REG_OP = X"5D" OR
2666
                   zw_REG_OP = X"1D" OR
2667
                   zw_REG_OP = X"3D" OR
2668
                   zw_REG_OP = X"DD")) THEN
2669
               next_state <= s210;
2670
            ELSIF (rdy_i = '1' and
2671
                   (zw_REG_OP = X"B9" OR
2672
                   zw_REG_OP = X"BE" OR
2673
                   zw_REG_OP = X"59" OR
2674
                   zw_REG_OP = X"19" OR
2675
                   zw_REG_OP = X"39" OR
2676
                   zw_REG_OP = X"D9")) THEN
2677
               next_state <= s211;
2678
            ELSIF (rdy_i = '1' and
2679
                   (zw_REG_OP = X"B1" OR
2680
                   zw_REG_OP = X"51" OR
2681
                   zw_REG_OP = X"11" OR
2682
                   zw_REG_OP = X"31" OR
2683
                   zw_REG_OP = X"D1")) THEN
2684
               next_state <= s215;
2685
            ELSIF (rdy_i = '1' and
2686
                   (zw_REG_OP = X"A1" OR
2687
                   zw_REG_OP = X"41" OR
2688
                   zw_REG_OP = X"01" OR
2689
                   zw_REG_OP = X"21" OR
2690
                   zw_REG_OP = X"C1")) THEN
2691
               next_state <= s218;
2692
            ELSIF (rdy_i = '1' and
2693
                   zw_REG_OP = X"B6") THEN
2694
               next_state <= s217;
2695
            ELSE
2696
               next_state <= s201;
2697
            END IF;
2698
         WHEN s202 =>
2699
            IF (rdy_i = '1') THEN
2700
               next_state <= s224;
2701
            ELSE
2702
               next_state <= s202;
2703
            END IF;
2704
         WHEN s210 =>
2705
            IF (rdy_i = '1') THEN
2706
               next_state <= s225;
2707
            ELSE
2708
               next_state <= s210;
2709
            END IF;
2710
         WHEN s211 =>
2711
            IF (rdy_i = '1') THEN
2712
               next_state <= s225;
2713
            ELSE
2714
               next_state <= s211;
2715
            END IF;
2716
         WHEN s215 =>
2717
            IF (rdy_i = '1') THEN
2718
               next_state <= s223;
2719
            ELSE
2720
               next_state <= s215;
2721
            END IF;
2722
         WHEN s217 =>
2723
            IF (rdy_i = '1') THEN
2724
               next_state <= s224;
2725
            ELSE
2726
               next_state <= s217;
2727
            END IF;
2728
         WHEN s218 =>
2729
            IF (rdy_i = '1') THEN
2730
               next_state <= s222;
2731
            ELSE
2732
               next_state <= s218;
2733
            END IF;
2734
         WHEN s222 =>
2735
            IF (rdy_i = '1') THEN
2736
               next_state <= s202;
2737
            ELSE
2738
               next_state <= s222;
2739
            END IF;
2740
         WHEN s223 =>
2741
            IF (rdy_i = '1') THEN
2742
               next_state <= s225;
2743
            ELSE
2744
               next_state <= s223;
2745
            END IF;
2746
         WHEN s224 =>
2747
            IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
2748
                zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
2749
                zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
2750
                zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
2751
               next_state <= FETCH;
2752
            ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
2753
                   zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
2754
                   zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
2755
                   zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
2756
               next_state <= FETCH;
2757
            ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
2758
                   zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
2759
                   zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
2760
                    zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
2761
               next_state <= FETCH;
2762
            ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
2763
                   zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
2764
                   zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
2765
                   zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
2766
                    zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
2767
                    zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
2768
                    zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
2769
               next_state <= FETCH;
2770
            ELSIF (rdy_i = '1') THEN
2771
               next_state <= FETCH;
2772
            ELSE
2773
               next_state <= s224;
2774
            END IF;
2775
         WHEN s225 =>
2776
            IF ((rdy_i = '1' AND
2777
                zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
2778
                zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
2779
                zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
2780
                zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
2781
               next_state <= FETCH;
2782
            ELSIF ((rdy_i = '1' AND
2783
                   zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
2784
                   zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
2785
                   zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
2786
                   zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
2787
               next_state <= FETCH;
2788
            ELSIF ((rdy_i = '1' AND
2789
                   zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
2790
                   zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
2791
                   zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
2792
                    zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
2793
               next_state <= FETCH;
2794
            ELSIF ((rdy_i = '1' AND
2795
                   zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
2796
                   zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
2797
                   zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
2798
                   zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
2799
                    zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
2800
                    zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
2801
                    zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
2802
               next_state <= FETCH;
2803
            ELSIF (rdy_i = '1' AND
2804
                   zw_b2(0) = '0') THEN
2805
               next_state <= FETCH;
2806
            ELSIF (rdy_i = '1') THEN
2807
               next_state <= s224;
2808
            ELSE
2809
               next_state <= s225;
2810
            END IF;
2811
         WHEN s226 =>
2812
            IF (rdy_i = '1' and
2813
                (zw_REG_OP = X"C6" OR
2814
                zw_REG_OP = X"E6")) THEN
2815
               next_state <= s343;
2816
            ELSIF (rdy_i = '1' and
2817
                   (zw_REG_OP = X"D6" OR
2818
                   zw_REG_OP = X"F6")) THEN
2819
               next_state <= s247;
2820
            ELSIF (rdy_i = '1' and
2821
                   (zw_REG_OP = X"CE" OR
2822
                   zw_REG_OP = X"EE")) THEN
2823
               next_state <= s243;
2824
            ELSIF (rdy_i = '1' and
2825
                   (zw_REG_OP = X"DE" OR
2826
                   zw_REG_OP = X"FE")) THEN
2827
               next_state <= s244;
2828
            ELSE
2829
               next_state <= s226;
2830
            END IF;
2831
         WHEN s243 =>
2832
            IF (rdy_i = '1') THEN
2833
               next_state <= s343;
2834
            ELSE
2835
               next_state <= s243;
2836
            END IF;
2837
         WHEN s244 =>
2838
            IF (rdy_i = '1') THEN
2839
               next_state <= s344;
2840
            ELSE
2841
               next_state <= s244;
2842
            END IF;
2843
         WHEN s247 =>
2844
            IF (rdy_i = '1') THEN
2845
               next_state <= s343;
2846
            ELSE
2847
               next_state <= s247;
2848
            END IF;
2849
         WHEN s344 =>
2850
            IF (rdy_i = '1') THEN
2851
               next_state <= s343;
2852
            ELSE
2853
               next_state <= s344;
2854
            END IF;
2855
         WHEN s343 =>
2856
            IF (rdy_i = '1') THEN
2857
               next_state <= s250;
2858
            ELSE
2859
               next_state <= s343;
2860
            END IF;
2861
         WHEN s250 =>
2862
            IF (rdy_i = '1') THEN
2863
               next_state <= s251;
2864
            ELSE
2865
               next_state <= s250;
2866
            END IF;
2867
         WHEN s251 =>
2868
            next_state <= FETCH;
2869
         WHEN s351 =>
2870
            IF (rdy_i = '1' and
2871
                zw_REG_OP = X"24") THEN
2872
               next_state <= s361;
2873
            ELSIF (rdy_i = '1' and
2874
                   zw_REG_OP = X"2C") THEN
2875
               next_state <= s360;
2876
            ELSE
2877
               next_state <= s351;
2878
            END IF;
2879
         WHEN s361 =>
2880
            IF (rdy_i = '1') THEN
2881
               next_state <= FETCH;
2882
            ELSE
2883
               next_state <= s361;
2884
            END IF;
2885
         WHEN s360 =>
2886
            IF (rdy_i = '1') THEN
2887
               next_state <= s361;
2888
            ELSE
2889
               next_state <= s360;
2890
            END IF;
2891
         WHEN s403 =>
2892
            IF (rdy_i = '1' and
2893
                (zw_REG_OP = X"1E" or
2894
                zw_REG_OP = X"7E" or
2895
                zw_REG_OP = X"3E" or
2896
                zw_REG_OP = X"5E")) THEN
2897
               next_state <= s407;
2898
            ELSIF (rdy_i = '1' and
2899
                   (zw_REG_OP = X"06" or
2900
                   zw_REG_OP = X"66" or
2901
                   zw_REG_OP = X"26" or
2902
                   zw_REG_OP = X"46")) THEN
2903
               next_state <= s413;
2904
            ELSIF (rdy_i = '1' and
2905
                   (zw_REG_OP = X"16" or
2906
                   zw_REG_OP = X"76" or
2907
                   zw_REG_OP = X"36" or
2908
                   zw_REG_OP = X"56")) THEN
2909
               next_state <= s409;
2910
            ELSIF (rdy_i = '1' and
2911
                   (zw_REG_OP = X"0E" or
2912
                   zw_REG_OP = X"6E" or
2913
                   zw_REG_OP = X"2E" or
2914
                   zw_REG_OP = X"4E")) THEN
2915
               next_state <= s406;
2916
            ELSE
2917
               next_state <= s403;
2918
            END IF;
2919
         WHEN s406 =>
2920
            IF (rdy_i = '1') THEN
2921
               next_state <= s413;
2922
            ELSE
2923
               next_state <= s406;
2924
            END IF;
2925
         WHEN s407 =>
2926
            IF (rdy_i = '1') THEN
2927
               next_state <= s412;
2928
            ELSE
2929
               next_state <= s407;
2930
            END IF;
2931
         WHEN s409 =>
2932
            IF (rdy_i = '1') THEN
2933
               next_state <= s413;
2934
            ELSE
2935
               next_state <= s409;
2936
            END IF;
2937
         WHEN s412 =>
2938
            IF (rdy_i = '1') THEN
2939
               next_state <= s413;
2940
            ELSE
2941
               next_state <= s412;
2942
            END IF;
2943
         WHEN s413 =>
2944
            IF (rdy_i = '1') THEN
2945
               next_state <= s416;
2946
            ELSE
2947
               next_state <= s413;
2948
            END IF;
2949
         WHEN s416 =>
2950
            IF (rdy_i = '1' and
2951
                (zw_REG_OP = X"06" or
2952
                zw_REG_OP = X"16" or
2953
                zw_REG_OP = X"0E" or
2954
                zw_REG_OP = X"1E")) THEN
2955
               next_state <= s418;
2956
            ELSIF (rdy_i = '1' and
2957
                   (zw_REG_OP = X"46" or
2958
                   zw_REG_OP = X"56" or
2959
                   zw_REG_OP = X"4E" or
2960
                   zw_REG_OP = X"5E")) THEN
2961
               next_state <= s418;
2962
            ELSIF (rdy_i = '1' and
2963
                   (zw_REG_OP = X"26" or
2964
                   zw_REG_OP = X"36" or
2965
                   zw_REG_OP = X"2E" or
2966
                   zw_REG_OP = X"3E")) THEN
2967
               next_state <= s418;
2968
            ELSIF (rdy_i = '1' and
2969
                   (zw_REG_OP = X"66" or
2970
                   zw_REG_OP = X"76" or
2971
                   zw_REG_OP = X"6E" or
2972
                   zw_REG_OP = X"7E")) THEN
2973
               next_state <= s418;
2974
            ELSE
2975
               next_state <= s416;
2976
            END IF;
2977
         WHEN s418 =>
2978
            next_state <= FETCH;
2979
         WHEN s510 =>
2980
            IF (rdy_i = '1' and
2981
                zw_REG_OP = X"65") THEN
2982
               next_state <= s565;
2983
            ELSIF (rdy_i = '1' and
2984
                   zw_REG_OP = X"69" and
2985
                   reg_F(3) = '0') THEN
2986
               next_state <= FETCH;
2987
            ELSIF (rdy_i = '1' and
2988
                   zw_REG_OP = X"75") THEN
2989
               next_state <= s560;
2990
            ELSIF (rdy_i = '1' and
2991
                   zw_REG_OP = X"6D") THEN
2992
               next_state <= s553;
2993
            ELSIF (rdy_i = '1' and
2994
                   zw_REG_OP = X"7D") THEN
2995
               next_state <= s555;
2996
            ELSIF (rdy_i = '1' and
2997
                   zw_REG_OP = X"79") THEN
2998
               next_state <= s555;
2999
            ELSIF (rdy_i = '1' and
3000
                   zw_REG_OP = X"71") THEN
3001
               next_state <= s558;
3002
            ELSIF (rdy_i = '1' and
3003
                   zw_REG_OP = X"61") THEN
3004
               next_state <= s561;
3005
            ELSIF (rdy_i = '1' and
3006
                   zw_REG_OP = X"69" and
3007
                   reg_F(3) = '1') THEN
3008
               next_state <= FETCH;
3009
            ELSE
3010
               next_state <= s510;
3011
            END IF;
3012
         WHEN s553 =>
3013
            IF (rdy_i = '1') THEN
3014
               next_state <= s565;
3015
            ELSE
3016
               next_state <= s553;
3017
            END IF;
3018
         WHEN s555 =>
3019
            IF (rdy_i = '1') THEN
3020
               next_state <= s564;
3021
            ELSE
3022
               next_state <= s555;
3023
            END IF;
3024
         WHEN s558 =>
3025
            IF (rdy_i = '1') THEN
3026
               next_state <= s566;
3027
            ELSE
3028
               next_state <= s558;
3029
            END IF;
3030
         WHEN s560 =>
3031
            IF (rdy_i = '1') THEN
3032
               next_state <= s565;
3033
            ELSE
3034
               next_state <= s560;
3035
            END IF;
3036
         WHEN s561 =>
3037
            IF (rdy_i = '1') THEN
3038
               next_state <= s563;
3039
            ELSE
3040
               next_state <= s561;
3041
            END IF;
3042
         WHEN s563 =>
3043
            IF (rdy_i = '1') THEN
3044
               next_state <= s553;
3045
            ELSE
3046
               next_state <= s563;
3047
            END IF;
3048
         WHEN s564 =>
3049
            IF (rdy_i = '1' AND
3050
                zw_b2(0) = '0' and
3051
                reg_F(3) = '0') THEN
3052
               next_state <= FETCH;
3053
            ELSIF (rdy_i = '1' AND
3054
                   zw_b2(0) = '0' and
3055
                   reg_F(3) = '1') THEN
3056
               next_state <= FETCH;
3057
            ELSIF (rdy_i = '1') THEN
3058
               next_state <= s565;
3059
            ELSE
3060
               next_state <= s564;
3061
            END IF;
3062
         WHEN s565 =>
3063
            IF (rdy_i = '1' and
3064
                reg_F(3) = '0') THEN
3065
               next_state <= FETCH;
3066
            ELSIF (rdy_i = '1' and
3067
                   reg_F(3) = '1') THEN
3068
               next_state <= FETCH;
3069
            ELSE
3070
               next_state <= s565;
3071
            END IF;
3072
         WHEN s566 =>
3073
            IF (rdy_i = '1') THEN
3074
               next_state <= s564;
3075
            ELSE
3076
               next_state <= s566;
3077
            END IF;
3078
         WHEN s266 =>
3079
            IF (rdy_i = '1' and (
3080
                (reg_F(0) = '1' and zw_REG_OP = X"90") or
3081
                (reg_F(0) = '0' and zw_REG_OP = X"B0") or
3082
                (reg_F(1) = '0' and zw_REG_OP = X"F0") or
3083
                (reg_F(7) = '0' and zw_REG_OP = X"30") or
3084
                (reg_F(1) = '1' and zw_REG_OP = X"D0") or
3085
                (reg_F(7) = '1' and zw_REG_OP = X"10") or
3086
                (reg_F(6) = '1' and zw_REG_OP = X"50") or
3087
                (reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
3088
               next_state <= FETCH;
3089
            ELSIF (rdy_i = '1') THEN
3090
               next_state <= s301;
3091
            ELSE
3092
               next_state <= s266;
3093
            END IF;
3094
         WHEN s301 =>
3095
            IF (rdy_i = '1' and
3096
                zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
3097
               next_state <= FETCH;
3098
            ELSIF (rdy_i = '1') THEN
3099
               next_state <= s302;
3100
            ELSE
3101
               next_state <= s301;
3102
            END IF;
3103
         WHEN s302 =>
3104
            IF (rdy_i = '1') THEN
3105
               next_state <= FETCH;
3106
            ELSE
3107
               next_state <= s302;
3108
            END IF;
3109
         WHEN RES =>
3110
            next_state <= s544;
3111
         WHEN s511 =>
3112
            IF (rdy_i = '1' and
3113
                zw_REG_OP = X"E5") THEN
3114
               next_state <= s574;
3115
            ELSIF (rdy_i = '1' and
3116
                   zw_REG_OP = X"E9" and
3117
                   reg_F(3) = '0') THEN
3118
               next_state <= FETCH;
3119
            ELSIF (rdy_i = '1' and
3120
                   zw_REG_OP = X"F5") THEN
3121
               next_state <= s569;
3122
            ELSIF (rdy_i = '1' and
3123
                   zw_REG_OP = X"ED") THEN
3124
               next_state <= s559;
3125
            ELSIF (rdy_i = '1' and
3126
                   zw_REG_OP = X"FD") THEN
3127
               next_state <= s562;
3128
            ELSIF (rdy_i = '1' and
3129
                   zw_REG_OP = X"F9") THEN
3130
               next_state <= s567;
3131
            ELSIF (rdy_i = '1' and
3132
                   zw_REG_OP = X"F1") THEN
3133
               next_state <= s568;
3134
            ELSIF (rdy_i = '1' and
3135
                   zw_REG_OP = X"E1") THEN
3136
               next_state <= s570;
3137
            ELSIF (rdy_i = '1' and
3138
                   zw_REG_OP = X"E9" and
3139
                   reg_F(3) = '1') THEN
3140
               next_state <= FETCH;
3141
            ELSE
3142
               next_state <= s511;
3143
            END IF;
3144
         WHEN s559 =>
3145
            IF (rdy_i = '1') THEN
3146
               next_state <= s574;
3147
            ELSE
3148
               next_state <= s559;
3149
            END IF;
3150
         WHEN s562 =>
3151
            IF (rdy_i = '1') THEN
3152
               next_state <= s573;
3153
            ELSE
3154
               next_state <= s562;
3155
            END IF;
3156
         WHEN s567 =>
3157
            IF (rdy_i = '1') THEN
3158
               next_state <= s573;
3159
            ELSE
3160
               next_state <= s567;
3161
            END IF;
3162
         WHEN s568 =>
3163
            IF (rdy_i = '1') THEN
3164
               next_state <= s571;
3165
            ELSE
3166
               next_state <= s568;
3167
            END IF;
3168
         WHEN s569 =>
3169
            IF (rdy_i = '1') THEN
3170
               next_state <= s574;
3171
            ELSE
3172
               next_state <= s569;
3173
            END IF;
3174
         WHEN s570 =>
3175
            IF (rdy_i = '1') THEN
3176
               next_state <= s572;
3177
            ELSE
3178
               next_state <= s570;
3179
            END IF;
3180
         WHEN s571 =>
3181
            IF (rdy_i = '1') THEN
3182
               next_state <= s573;
3183
            ELSE
3184
               next_state <= s571;
3185
            END IF;
3186
         WHEN s572 =>
3187
            IF (rdy_i = '1') THEN
3188
               next_state <= s559;
3189
            ELSE
3190
               next_state <= s572;
3191
            END IF;
3192
         WHEN s573 =>
3193
            IF (rdy_i = '1' AND
3194
                zw_b2(0) = '0' and
3195
                reg_F(3) = '0') THEN
3196
               next_state <= FETCH;
3197
            ELSIF (rdy_i = '1' AND
3198
                   zw_b2(0) = '0' and
3199
                   reg_F(3) = '1') THEN
3200
               next_state <= FETCH;
3201
            ELSIF (rdy_i = '1') THEN
3202
               next_state <= s574;
3203
            ELSE
3204
               next_state <= s573;
3205
            END IF;
3206
         WHEN s574 =>
3207
            IF (rdy_i = '1' and
3208
                reg_F(3) = '0') THEN
3209
               next_state <= FETCH;
3210
            ELSIF (rdy_i = '1' and
3211
                   reg_F(3) = '1') THEN
3212
               next_state <= FETCH;
3213
            ELSE
3214
               next_state <= s574;
3215
            END IF;
3216
         WHEN s548 =>
3217
            IF (rdy_i = '1') THEN
3218
               next_state <= s551;
3219
            ELSE
3220
               next_state <= s548;
3221
            END IF;
3222
         WHEN s551 =>
3223
            next_state <= s552;
3224
         WHEN s552 =>
3225
            next_state <= s576;
3226
         WHEN s575 =>
3227
            IF (rdy_i = '1') THEN
3228
               next_state <= s577;
3229
            ELSE
3230
               next_state <= s575;
3231
            END IF;
3232
         WHEN s576 =>
3233
            IF (NMI_i = '1') THEN
3234
               next_state <= s578;
3235
            ELSE
3236
               next_state <= s575;
3237
            END IF;
3238
         WHEN s577 =>
3239
            IF (rdy_i = '1') THEN
3240
               next_state <= FETCH;
3241
            ELSE
3242
               next_state <= s577;
3243
            END IF;
3244
         WHEN s578 =>
3245
            IF (rdy_i = '1') THEN
3246
               next_state <= s577;
3247
            ELSE
3248
               next_state <= s578;
3249
            END IF;
3250
         WHEN OTHERS =>
3251
            next_state <= RES;
3252
      END CASE;
3253
   END PROCESS nextstate_proc;
3254
 
3255
   -----------------------------------------------------------------
3256
   output_proc : PROCESS (
3257
      adr_nxt_pc_i,
3258
      adr_pc_i,
3259
      adr_sp_i,
3260
      current_state,
3261
      d_alu_i,
3262
      d_i,
3263
      d_regs_out_i,
3264
      irq_n_i,
3265
      nmi_i,
3266
      q_a_i,
3267
      q_x_i,
3268
      q_y_i,
3269
      rdy_i,
3270
      reg_F,
3271
      reg_sel_pc_in,
3272
      reg_sel_pc_val,
3273
      reg_sel_rb_in,
3274
      reg_sel_rb_out,
3275
      reg_sel_reg,
3276
      reg_sel_sp_as,
3277
      reg_sel_sp_in,
3278
      sig_PC,
3279
      zw_ALU,
3280
      zw_ALU1,
3281
      zw_ALU2,
3282
      zw_ALU3,
3283
      zw_ALU4,
3284
      zw_ALU5,
3285
      zw_ALU6,
3286
      zw_REG_OP,
3287
      zw_b1,
3288
      zw_b2,
3289
      zw_b3,
3290
      zw_b4
3291
   )
3292
   -----------------------------------------------------------------
3293
   BEGIN
3294
      -- Default Assignment
3295
      a_o <= sig_PC;
3296
      adr_o <= X"0000";
3297
      ch_a_o <= X"00";
3298
      ch_b_o <= X"00";
3299
      d_regs_in_o <= X"00";
3300
      ld_o <= "00";
3301
      ld_pc_o <= '0';
3302
      ld_sp_o <= '0';
3303
      load_regs_o <= '0';
3304
      offset_o <= X"0000";
3305
      rst_nmi_o <= '0';
3306
      sel_pc_in_o <= reg_sel_pc_in;
3307
      sel_pc_val_o <= reg_sel_pc_val;
3308
      sel_rb_in_o <= reg_sel_rb_in;
3309
      sel_rb_out_o <= reg_sel_rb_out;
3310
      sel_reg_o <= reg_sel_reg;
3311
      sel_sp_as_o <= reg_sel_sp_as;
3312
      sel_sp_in_o <= reg_sel_sp_in;
3313
      -- Default Assignment To Internals
3314
      sig_D_OUT <= X"00";
3315
      sig_RD <= '1';
3316
      sig_RWn <= '1';
3317
      sig_SYNC <= '0';
3318
      sig_WR <= '0';
3319
      zw_ALU <= '0' & X"00";
3320
      zw_ALU1 <= '0' & X"0";
3321
      zw_ALU2 <= '0' & X"0";
3322
      zw_ALU3 <= '0' & X"0";
3323
      zw_ALU4 <= '0' & X"0";
3324
      zw_ALU5 <= X"0";
3325
      zw_ALU6 <= X"0";
3326
 
3327
      -- Combined Actions
3328
      CASE current_state IS
3329
         WHEN FETCH =>
3330
            sig_RWn <= '1';
3331
            sig_RD <= '1';
3332
            sig_SYNC <= NOT (rdy_i);
3333
            IF ((nmi_i = '1') AND (rdy_i = '1')) THEN
3334
            ELSIF ((irq_n_i = '0' and
3335
                   reg_F(2) = '0') AND (rdy_i = '1')) THEN
3336
            ELSIF ((d_i = X"69" or
3337
                   d_i = X"65" or
3338
                   d_i = X"75" or
3339
                   d_i = X"6D" or
3340
                   d_i = X"7D" or
3341
                   d_i = X"79" or
3342
                   d_i = X"61" or
3343
                   d_i = X"71") AND (rdy_i = '1')) THEN
3344
               ld_o <= "11";
3345
               ld_pc_o <= '1';
3346
            ELSIF ((d_i = X"06" or
3347
                   d_i = X"16" or
3348
                   d_i = X"0E" or
3349
                   d_i = X"1E") AND (rdy_i = '1')) THEN
3350
               ld_o <= "11";
3351
               ld_pc_o <= '1';
3352
            ELSIF ((d_i = X"90" or
3353
                   d_i = X"B0" or
3354
                   d_i = X"F0" or
3355
                   d_i = X"30" or
3356
                   d_i = X"D0" or
3357
                   d_i = X"10" or
3358
                   d_i = X"50" or
3359
                   d_i = X"70") AND (rdy_i = '1')) THEN
3360
               ld_o <= "11";
3361
               ld_pc_o <= '1';
3362
            ELSIF ((d_i = X"24" or
3363
                   d_i = X"2C") AND (rdy_i = '1')) THEN
3364
               ld_o <= "11";
3365
               ld_pc_o <= '1';
3366
            ELSIF ((d_i = X"00") AND (rdy_i = '1')) THEN
3367
               ld_o <= "11";
3368
               ld_pc_o <= '1';
3369
            ELSIF ((d_i = X"18") AND (rdy_i = '1')) THEN
3370
               ld_o <= "11";
3371
               ld_pc_o <= '1';
3372
            ELSIF ((d_i = X"D8") AND (rdy_i = '1')) THEN
3373
               ld_o <= "11";
3374
               ld_pc_o <= '1';
3375
            ELSIF ((d_i = X"58") AND (rdy_i = '1')) THEN
3376
               ld_o <= "11";
3377
               ld_pc_o <= '1';
3378
            ELSIF ((d_i = X"B8") AND (rdy_i = '1')) THEN
3379
               ld_o <= "11";
3380
               ld_pc_o <= '1';
3381
            ELSIF ((d_i = X"E0" or
3382
                   d_i = X"E4" or
3383
                   d_i = X"EC") AND (rdy_i = '1')) THEN
3384
               ld_o <= "11";
3385
               ld_pc_o <= '1';
3386
            ELSIF ((d_i = X"C0" or
3387
                   d_i = X"C4" or
3388
                   d_i = X"CC") AND (rdy_i = '1')) THEN
3389
               ld_o <= "11";
3390
               ld_pc_o <= '1';
3391
            ELSIF ((d_i = X"C6" or
3392
                   d_i = X"D6" or
3393
                   d_i = X"CE" or
3394
                   d_i = X"DE") AND (rdy_i = '1')) THEN
3395
               ld_o <= "11";
3396
               ld_pc_o <= '1';
3397
            ELSIF ((d_i = X"CA") AND (rdy_i = '1')) THEN
3398
               ld_o <= "11";
3399
               ld_pc_o <= '1';
3400
            ELSIF ((d_i = X"88") AND (rdy_i = '1')) THEN
3401
               ld_o <= "11";
3402
               ld_pc_o <= '1';
3403
            ELSIF ((d_i = X"49" or
3404
                   d_i = X"45" or
3405
                   d_i = X"55" or
3406
                   d_i = X"4D" or
3407
                   d_i = X"5D" or
3408
                   d_i = X"59" or
3409
                   d_i = X"41" or
3410
                   d_i = X"51" or
3411
                   d_i = X"09" or
3412
                   d_i = X"05" or
3413
                   d_i = X"15" or
3414
                   d_i = X"0D" or
3415
                   d_i = X"1D" or
3416
                   d_i = X"19" or
3417
                   d_i = X"01" or
3418
                   d_i = X"11" or
3419
                   d_i = X"29" or
3420
                   d_i = X"25" or
3421
                   d_i = X"35" or
3422
                   d_i = X"2D" or
3423
                   d_i = X"3D" or
3424
                   d_i = X"39" or
3425
                   d_i = X"21" or
3426
                   d_i = X"31" or
3427
                   d_i = X"C9" or
3428
                   d_i = X"C5" or
3429
                   d_i = X"D5" or
3430
                   d_i = X"CD" or
3431
                   d_i = X"DD" or
3432
                   d_i = X"D9" or
3433
                   d_i = X"C1" or
3434
                   d_i = X"D1") AND (rdy_i = '1')) THEN
3435
               ld_o <= "11";
3436
               ld_pc_o <= '1';
3437
            ELSIF ((d_i = X"E6" or
3438
                   d_i = X"F6" or
3439
                   d_i = X"EE" or
3440
                   d_i = X"FE") AND (rdy_i = '1')) THEN
3441
               ld_o <= "11";
3442
               ld_pc_o <= '1';
3443
            ELSIF ((d_i = X"E8") AND (rdy_i = '1')) THEN
3444
               ld_o <= "11";
3445
               ld_pc_o <= '1';
3446
            ELSIF ((d_i = X"C8") AND (rdy_i = '1')) THEN
3447
               ld_o <= "11";
3448
               ld_pc_o <= '1';
3449
            ELSIF ((d_i = X"4C" or
3450
                   d_i = X"6C") AND (rdy_i = '1')) THEN
3451
               ld_o <= "11";
3452
               ld_pc_o <= '1';
3453
            ELSIF ((d_i = X"20") AND (rdy_i = '1')) THEN
3454
               ld_o <= "11";
3455
               ld_pc_o <= '1';
3456
            ELSIF ((d_i = X"A9" or
3457
                   d_i = X"A5" or
3458
                   d_i = X"B5" or
3459
                   d_i = X"AD" or
3460
                   d_i = X"BD" or
3461
                   d_i = X"B9" or
3462
                   d_i = X"A1" or
3463
                   d_i = X"B1") AND (rdy_i = '1')) THEN
3464
               ld_o <= "11";
3465
               ld_pc_o <= '1';
3466
            ELSIF ((d_i = X"A2" or
3467
                   d_i = X"A6" or
3468
                   d_i = X"B6" or
3469
                   d_i = X"AE" or
3470
                   d_i = X"BE") AND (rdy_i = '1')) THEN
3471
               ld_o <= "11";
3472
               ld_pc_o <= '1';
3473
            ELSIF ((d_i = X"A0" or
3474
                   d_i = X"A4" or
3475
                   d_i = X"B4" or
3476
                   d_i = X"AC" or
3477
                   d_i = X"BC") AND (rdy_i = '1')) THEN
3478
               ld_o <= "11";
3479
               ld_pc_o <= '1';
3480
            ELSIF ((d_i = X"46" or
3481
                   d_i = X"56" or
3482
                   d_i = X"4E" or
3483
                   d_i = X"5E") AND (rdy_i = '1')) THEN
3484
               ld_o <= "11";
3485
               ld_pc_o <= '1';
3486
            ELSIF ((d_i = X"EA") AND (rdy_i = '1')) THEN
3487
               ld_o <= "11";
3488
               ld_pc_o <= '1';
3489
            ELSIF ((d_i = X"48") AND (rdy_i = '1')) THEN
3490
               ld_o <= "11";
3491
               ld_pc_o <= '1';
3492
            ELSIF ((d_i = X"08") AND (rdy_i = '1')) THEN
3493
               ld_o <= "11";
3494
               ld_pc_o <= '1';
3495
            ELSIF ((d_i = X"68") AND (rdy_i = '1')) THEN
3496
               ld_o <= "11";
3497
               ld_pc_o <= '1';
3498
            ELSIF ((d_i = X"28") AND (rdy_i = '1')) THEN
3499
               ld_o <= "11";
3500
               ld_pc_o <= '1';
3501
            ELSIF ((d_i = X"26" or
3502
                   d_i = X"36" or
3503
                   d_i = X"2E" or
3504
                   d_i = X"3E") AND (rdy_i = '1')) THEN
3505
               ld_o <= "11";
3506
               ld_pc_o <= '1';
3507
            ELSIF ((d_i = X"66" or
3508
                   d_i = X"76" or
3509
                   d_i = X"6E" or
3510
                   d_i = X"7E") AND (rdy_i = '1')) THEN
3511
               ld_o <= "11";
3512
               ld_pc_o <= '1';
3513
            ELSIF ((d_i = X"40") AND (rdy_i = '1')) THEN
3514
               ld_o <= "11";
3515
               ld_pc_o <= '1';
3516
            ELSIF ((d_i = X"60") AND (rdy_i = '1')) THEN
3517
               ld_o <= "11";
3518
               ld_pc_o <= '1';
3519
            ELSIF ((d_i = X"E9" or
3520
                   d_i = X"E5" or
3521
                   d_i = X"F5" or
3522
                   d_i = X"ED" or
3523
                   d_i = X"FD" or
3524
                   d_i = X"F9" or
3525
                   d_i = X"E1" or
3526
                   d_i = X"F1") AND (rdy_i = '1')) THEN
3527
               ld_o <= "11";
3528
               ld_pc_o <= '1';
3529
            ELSIF ((d_i = X"38") AND (rdy_i = '1')) THEN
3530
               ld_o <= "11";
3531
               ld_pc_o <= '1';
3532
            ELSIF ((d_i = X"F8") AND (rdy_i = '1')) THEN
3533
               ld_o <= "11";
3534
               ld_pc_o <= '1';
3535
            ELSIF ((d_i = X"78") AND (rdy_i = '1')) THEN
3536
               ld_o <= "11";
3537
               ld_pc_o <= '1';
3538
            ELSIF ((d_i = X"85" or
3539
                   d_i = X"95" or
3540
                   d_i = X"8D" or
3541
                   d_i = X"9D" or
3542
                   d_i = X"99" or
3543
                   d_i = X"81" or
3544
                   d_i = X"91") AND (rdy_i = '1')) THEN
3545
               ld_o <= "11";
3546
               ld_pc_o <= '1';
3547
            ELSIF ((d_i = X"86" or
3548
                   d_i = X"96" or
3549
                   d_i = X"8E") AND (rdy_i = '1')) THEN
3550
               ld_o <= "11";
3551
               ld_pc_o <= '1';
3552
            ELSIF ((d_i = X"84" or
3553
                   d_i = X"94" or
3554
                   d_i = X"8C") AND (rdy_i = '1')) THEN
3555
               ld_o <= "11";
3556
               ld_pc_o <= '1';
3557
            ELSIF ((d_i = X"AA") AND (rdy_i = '1')) THEN
3558
 
3559
               ld_o <= "11";
3560
               ld_pc_o <= '1';
3561
            ELSIF ((d_i = X"0A") AND (rdy_i = '1')) THEN
3562
               ld_o <= "11";
3563
               ld_pc_o <= '1';
3564
            ELSIF ((d_i = X"4A") AND (rdy_i = '1')) THEN
3565
               ld_o <= "11";
3566
               ld_pc_o <= '1';
3567
            ELSIF ((d_i = X"2A") AND (rdy_i = '1')) THEN
3568
               ld_o <= "11";
3569
               ld_pc_o <= '1';
3570
            ELSIF ((d_i = X"6A") AND (rdy_i = '1')) THEN
3571
               ld_o <= "11";
3572
               ld_pc_o <= '1';
3573
            ELSIF ((d_i = X"A8") AND (rdy_i = '1')) THEN
3574
 
3575
               ld_o <= "11";
3576
               ld_pc_o <= '1';
3577
            ELSIF ((d_i = X"98") AND (rdy_i = '1')) THEN
3578
 
3579
               ld_o <= "11";
3580
               ld_pc_o <= '1';
3581
            ELSIF ((d_i = X"BA") AND (rdy_i = '1')) THEN
3582
 
3583
               ld_o <= "11";
3584
               ld_pc_o <= '1';
3585
            ELSIF ((d_i = X"8A") AND (rdy_i = '1')) THEN
3586
 
3587
               ld_o <= "11";
3588
               ld_pc_o <= '1';
3589
            ELSIF ((d_i = X"9A") AND (rdy_i = '1')) THEN
3590
 
3591
               ld_o <= "11";
3592
               ld_pc_o <= '1';
3593
            ELSIF (rdy_i = '1') THEN
3594
               ld_o <= "11";
3595
               ld_pc_o <= '1';
3596
            END IF;
3597
         WHEN s1 =>
3598
            IF (rdy_i = '1') THEN
3599
               sig_SYNC <= '1';
3600
            END IF;
3601
         WHEN s2 =>
3602
            IF (rdy_i = '1') THEN
3603
               sig_SYNC <= '1';
3604
            END IF;
3605
         WHEN s5 =>
3606
            IF (rdy_i = '1') THEN
3607
               sig_SYNC <= '1';
3608
            END IF;
3609
         WHEN s3 =>
3610
            IF (rdy_i = '1') THEN
3611
               sig_SYNC <= '1';
3612
            END IF;
3613
         WHEN s4 =>
3614
            IF (rdy_i = '1' and
3615
                zw_REG_OP = X"9A") THEN
3616
               adr_o <= X"01" & d_regs_out_i;
3617
               ld_o <= "11";
3618
               ld_sp_o <= '1';
3619
               sig_SYNC <= '1';
3620
            ELSIF (rdy_i = '1' and
3621
                   zw_REG_OP = X"BA") THEN
3622
               d_regs_in_o <= adr_sp_i (7 downto 0);
3623
               ch_a_o <= adr_sp_i (7 downto 0);
3624
               ch_b_o <= X"00";
3625
               load_regs_o <= '1';
3626
               sig_SYNC <= '1';
3627
            ELSIF (rdy_i = '1') THEN
3628
               ch_a_o <= d_regs_out_i;
3629
               ch_b_o <= X"00";
3630
               load_regs_o <= '1';
3631
               sig_SYNC <= '1';
3632
            END IF;
3633
         WHEN s12 =>
3634
            IF (rdy_i = '1') THEN
3635
               sig_SYNC <= '1';
3636
            END IF;
3637
         WHEN s16 =>
3638
            IF (rdy_i = '1') THEN
3639
               sig_SYNC <= '1';
3640
            END IF;
3641
         WHEN s17 =>
3642
            IF (rdy_i = '1') THEN
3643
               sig_SYNC <= '1';
3644
            END IF;
3645
         WHEN s24 =>
3646
            IF (rdy_i = '1') THEN
3647
               sig_SYNC <= '1';
3648
            END IF;
3649
         WHEN s25 =>
3650
            IF (rdy_i = '1') THEN
3651
               d_regs_in_o <= d_alu_i;
3652
               ch_a_o <= d_regs_out_i;
3653
               ch_b_o <= zw_b4;
3654
               load_regs_o <= '1';
3655
               sig_SYNC <= '1';
3656
            END IF;
3657
         WHEN s273 =>
3658
            IF (rdy_i = '1') THEN
3659
               adr_o <= d_i & zw_b1;
3660
               ld_o <= "11";
3661
               ld_pc_o <= '1';
3662
            END IF;
3663
         WHEN s307 =>
3664
            IF (rdy_i = '1') THEN
3665
               adr_o <= d_i & zw_b1;
3666
               ld_o <= "11";
3667
               ld_pc_o <= '1';
3668
               sig_SYNC <= '1';
3669
            END IF;
3670
         WHEN s177 =>
3671
            IF (rdy_i = '1' and
3672
                (zw_REG_OP = X"85" OR
3673
                zw_REG_OP = X"86" OR
3674
                zw_REG_OP = X"84")) THEN
3675
               sig_RWn <= '0';
3676
               sig_RD <= '0';
3677
               sig_WR <= '1';
3678
               sig_D_OUT <= d_regs_out_i;
3679
               ld_o <= "11";
3680
               ld_pc_o <= '1';
3681
            ELSIF (rdy_i = '1' and
3682
                   (zw_REG_OP = X"95" OR
3683
                   zw_REG_OP = X"94")) THEN
3684
               ch_a_o <=  d_i;
3685
               ch_b_o <= q_x_i;
3686
            ELSIF (rdy_i = '1' and
3687
                   (zw_REG_OP = X"8D" OR
3688
                   zw_REG_OP = X"8E" OR
3689
                   zw_REG_OP = X"8C")) THEN
3690
               ld_o <= "11";
3691
               ld_pc_o <= '1';
3692
            ELSIF (rdy_i = '1' and
3693
                   zw_REG_OP = X"9D") THEN
3694
               ld_o <= "11";
3695
               ld_pc_o <= '1';
3696
               ch_a_o <= d_i;
3697
               ch_b_o <= q_x_i;
3698
            ELSIF (rdy_i = '1' and
3699
                   zw_REG_OP = X"99") THEN
3700
               ld_o <= "11";
3701
               ld_pc_o <= '1';
3702
               ch_a_o <= d_i;
3703
               ch_b_o <= q_y_i;
3704
            ELSIF (rdy_i = '1' and
3705
                   zw_REG_OP = X"91") THEN
3706
               ch_a_o <= d_i;
3707
               ch_b_o <= X"01";
3708
            ELSIF (rdy_i = '1' and
3709
                   zw_REG_OP = X"81") THEN
3710
               ch_a_o <=  d_i;
3711
               ch_b_o <= q_x_i;
3712
            ELSIF (rdy_i = '1' and
3713
                   zw_REG_OP = X"96") THEN
3714
               ch_a_o <=  d_i;
3715
               ch_b_o <= q_y_i;
3716
            END IF;
3717
         WHEN s180 =>
3718
            IF (rdy_i = '1') THEN
3719
               ch_a_o <= d_i;
3720
               ch_b_o <= "0000000" & zw_b2(0);
3721
               ld_o <= "11";
3722
               ld_pc_o <= '1';
3723
            END IF;
3724
         WHEN s181 =>
3725
            IF (rdy_i = '1') THEN
3726
               ch_a_o <= d_i;
3727
               ch_b_o <= q_y_i;
3728
            END IF;
3729
         WHEN s182 =>
3730
            sig_RWn <= '1';
3731
            sig_RD <= '1';
3732
            IF (rdy_i = '1') THEN
3733
               ch_a_o <= d_i;
3734
               ch_b_o <= "0000000" & zw_b2(0);
3735
               ld_o <= "11";
3736
               ld_pc_o <= '1';
3737
            END IF;
3738
         WHEN s183 =>
3739
            IF (rdy_i = '1') THEN
3740
               sig_RWn <= '0';
3741
               sig_RD <= '0';
3742
               sig_WR <= '1';
3743
               sig_D_OUT <= d_regs_out_i;
3744
               ld_o <= "11";
3745
               ld_pc_o <= '1';
3746
            END IF;
3747
         WHEN s184 =>
3748
            sig_SYNC <= '1';
3749
         WHEN s185 =>
3750
            IF (rdy_i = '1') THEN
3751
               sig_RWn <= '0';
3752
               sig_RD <= '0';
3753
               sig_WR <= '1';
3754
               sig_D_OUT <= d_regs_out_i;
3755
               ld_o <= "11";
3756
               ld_pc_o <= '1';
3757
            END IF;
3758
         WHEN s187 =>
3759
            sig_SYNC <= '1';
3760
         WHEN s188 =>
3761
            IF (rdy_i = '1') THEN
3762
               ch_a_o <=  zw_b1;
3763
               ch_b_o <= X"01";
3764
            END IF;
3765
         WHEN s189 =>
3766
            IF (rdy_i = '1') THEN
3767
               ch_a_o <= d_i;
3768
               ch_b_o <= "0000000" & zw_b2(0);
3769
               ld_o <= "11";
3770
               ld_pc_o <= '1';
3771
            END IF;
3772
         WHEN s190 =>
3773
            sig_SYNC <= '1';
3774
         WHEN s191 =>
3775
            sig_RWn <= '0';
3776
            sig_RD <= '0';
3777
            sig_WR <= '1';
3778
            sig_D_OUT <= d_regs_out_i;
3779
         WHEN s192 =>
3780
            sig_RWn <= '0';
3781
            sig_RD <= '0';
3782
            sig_WR <= '1';
3783
            sig_D_OUT <= d_regs_out_i;
3784
            ld_o <= "11";
3785
            ld_pc_o <= '1';
3786
         WHEN s193 =>
3787
            sig_SYNC <= '1';
3788
         WHEN s377 =>
3789
            IF (rdy_i = '1') THEN
3790
               sig_RWn <= '0';
3791
               sig_RD <= '0';
3792
               sig_WR <= '1';
3793
               sig_D_OUT <= q_a_i;
3794
               ld_o <= "11";
3795
               ld_sp_o <= '1';
3796
            END IF;
3797
         WHEN s381 =>
3798
            sig_SYNC <= '1';
3799
         WHEN s378 =>
3800
            IF (rdy_i = '1') THEN
3801
               sig_RWn <= '0';
3802
               sig_RD <= '0';
3803
               sig_WR <= '1';
3804
               sig_D_OUT <= reg_F;
3805
               ld_o <= "11";
3806
               ld_sp_o <= '1';
3807
            END IF;
3808
         WHEN s382 =>
3809
            sig_SYNC <= '1';
3810
         WHEN s379 =>
3811
            IF (rdy_i = '1') THEN
3812
               ld_o <= "11";
3813
               ld_sp_o <= '1';
3814
            END IF;
3815
         WHEN s384 =>
3816
            IF (rdy_i = '1') THEN
3817
               d_regs_in_o <= d_i;
3818
               load_regs_o <= '1';
3819
               ch_a_o <= d_i;
3820
               ch_b_o <= X"00";
3821
               sig_SYNC <= '1';
3822
            END IF;
3823
         WHEN s380 =>
3824
            IF (rdy_i = '1') THEN
3825
               ld_o <= "11";
3826
               ld_sp_o <= '1';
3827
            END IF;
3828
         WHEN s386 =>
3829
            IF (rdy_i = '1') THEN
3830
               sig_SYNC <= '1';
3831
            END IF;
3832
         WHEN s387 =>
3833
            IF (rdy_i = '1') THEN
3834
               ld_o <= "11";
3835
               ld_sp_o <= '1';
3836
            END IF;
3837
         WHEN s388 =>
3838
            IF (rdy_i = '1') THEN
3839
               ld_o <= "11";
3840
               ld_sp_o <= '1';
3841
            END IF;
3842
         WHEN s389 =>
3843
            IF (rdy_i = '1') THEN
3844
               ld_o <= "11";
3845
               ld_sp_o <= '1';
3846
            END IF;
3847
         WHEN s392 =>
3848
            IF (rdy_i = '1') THEN
3849
               adr_o <= d_i & zw_b1;
3850
               ld_o <= "11";
3851
               ld_pc_o <= '1';
3852
               sig_SYNC <= '1';
3853
            END IF;
3854
         WHEN s390 =>
3855
            IF (rdy_i = '1') THEN
3856
               ld_o <= "11";
3857
               ld_sp_o <= '1';
3858
            END IF;
3859
         WHEN s393 =>
3860
            IF (rdy_i = '1') THEN
3861
               ld_o <= "11";
3862
               ld_sp_o <= '1';
3863
            END IF;
3864
         WHEN s395 =>
3865
            IF (rdy_i = '1') THEN
3866
               adr_o <= d_i & zw_b1;
3867
               ld_o <= "11";
3868
               ld_pc_o <= '1';
3869
            END IF;
3870
         WHEN s396 =>
3871
            IF (rdy_i = '1') THEN
3872
               sig_SYNC <= '1';
3873
            END IF;
3874
         WHEN s397 =>
3875
            IF (rdy_i = '1') THEN
3876
               ld_o <= "11";
3877
               ld_sp_o <= '1';
3878
               ld_pc_o <= '1';
3879
            END IF;
3880
         WHEN s398 =>
3881
            IF (rdy_i = '1') THEN
3882
               sig_RWn <= '0';
3883
               sig_RD <= '0';
3884
               sig_WR <= '1';
3885
               sig_D_OUT <= adr_pc_i (15 downto 8);
3886
            END IF;
3887
         WHEN s399 =>
3888
            ld_o <= "11";
3889
            ld_sp_o <= '1';
3890
            sig_RWn <= '0';
3891
            sig_RD <= '0';
3892
            sig_WR <= '1';
3893
            sig_D_OUT <= adr_pc_i (7 downto 0);
3894
         WHEN s401 =>
3895
            IF (rdy_i = '1') THEN
3896
               adr_o <= d_i & zw_b1;
3897
               ld_o <= "11";
3898
               ld_pc_o <= '1';
3899
               sig_SYNC <= '1';
3900
            END IF;
3901
         WHEN s526 =>
3902
            IF (rdy_i = '1') THEN
3903
               ld_o <= "11";
3904
               ld_sp_o <= '1';
3905
               ld_pc_o <= '1';
3906
               sig_RWn <= '0';
3907
               sig_RD <= '0';
3908
               sig_WR <= '1';
3909
               sig_D_OUT <= adr_pc_i (15 downto 8);
3910
            END IF;
3911
         WHEN s527 =>
3912
            ld_o <= "11";
3913
            ld_sp_o <= '1';
3914
            sig_RWn <= '0';
3915
            sig_RD <= '0';
3916
            sig_WR <= '1';
3917
            sig_D_OUT <= adr_pc_i (7 downto 0);
3918
         WHEN s528 =>
3919
            ld_o <= "11";
3920
            ld_sp_o <= '1';
3921
            sig_RWn <= '0';
3922
            sig_RD <= '0';
3923
            sig_WR <= '1';
3924
            sig_D_OUT <= reg_F OR X"10";
3925
         WHEN s530 =>
3926
            IF (rdy_i = '1') THEN
3927
               adr_o <= d_i & zw_b1;
3928
               ld_o <= "11";
3929
               ld_pc_o <= '1';
3930
               sig_SYNC <= '1';
3931
            END IF;
3932
         WHEN s544 =>
3933
            ld_o <= "11";
3934
            ld_sp_o <= '1';
3935
         WHEN s545 =>
3936
            adr_o <= X"FFFB";
3937
            ld_o <= "11";
3938
            ld_pc_o <= '1';
3939
         WHEN s546 =>
3940
            ld_o <= "11";
3941
            ld_pc_o <= '1';
3942
         WHEN s549 =>
3943
            IF (rdy_i = '1') THEN
3944
               adr_o <= d_i & zw_b1;
3945
               ld_o <= "11";
3946
               ld_pc_o <= '1';
3947
               sig_SYNC <= '1';
3948
            END IF;
3949
         WHEN s550 =>
3950
            ld_o <= "11";
3951
            ld_sp_o <= '1';
3952
         WHEN s404 =>
3953
            IF (rdy_i = '1') THEN
3954
               ch_a_o <= q_a_i (6 downto 0) & '0';
3955
               ch_b_o <= X"00";
3956
               d_regs_in_o <= q_a_i (6 downto 0) & '0';
3957
               load_regs_o <= '1';
3958
               sig_SYNC <= '1';
3959
            END IF;
3960
         WHEN s556 =>
3961
            IF (rdy_i = '1') THEN
3962
               ch_a_o <= '0' & q_a_i (7 downto 1);
3963
               ch_b_o <= X"00";
3964
               d_regs_in_o <= '0' & q_a_i (7 downto 1);
3965
               load_regs_o <= '1';
3966
               sig_SYNC <= '1';
3967
            END IF;
3968
         WHEN s557 =>
3969
            IF (rdy_i = '1') THEN
3970
               ch_a_o <= q_a_i (6 downto 0) & reg_F(0);
3971
               ch_b_o <= X"00";
3972
               d_regs_in_o <= q_a_i (6 downto 0) & reg_F(0);
3973
               load_regs_o <= '1';
3974
               sig_SYNC <= '1';
3975
            END IF;
3976
         WHEN s579 =>
3977
            IF (rdy_i = '1') THEN
3978
               ch_a_o <= reg_F(0) & q_a_i (7 downto 1);
3979
               ch_b_o <= X"00";
3980
               d_regs_in_o <= reg_F(0) & q_a_i (7 downto 1);
3981
               load_regs_o <= '1';
3982
               sig_SYNC <= '1';
3983
            END IF;
3984
         WHEN s201 =>
3985
            IF (rdy_i = '1' and
3986
                (zw_REG_OP = X"A5" OR zw_REG_OP = X"A6" OR
3987
                zw_REG_OP = X"A4" OR zw_REG_OP = X"45" OR
3988
                zw_REG_OP = X"05" OR zw_REG_OP = X"25" OR
3989
                zw_REG_OP = X"C5" OR zw_REG_OP = X"E4" OR zw_REG_OP = X"C4")) THEN
3990
               ld_o <= "11";
3991
               ld_pc_o <= '1';
3992
            ELSIF ((rdy_i = '1' and
3993
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
3994
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
3995
                   zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
3996
                   zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
3997
                   zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
3998
               ld_o <= "11";
3999
               ld_pc_o <= '1';
4000
               d_regs_in_o <= d_i OR q_a_i;
4001
               load_regs_o <= '1';
4002
               ch_a_o <= d_i OR q_a_i;
4003
               ch_b_o <= X"00";
4004
               sig_SYNC <= '1';
4005
            ELSIF ((rdy_i = '1' and
4006
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
4007
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
4008
                   zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
4009
                   zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
4010
                   zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
4011
               ld_o <= "11";
4012
               ld_pc_o <= '1';
4013
               d_regs_in_o <= d_i XOR q_a_i;
4014
               load_regs_o <= '1';
4015
               ch_a_o <= d_i XOR q_a_i;
4016
               ch_b_o <= X"00";
4017
               sig_SYNC <= '1';
4018
            ELSIF ((rdy_i = '1' and
4019
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
4020
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
4021
                   zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
4022
                   zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
4023
                    zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
4024
               ld_o <= "11";
4025
               ld_pc_o <= '1';
4026
               d_regs_in_o <= d_i AND q_a_i;
4027
               load_regs_o <= '1';
4028
               ch_a_o <= d_i AND q_a_i;
4029
               ch_b_o <= X"00";
4030
               sig_SYNC <= '1';
4031
            ELSIF ((rdy_i = '1' and
4032
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
4033
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
4034
                   zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
4035
                   zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
4036
                   zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
4037
                    zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
4038
                    zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
4039
                    zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
4040
               ld_o <= "11";
4041
               ld_pc_o <= '1';
4042
               zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
4043
               sig_SYNC <= '1';
4044
            ELSIF (rdy_i = '1' and
4045
                   (zw_REG_OP = X"A9" OR zw_REG_OP = X"A2" OR zw_REG_OP = X"A0" OR zw_REG_OP = X"E0" OR zw_REG_OP = X"C0" OR
4046
                   zw_REG_OP = X"49" or zw_REG_OP = X"09" or zw_REG_OP = X"29" or zw_REG_OP = X"C9")) THEN
4047
               ld_o <= "11";
4048
               ld_pc_o <= '1';
4049
               d_regs_in_o <= d_i;
4050
               load_regs_o <= '1';
4051
               ch_a_o <= d_i;
4052
               ch_b_o <= X"00";
4053
               sig_SYNC <= '1';
4054
            ELSIF (rdy_i = '1' and
4055
                   (zw_REG_OP = X"B5" OR
4056
                   zw_REG_OP = X"B4" OR
4057
                   zw_REG_OP = X"55" OR zw_REG_OP = X"15" OR
4058
                   zw_REG_OP = X"35" OR
4059
                   zw_REG_OP = X"D5")) THEN
4060
               ch_a_o <=  d_i;
4061
               ch_b_o <= q_x_i;
4062
            ELSIF (rdy_i = '1' and
4063
                   (zw_REG_OP = X"AD" OR
4064
                   zw_REG_OP = X"AE" OR
4065
                   zw_REG_OP = X"AC" OR
4066
                   zw_REG_OP = X"4D" OR
4067
                   zw_REG_OP = X"0D" OR
4068
                   zw_REG_OP = X"2D" OR
4069
                   zw_REG_OP = X"CD" OR
4070
                   zw_REG_OP = X"EC" OR
4071
                   zw_REG_OP = X"CC")) THEN
4072
               ld_o <= "11";
4073
               ld_pc_o <= '1';
4074
            ELSIF (rdy_i = '1' and
4075
                   (zw_REG_OP = X"BD" OR
4076
                   zw_REG_OP = X"BC" OR
4077
                   zw_REG_OP = X"5D" OR
4078
                   zw_REG_OP = X"1D" OR
4079
                   zw_REG_OP = X"3D" OR
4080
                   zw_REG_OP = X"DD")) THEN
4081
               ld_o <= "11";
4082
               ld_pc_o <= '1';
4083
               ch_a_o <= d_i;
4084
               ch_b_o <= q_x_i;
4085
            ELSIF (rdy_i = '1' and
4086
                   (zw_REG_OP = X"B9" OR
4087
                   zw_REG_OP = X"BE" OR
4088
                   zw_REG_OP = X"59" OR
4089
                   zw_REG_OP = X"19" OR
4090
                   zw_REG_OP = X"39" OR
4091
                   zw_REG_OP = X"D9")) THEN
4092
               ld_o <= "11";
4093
               ld_pc_o <= '1';
4094
               ch_a_o <= d_i;
4095
               ch_b_o <= q_y_i;
4096
            ELSIF (rdy_i = '1' and
4097
                   (zw_REG_OP = X"B1" OR
4098
                   zw_REG_OP = X"51" OR
4099
                   zw_REG_OP = X"11" OR
4100
                   zw_REG_OP = X"31" OR
4101
                   zw_REG_OP = X"D1")) THEN
4102
               ch_a_o <= d_i;
4103
               ch_b_o <= X"01";
4104
            ELSIF (rdy_i = '1' and
4105
                   (zw_REG_OP = X"A1" OR
4106
                   zw_REG_OP = X"41" OR
4107
                   zw_REG_OP = X"01" OR
4108
                   zw_REG_OP = X"21" OR
4109
                   zw_REG_OP = X"C1")) THEN
4110
               ch_a_o <=  d_i;
4111
               ch_b_o <= q_x_i;
4112
            ELSIF (rdy_i = '1' and
4113
                   zw_REG_OP = X"B6") THEN
4114
               ch_a_o <=  d_i;
4115
               ch_b_o <= q_y_i;
4116
            END IF;
4117
         WHEN s202 =>
4118
            IF (rdy_i = '1') THEN
4119
               ld_o <= "11";
4120
               ld_pc_o <= '1';
4121
            END IF;
4122
         WHEN s210 =>
4123
            IF (rdy_i = '1') THEN
4124
               ch_a_o <= d_i;
4125
               ch_b_o <= "0000000" & zw_b2(0);
4126
               ld_o <= "11";
4127
               ld_pc_o <= '1';
4128
            END IF;
4129
         WHEN s211 =>
4130
            IF (rdy_i = '1') THEN
4131
               ch_a_o <= d_i;
4132
               ch_b_o <= "0000000" & zw_b2(0);
4133
               ld_o <= "11";
4134
               ld_pc_o <= '1';
4135
            END IF;
4136
         WHEN s215 =>
4137
            IF (rdy_i = '1') THEN
4138
               ch_a_o <= d_i;
4139
               ch_b_o <= q_y_i;
4140
            END IF;
4141
         WHEN s217 =>
4142
            IF (rdy_i = '1') THEN
4143
               ld_o <= "11";
4144
               ld_pc_o <= '1';
4145
            END IF;
4146
         WHEN s222 =>
4147
            IF (rdy_i = '1') THEN
4148
               ch_a_o <=  zw_b1;
4149
               ch_b_o <= X"01";
4150
            END IF;
4151
         WHEN s223 =>
4152
            IF (rdy_i = '1') THEN
4153
               ch_a_o <= d_i;
4154
               ch_b_o <= "0000000" & zw_b2(0);
4155
               ld_o <= "11";
4156
               ld_pc_o <= '1';
4157
            END IF;
4158
         WHEN s224 =>
4159
            IF ((rdy_i = '1') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
4160
                zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
4161
                zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
4162
                zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
4163
               d_regs_in_o <= d_i OR q_a_i;
4164
               load_regs_o <= '1';
4165
               ch_a_o <= d_i OR q_a_i;
4166
               ch_b_o <= X"00";
4167
               sig_SYNC <= '1';
4168
            ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
4169
                   zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
4170
                   zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
4171
                   zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
4172
               d_regs_in_o <= d_i XOR q_a_i;
4173
               load_regs_o <= '1';
4174
               ch_a_o <= d_i XOR q_a_i;
4175
               ch_b_o <= X"00";
4176
               sig_SYNC <= '1';
4177
            ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
4178
                   zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
4179
                   zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
4180
                    zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
4181
               d_regs_in_o <= d_i AND q_a_i;
4182
               load_regs_o <= '1';
4183
               ch_a_o <= d_i AND q_a_i;
4184
               ch_b_o <= X"00";
4185
               sig_SYNC <= '1';
4186
            ELSIF ((rdy_i = '1') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
4187
                   zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
4188
                   zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
4189
                   zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
4190
                    zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
4191
                    zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
4192
                    zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
4193
               zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
4194
               sig_SYNC <= '1';
4195
            ELSIF (rdy_i = '1') THEN
4196
               d_regs_in_o <= d_i;
4197
               load_regs_o <= '1';
4198
               ch_a_o <= d_i;
4199
               ch_b_o <= X"00";
4200
               sig_SYNC <= '1';
4201
            END IF;
4202
         WHEN s225 =>
4203
            IF ((rdy_i = '1' AND
4204
                zw_b2(0) = '0') AND (zw_REG_OP = X"09" or zw_REG_OP = X"05" or
4205
                zw_REG_OP = X"15" or zw_REG_OP = X"0D" or
4206
                zw_REG_OP = X"1D" or zw_REG_OP = X"19" or
4207
                zw_REG_OP = X"01" or zw_REG_OP = X"11")) THEN
4208
               d_regs_in_o <= d_i OR q_a_i;
4209
               load_regs_o <= '1';
4210
               ch_a_o <= d_i OR q_a_i;
4211
               ch_b_o <= X"00";
4212
               sig_SYNC <= '1';
4213
            ELSIF ((rdy_i = '1' AND
4214
                   zw_b2(0) = '0') AND (zw_REG_OP = X"49" or zw_REG_OP = X"45" or
4215
                   zw_REG_OP = X"55" or zw_REG_OP = X"4D" or
4216
                   zw_REG_OP = X"5D" or zw_REG_OP = X"59" or
4217
                   zw_REG_OP = X"41" or zw_REG_OP = X"51")) THEN
4218
               d_regs_in_o <= d_i XOR q_a_i;
4219
               load_regs_o <= '1';
4220
               ch_a_o <= d_i XOR q_a_i;
4221
               ch_b_o <= X"00";
4222
               sig_SYNC <= '1';
4223
            ELSIF ((rdy_i = '1' AND
4224
                   zw_b2(0) = '0') AND (zw_REG_OP = X"29" or zw_REG_OP = X"25" or
4225
                   zw_REG_OP = X"35" or zw_REG_OP = X"2D" or
4226
                   zw_REG_OP = X"3D" or zw_REG_OP = X"39" or
4227
                    zw_REG_OP = X"21" or zw_REG_OP = X"31")) THEN
4228
               d_regs_in_o <= d_i AND q_a_i;
4229
               load_regs_o <= '1';
4230
               ch_a_o <= d_i AND q_a_i;
4231
               ch_b_o <= X"00";
4232
               sig_SYNC <= '1';
4233
            ELSIF ((rdy_i = '1' AND
4234
                   zw_b2(0) = '0') AND (zw_REG_OP = X"C9" or zw_REG_OP = X"C5" or
4235
                   zw_REG_OP = X"D5" or zw_REG_OP = X"CD" or
4236
                   zw_REG_OP = X"DD" or zw_REG_OP = X"D9" or
4237
                   zw_REG_OP = X"C1" or zw_REG_OP = X"D1" or
4238
                    zw_REG_OP = X"C0" or zw_REG_OP = X"E0" or
4239
                    zw_REG_OP = X"C4" or zw_REG_OP = X"E4" or
4240
                    zw_REG_OP = X"CC" or zw_REG_OP = X"EC")) THEN
4241
               zw_ALU <= unsigned ('0' & d_regs_out_i) + unsigned ('0' & NOT (d_i)) + 1;
4242
               sig_SYNC <= '1';
4243
            ELSIF (rdy_i = '1' AND
4244
                   zw_b2(0) = '0') THEN
4245
               d_regs_in_o <= d_i;
4246
               load_regs_o <= '1';
4247
               ch_a_o <= d_i;
4248
               ch_b_o <= X"00";
4249
               sig_SYNC <= '1';
4250
            END IF;
4251
         WHEN s226 =>
4252
            IF (rdy_i = '1' and
4253
                (zw_REG_OP = X"C6" OR
4254
                zw_REG_OP = X"E6")) THEN
4255
               ld_o <= "11";
4256
               ld_pc_o <= '1';
4257
            ELSIF (rdy_i = '1' and
4258
                   (zw_REG_OP = X"D6" OR
4259
                   zw_REG_OP = X"F6")) THEN
4260
               ch_a_o <=  d_i;
4261
               ch_b_o <= q_x_i;
4262
            ELSIF (rdy_i = '1' and
4263
                   (zw_REG_OP = X"CE" OR
4264
                   zw_REG_OP = X"EE")) THEN
4265
               ld_o <= "11";
4266
               ld_pc_o <= '1';
4267
            ELSIF (rdy_i = '1' and
4268
                   (zw_REG_OP = X"DE" OR
4269
                   zw_REG_OP = X"FE")) THEN
4270
               ld_o <= "11";
4271
               ld_pc_o <= '1';
4272
               ch_a_o <= d_i;
4273
               ch_b_o <= q_x_i;
4274
            END IF;
4275
         WHEN s243 =>
4276
            IF (rdy_i = '1') THEN
4277
               ld_o <= "11";
4278
               ld_pc_o <= '1';
4279
            END IF;
4280
         WHEN s244 =>
4281
            IF (rdy_i = '1') THEN
4282
               ch_a_o <= d_i;
4283
               ch_b_o <= "0000000" & zw_b2(0);
4284
               ld_o <= "11";
4285
               ld_pc_o <= '1';
4286
            END IF;
4287
         WHEN s247 =>
4288
            IF (rdy_i = '1') THEN
4289
               ld_o <= "11";
4290
               ld_pc_o <= '1';
4291
            END IF;
4292
         WHEN s343 =>
4293
            IF (rdy_i = '1') THEN
4294
               ch_a_o <= d_i;
4295
               ch_b_o <= zw_b4;
4296
            END IF;
4297
         WHEN s250 =>
4298
            IF (rdy_i = '1') THEN
4299
               sig_RWn <= '0';
4300
               sig_RD <= '0';
4301
               sig_WR <= '1';
4302
               sig_D_OUT <= zw_b1;
4303
            END IF;
4304
         WHEN s251 =>
4305
            ch_a_o <= zw_b1;
4306
            ch_b_o <= X"00";
4307
            sig_SYNC <= '1';
4308
         WHEN s351 =>
4309
            IF (rdy_i = '1' and
4310
                zw_REG_OP = X"24") THEN
4311
               ld_o <= "11";
4312
               ld_pc_o <= '1';
4313
            ELSIF (rdy_i = '1' and
4314
                   zw_REG_OP = X"2C") THEN
4315
               ld_o <= "11";
4316
               ld_pc_o <= '1';
4317
            END IF;
4318
         WHEN s361 =>
4319
            IF (rdy_i = '1') THEN
4320
               ch_a_o <= q_a_i AND d_i;
4321
               ch_b_o <= X"00";
4322
               sig_SYNC <= '1';
4323
            END IF;
4324
         WHEN s360 =>
4325
            IF (rdy_i = '1') THEN
4326
               ld_o <= "11";
4327
               ld_pc_o <= '1';
4328
            END IF;
4329
         WHEN s403 =>
4330
            IF (rdy_i = '1' and
4331
                (zw_REG_OP = X"1E" or
4332
                zw_REG_OP = X"7E" or
4333
                zw_REG_OP = X"3E" or
4334
                zw_REG_OP = X"5E")) THEN
4335
               ld_o <= "11";
4336
               ld_pc_o <= '1';
4337
               ch_a_o <= d_i;
4338
               ch_b_o <= q_x_i;
4339
            ELSIF (rdy_i = '1' and
4340
                   (zw_REG_OP = X"06" or
4341
                   zw_REG_OP = X"66" or
4342
                   zw_REG_OP = X"26" or
4343
                   zw_REG_OP = X"46")) THEN
4344
               ld_o <= "11";
4345
               ld_pc_o <= '1';
4346
            ELSIF (rdy_i = '1' and
4347
                   (zw_REG_OP = X"16" or
4348
                   zw_REG_OP = X"76" or
4349
                   zw_REG_OP = X"36" or
4350
                   zw_REG_OP = X"56")) THEN
4351
               ch_a_o <=  d_i;
4352
               ch_b_o <= q_x_i;
4353
            ELSIF (rdy_i = '1' and
4354
                   (zw_REG_OP = X"0E" or
4355
                   zw_REG_OP = X"6E" or
4356
                   zw_REG_OP = X"2E" or
4357
                   zw_REG_OP = X"4E")) THEN
4358
               ld_o <= "11";
4359
               ld_pc_o <= '1';
4360
            END IF;
4361
         WHEN s406 =>
4362
            IF (rdy_i = '1') THEN
4363
               ld_o <= "11";
4364
               ld_pc_o <= '1';
4365
            END IF;
4366
         WHEN s407 =>
4367
            IF (rdy_i = '1') THEN
4368
               ch_a_o <= d_i;
4369
               ch_b_o <= "0000000" & zw_b2(0);
4370
               ld_o <= "11";
4371
               ld_pc_o <= '1';
4372
            END IF;
4373
         WHEN s409 =>
4374
            IF (rdy_i = '1') THEN
4375
               ld_o <= "11";
4376
               ld_pc_o <= '1';
4377
            END IF;
4378
         WHEN s416 =>
4379
            IF (rdy_i = '1' and
4380
                (zw_REG_OP = X"06" or
4381
                zw_REG_OP = X"16" or
4382
                zw_REG_OP = X"0E" or
4383
                zw_REG_OP = X"1E")) THEN
4384
               sig_D_OUT <= d_i(6 downto 0) & '0';
4385
               sig_RWn <= '0';
4386
               sig_RD <= '0';
4387
               sig_WR <= '1';
4388
            ELSIF (rdy_i = '1' and
4389
                   (zw_REG_OP = X"46" or
4390
                   zw_REG_OP = X"56" or
4391
                   zw_REG_OP = X"4E" or
4392
                   zw_REG_OP = X"5E")) THEN
4393
               sig_D_OUT <= '0' & d_i(7 downto 1);
4394
               sig_RWn <= '0';
4395
               sig_RD <= '0';
4396
               sig_WR <= '1';
4397
            ELSIF (rdy_i = '1' and
4398
                   (zw_REG_OP = X"26" or
4399
                   zw_REG_OP = X"36" or
4400
                   zw_REG_OP = X"2E" or
4401
                   zw_REG_OP = X"3E")) THEN
4402
               sig_D_OUT <= d_i(6 downto 0) & reg_F(0);
4403
               sig_RWn <= '0';
4404
               sig_RD <= '0';
4405
               sig_WR <= '1';
4406
            ELSIF (rdy_i = '1' and
4407
                   (zw_REG_OP = X"66" or
4408
                   zw_REG_OP = X"76" or
4409
                   zw_REG_OP = X"6E" or
4410
                   zw_REG_OP = X"7E")) THEN
4411
               sig_D_OUT <= reg_F(0) & d_i(7 downto 1);
4412
               sig_RWn <= '0';
4413
               sig_RD <= '0';
4414
               sig_WR <= '1';
4415
            END IF;
4416
         WHEN s418 =>
4417
            ch_a_o <= zw_b1;
4418
            ch_b_o <= X"00";
4419
            sig_SYNC <= '1';
4420
         WHEN s510 =>
4421
            IF (rdy_i = '1' and
4422
                zw_REG_OP = X"65") THEN
4423
               ld_o <= "11";
4424
               ld_pc_o <= '1';
4425
            ELSIF (rdy_i = '1' and
4426
                   zw_REG_OP = X"69" and
4427
                   reg_F(3) = '0') THEN
4428
               ld_o <= "11";
4429
               ld_pc_o <= '1';
4430
               d_regs_in_o <= zw_ALU(7 downto 0);
4431
               load_regs_o <= '1';
4432
               zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
4433
               sig_SYNC <= '1';
4434
            ELSIF (rdy_i = '1' and
4435
                   zw_REG_OP = X"75") THEN
4436
               ch_a_o <=  d_i;
4437
               ch_b_o <= q_x_i;
4438
            ELSIF (rdy_i = '1' and
4439
                   zw_REG_OP = X"6D") THEN
4440
               ld_o <= "11";
4441
               ld_pc_o <= '1';
4442
            ELSIF (rdy_i = '1' and
4443
                   zw_REG_OP = X"7D") THEN
4444
               ld_o <= "11";
4445
               ld_pc_o <= '1';
4446
               ch_a_o <= d_i;
4447
               ch_b_o <= q_x_i;
4448
            ELSIF (rdy_i = '1' and
4449
                   zw_REG_OP = X"79") THEN
4450
               ld_o <= "11";
4451
               ld_pc_o <= '1';
4452
               ch_a_o <= d_i;
4453
               ch_b_o <= q_y_i;
4454
            ELSIF (rdy_i = '1' and
4455
                   zw_REG_OP = X"71") THEN
4456
               ch_a_o <= d_i;
4457
               ch_b_o <= X"01";
4458
            ELSIF (rdy_i = '1' and
4459
                   zw_REG_OP = X"61") THEN
4460
               ch_a_o <=  d_i;
4461
               ch_b_o <= q_x_i;
4462
            ELSIF (rdy_i = '1' and
4463
                   zw_REG_OP = X"69" and
4464
                   reg_F(3) = '1') THEN
4465
               ld_o <= "11";
4466
               ld_pc_o <= '1';
4467
               d_regs_in_o <= zw_ALU(7 downto 0);
4468
               load_regs_o <= '1';
4469
               zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
4470
               zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
4471
 
4472
               zw_ALU6(2 downto 0) <=  (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
4473
               zw_ALU5(2 downto 0) <=  (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
4474
 
4475
               zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
4476
               zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
4477
 
4478
               zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
4479
               zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
4480
               sig_SYNC <= '1';
4481
            END IF;
4482
         WHEN s553 =>
4483
            IF (rdy_i = '1') THEN
4484
               ld_o <= "11";
4485
               ld_pc_o <= '1';
4486
            END IF;
4487
         WHEN s555 =>
4488
            IF (rdy_i = '1') THEN
4489
               ch_a_o <= d_i;
4490
               ch_b_o <= X"01";
4491
               ld_o <= "11";
4492
               ld_pc_o <= '1';
4493
            END IF;
4494
         WHEN s558 =>
4495
            IF (rdy_i = '1') THEN
4496
               ch_a_o <= d_i;
4497
               ch_b_o <= q_y_i;
4498
            END IF;
4499
         WHEN s560 =>
4500
            IF (rdy_i = '1') THEN
4501
               ld_o <= "11";
4502
               ld_pc_o <= '1';
4503
            END IF;
4504
         WHEN s563 =>
4505
            IF (rdy_i = '1') THEN
4506
               ch_a_o <=  zw_b1;
4507
               ch_b_o <= X"01";
4508
            END IF;
4509
         WHEN s564 =>
4510
            IF (rdy_i = '1' AND
4511
                zw_b2(0) = '0' and
4512
                reg_F(3) = '0') THEN
4513
               d_regs_in_o <= zw_ALU(7 downto 0);
4514
               load_regs_o <= '1';
4515
               zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
4516
               sig_SYNC <= '1';
4517
            ELSIF (rdy_i = '1' AND
4518
                   zw_b2(0) = '0' and
4519
                   reg_F(3) = '1') THEN
4520
               d_regs_in_o <= zw_ALU(7 downto 0);
4521
               load_regs_o <= '1';
4522
               zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
4523
               zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
4524
 
4525
               zw_ALU6(2 downto 0) <=  (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
4526
               zw_ALU5(2 downto 0) <=  (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
4527
 
4528
               zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
4529
               zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
4530
 
4531
               zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
4532
               zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
4533
               sig_SYNC <= '1';
4534
            END IF;
4535
         WHEN s565 =>
4536
            IF (rdy_i = '1' and
4537
                reg_F(3) = '0') THEN
4538
               d_regs_in_o <= zw_ALU(7 downto 0);
4539
               load_regs_o <= '1';
4540
               zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & d_i) + reg_F(0);
4541
               sig_SYNC <= '1';
4542
            ELSIF (rdy_i = '1' and
4543
                   reg_F(3) = '1') THEN
4544
               d_regs_in_o <= zw_ALU(7 downto 0);
4545
               load_regs_o <= '1';
4546
               zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6(2 downto 0));
4547
               zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5(2 downto 0));
4548
 
4549
               zw_ALU6(2 downto 0) <=  (zw_ALU2(4) OR (zw_ALU4(4))) & (zw_ALU2(4) OR (zw_ALU4(4))) & '0';
4550
               zw_ALU5(2 downto 0) <=  (zw_ALU1(4) OR (zw_ALU3(4))) & (zw_ALU1(4) OR (zw_ALU3(4))) & '0';
4551
 
4552
               zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
4553
               zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & d_i(7 downto 4)) + (zw_ALU1(4) OR zw_ALU3(4));
4554
 
4555
               zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
4556
               zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & d_i(3 downto 0)) + reg_F(0);
4557
               sig_SYNC <= '1';
4558
            END IF;
4559
         WHEN s566 =>
4560
            IF (rdy_i = '1') THEN
4561
               ch_a_o <= d_i;
4562
               ch_b_o <= X"01";
4563
               ld_o <= "11";
4564
               ld_pc_o <= '1';
4565
            END IF;
4566
         WHEN s266 =>
4567
            IF (rdy_i = '1' and (
4568
                (reg_F(0) = '1' and zw_REG_OP = X"90") or
4569
                (reg_F(0) = '0' and zw_REG_OP = X"B0") or
4570
                (reg_F(1) = '0' and zw_REG_OP = X"F0") or
4571
                (reg_F(7) = '0' and zw_REG_OP = X"30") or
4572
                (reg_F(1) = '1' and zw_REG_OP = X"D0") or
4573
                (reg_F(7) = '1' and zw_REG_OP = X"10") or
4574
                (reg_F(6) = '1' and zw_REG_OP = X"50") or
4575
                (reg_F(6) = '0' and zw_REG_OP = X"70"))) THEN
4576
               ld_o <= "11";
4577
               ld_pc_o <= '1';
4578
               sig_SYNC <= '1';
4579
            ELSIF (rdy_i = '1') THEN
4580
               ld_o <= "11";
4581
               ld_pc_o <= '1';
4582
            END IF;
4583
         WHEN s301 =>
4584
            IF (rdy_i = '1' and
4585
                zw_b3 = adr_nxt_pc_i (15 downto 8)) THEN
4586
               offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
4587
               zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
4588
               ld_o <= "11";
4589
               ld_pc_o <= '1';
4590
               sig_SYNC <= '1';
4591
            ELSIF (rdy_i = '1') THEN
4592
               offset_o <= (zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) &
4593
               zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(7) & zw_b2(6 downto 0));
4594
               ld_o <= "11";
4595
               ld_pc_o <= '1';
4596
            END IF;
4597
         WHEN s302 =>
4598
            IF (rdy_i = '1') THEN
4599
               sig_SYNC <= '1';
4600
            END IF;
4601
         WHEN RES =>
4602
            sig_RWn <= '1';
4603
            sig_RD <= '1';
4604
            ld_o <= "11";
4605
            ld_pc_o <= '1';
4606
 
4607
            ld_sp_o <= '1';
4608
            sig_RWn <= '1';
4609
            sig_RD <= '1';
4610
         WHEN s511 =>
4611
            IF (rdy_i = '1' and
4612
                zw_REG_OP = X"E5") THEN
4613
               ld_o <= "11";
4614
               ld_pc_o <= '1';
4615
            ELSIF (rdy_i = '1' and
4616
                   zw_REG_OP = X"E9" and
4617
                   reg_F(3) = '0') THEN
4618
               ld_o <= "11";
4619
               ld_pc_o <= '1';
4620
               d_regs_in_o <= zw_ALU(7 downto 0);
4621
               load_regs_o <= '1';
4622
               zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
4623
               sig_SYNC <= '1';
4624
            ELSIF (rdy_i = '1' and
4625
                   zw_REG_OP = X"F5") THEN
4626
               ch_a_o <=  d_i;
4627
               ch_b_o <= q_x_i;
4628
            ELSIF (rdy_i = '1' and
4629
                   zw_REG_OP = X"ED") THEN
4630
               ld_o <= "11";
4631
               ld_pc_o <= '1';
4632
            ELSIF (rdy_i = '1' and
4633
                   zw_REG_OP = X"FD") THEN
4634
               ld_o <= "11";
4635
               ld_pc_o <= '1';
4636
               ch_a_o <= d_i;
4637
               ch_b_o <= q_x_i;
4638
            ELSIF (rdy_i = '1' and
4639
                   zw_REG_OP = X"F9") THEN
4640
               ld_o <= "11";
4641
               ld_pc_o <= '1';
4642
               ch_a_o <= d_i;
4643
               ch_b_o <= q_y_i;
4644
            ELSIF (rdy_i = '1' and
4645
                   zw_REG_OP = X"F1") THEN
4646
               ch_a_o <= d_i;
4647
               ch_b_o <= X"01";
4648
            ELSIF (rdy_i = '1' and
4649
                   zw_REG_OP = X"E1") THEN
4650
               ch_a_o <=  d_i;
4651
               ch_b_o <= q_x_i;
4652
            ELSIF (rdy_i = '1' and
4653
                   zw_REG_OP = X"E9" and
4654
                   reg_F(3) = '1') THEN
4655
               ld_o <= "11";
4656
               ld_pc_o <= '1';
4657
               d_regs_in_o <= zw_ALU(7 downto 0);
4658
               load_regs_o <= '1';
4659
               zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
4660
               zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
4661
 
4662
               zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
4663
               zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
4664
 
4665
               zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
4666
               zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
4667
 
4668
               zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
4669
               zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
4670
               sig_SYNC <= '1';
4671
            END IF;
4672
         WHEN s559 =>
4673
            IF (rdy_i = '1') THEN
4674
               ld_o <= "11";
4675
               ld_pc_o <= '1';
4676
            END IF;
4677
         WHEN s562 =>
4678
            IF (rdy_i = '1') THEN
4679
               ch_a_o <= d_i;
4680
               ch_b_o <= X"01";
4681
               ld_o <= "11";
4682
               ld_pc_o <= '1';
4683
            END IF;
4684
         WHEN s567 =>
4685
            IF (rdy_i = '1') THEN
4686
               ch_a_o <= d_i;
4687
               ch_b_o <= X"01";
4688
               ld_o <= "11";
4689
               ld_pc_o <= '1';
4690
            END IF;
4691
         WHEN s568 =>
4692
            IF (rdy_i = '1') THEN
4693
               ch_a_o <= d_i;
4694
               ch_b_o <= q_y_i;
4695
            END IF;
4696
         WHEN s569 =>
4697
            IF (rdy_i = '1') THEN
4698
               ld_o <= "11";
4699
               ld_pc_o <= '1';
4700
            END IF;
4701
         WHEN s571 =>
4702
            IF (rdy_i = '1') THEN
4703
               ch_a_o <= d_i;
4704
               ch_b_o <= X"01";
4705
               ld_o <= "11";
4706
               ld_pc_o <= '1';
4707
            END IF;
4708
         WHEN s572 =>
4709
            IF (rdy_i = '1') THEN
4710
               ch_a_o <=  zw_b1;
4711
               ch_b_o <= X"01";
4712
            END IF;
4713
         WHEN s573 =>
4714
            IF (rdy_i = '1' AND
4715
                zw_b2(0) = '0' and
4716
                reg_F(3) = '0') THEN
4717
               d_regs_in_o <= zw_ALU(7 downto 0);
4718
               load_regs_o <= '1';
4719
               zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
4720
               sig_SYNC <= '1';
4721
            ELSIF (rdy_i = '1' AND
4722
                   zw_b2(0) = '0' and
4723
                   reg_F(3) = '1') THEN
4724
               d_regs_in_o <= zw_ALU(7 downto 0);
4725
               load_regs_o <= '1';
4726
               zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
4727
               zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
4728
 
4729
               zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
4730
               zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
4731
 
4732
               zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
4733
               zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
4734
 
4735
               zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
4736
               zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
4737
               sig_SYNC <= '1';
4738
            END IF;
4739
         WHEN s574 =>
4740
            IF (rdy_i = '1' and
4741
                reg_F(3) = '0') THEN
4742
               d_regs_in_o <= zw_ALU(7 downto 0);
4743
               load_regs_o <= '1';
4744
               zw_ALU <= unsigned ('0' & q_a_i) + unsigned ('0' & NOT (d_i)) + reg_F(0);
4745
               sig_SYNC <= '1';
4746
            ELSIF (rdy_i = '1' and
4747
                   reg_F(3) = '1') THEN
4748
               d_regs_in_o <= zw_ALU(7 downto 0);
4749
               load_regs_o <= '1';
4750
               zw_ALU(7 downto 4) <= unsigned (zw_ALU2(3 downto 0)) + unsigned (zw_ALU6);
4751
               zw_ALU(3 downto 0) <= unsigned (zw_ALU1(3 downto 0)) + unsigned (zw_ALU5);
4752
 
4753
               zw_ALU6 <= (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0' & (zw_ALU4(4) OR NOT (zw_ALU2(4))) & '0';
4754
               zw_ALU5 <= (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' & (zw_ALU3(4) OR NOT (zw_ALU1(4))) & '0' ;
4755
 
4756
               zw_ALU4 <= unsigned ('0' & zw_ALU2(3 downto 0)) + 6;
4757
               zw_ALU2 <= unsigned ('0' & q_a_i(7 downto 4)) + unsigned ('0' & NOT (d_i(7 downto 4))) + zw_ALU1(4);
4758
 
4759
               zw_ALU3 <= unsigned ('0' & zw_ALU1(3 downto 0)) + 6;
4760
               zw_ALU1 <= unsigned ('0' & q_a_i(3 downto 0)) + unsigned ('0' & NOT (d_i(3 downto 0))) + reg_F(0);
4761
               sig_SYNC <= '1';
4762
            END IF;
4763
         WHEN s548 =>
4764
            IF (rdy_i = '1') THEN
4765
               ld_o <= "11";
4766
               ld_sp_o <= '1';
4767
               sig_RWn <= '0';
4768
               sig_RD <= '0';
4769
               sig_WR <= '1';
4770
               sig_D_OUT <= adr_pc_i (15 downto 8);
4771
            END IF;
4772
         WHEN s551 =>
4773
            ld_o <= "11";
4774
            ld_sp_o <= '1';
4775
            sig_RWn <= '0';
4776
            sig_RD <= '0';
4777
            sig_WR <= '1';
4778
            sig_D_OUT <= adr_pc_i (7 downto 0);
4779
         WHEN s552 =>
4780
            ld_o <= "11";
4781
            ld_sp_o <= '1';
4782
            sig_RWn <= '0';
4783
            sig_RD <= '0';
4784
            sig_WR <= '1';
4785
            sig_D_OUT <= reg_F;
4786
         WHEN s576 =>
4787
            IF (NMI_i = '1') THEN
4788
               rst_nmi_o <= '1';
4789
            END IF;
4790
         WHEN s577 =>
4791
            IF (rdy_i = '1') THEN
4792
               adr_o <= d_i & zw_b1;
4793
               ld_o <= "11";
4794
               ld_pc_o <= '1';
4795
               sig_SYNC <= '1';
4796
            END IF;
4797
         WHEN OTHERS =>
4798
            NULL;
4799
      END CASE;
4800
   END PROCESS output_proc;
4801
 
4802
   -- Concurrent Statements
4803
   -- Clocked output assignments
4804
   d_o <= d_o_cld;
4805
   rd_o <= rd_o_cld;
4806
   sync_o <= sync_o_cld;
4807
   wr_n_o <= wr_n_o_cld;
4808
   wr_o <= wr_o_cld;
4809
END fsm;

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