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-- VHDL Entity R6502_TC.Reg_PC.symbol

--

-- Created:

--          by - eda.UNKNOWN (TEST)

--          at - 19:25:31 10.02.2009

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

--

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ENTITY Reg_PC IS

   PORT(

      adr_i        : IN     std_logic_vector (15 DOWNTO 0);

      clk_clk_i    : IN     std_logic;

      ld_i         : IN     std_logic_vector (1 DOWNTO 0);

      ld_pc_i      : IN     std_logic;

      offset_i     : IN     std_logic_vector (15 DOWNTO 0);

      rst_rst_n_i  : IN     std_logic;

      sel_pc_in_i  : IN     std_logic;

      sel_pc_val_i : IN     std_logic_vector (1 DOWNTO 0);

      adr_nxt_pc_o : OUT    std_logic_vector (15 DOWNTO 0);

      adr_pc_o     : OUT    std_logic_vector (15 DOWNTO 0)

   );

-- Declarations

END Reg_PC ;

-- Jens-D. Gutschmidt     Project:  R6502_TC  

-- scantara2003@yahoo.de                      

-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG                                                                                

--                                                                                                                                             

-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by   

-- the Free Software Foundation, either version 3 of the License, or any later version.                                                        

--                                                                                                                                             

-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of              

-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.                                  

--                                                                                                                                             

-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.     

--                                                                                                                                             

-- CVS Revisins History                                                                                                                        

--                                                                                                                                             

-- $Log: not supported by cvs2svn $                                                                                                                         

--   <<-- more -->>                                                                                                                            

-- Title:  Program Counter Logic  

-- Path:  R6502_TC/Reg_PC/struct  

-- Edited:  by eda on 10 Feb 2009  

--

-- VHDL Architecture R6502_TC.Reg_PC.struct

--

-- Created:

--          by - eda.UNKNOWN (TEST)

--          at - 19:25:32 10.02.2009

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

--

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ARCHITECTURE struct OF Reg_PC IS

   -- Architecture declarations

   -- Internal signal declarations

   SIGNAL adr_pc_high_o_i : std_logic_vector(7 DOWNTO 0);

   SIGNAL adr_pc_low_o_i  : std_logic_vector(7 DOWNTO 0);

   SIGNAL adr_pc_o_i      : std_logic_vector(15 DOWNTO 0);

   SIGNAL ci_o_i          : std_logic;

   SIGNAL cout_pc_o_i     : std_logic;

   SIGNAL load3_o_i       : std_logic;

   SIGNAL load_o_i        : std_logic;

   SIGNAL offset_high_o_i : std_logic_vector(7 DOWNTO 0);

   SIGNAL offset_low_o_i  : std_logic_vector(7 DOWNTO 0);

   SIGNAL val_o_i         : std_logic_vector(7 DOWNTO 0);

   SIGNAL val_one         : std_logic_vector(7 DOWNTO 0);

   SIGNAL val_zero        : std_logic_vector(7 DOWNTO 0);

   -- Implicit buffer signal declarations

   SIGNAL adr_pc_o_internal     : std_logic_vector (15 DOWNTO 0);

   SIGNAL adr_nxt_pc_o_internal : std_logic_vector (15 DOWNTO 0);

   -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'

   SIGNAL mw_U_0reg_cval : std_logic_vector(7 DOWNTO 0);

   -- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'

   SIGNAL mw_U_4reg_cval : std_logic_vector(7 DOWNTO 0);

   -- ModuleWare signal declarations(v1.9) for instance 'U_3' of 'split'

   SIGNAL mw_U_3temp_din : std_logic_vector(15 DOWNTO 0);

   -- ModuleWare signal declarations(v1.9) for instance 'U_5' of 'split'

   SIGNAL mw_U_5temp_din : std_logic_vector(15 DOWNTO 0);

BEGIN

   -- ModuleWare code(v1.9) for instance 'U_2' of 'add'

   u_2combo_proc: PROCESS (adr_pc_low_o_i, val_o_i)

   VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);

   VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);

   VARIABLE temp_sum : unsigned(8 DOWNTO 0);

   VARIABLE temp_carry : std_logic;

   BEGIN

      temp_din0 := '0' & adr_pc_low_o_i;

      temp_din1 := '0' & val_o_i;

      temp_carry := '0';

      temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;

      adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);

      cout_pc_o_i <= temp_sum(8) ;

   END PROCESS u_2combo_proc;

   -- ModuleWare code(v1.9) for instance 'U_11' of 'add'

   u_11combo_proc: PROCESS (adr_pc_high_o_i, offset_high_o_i, ci_o_i)

   VARIABLE temp_din0 : std_logic_vector(8 DOWNTO 0);

   VARIABLE temp_din1 : std_logic_vector(8 DOWNTO 0);

   VARIABLE temp_sum : unsigned(8 DOWNTO 0);

   VARIABLE temp_carry : std_logic;

   BEGIN

      temp_din0 := '0' & adr_pc_high_o_i;

      temp_din1 := '0' & offset_high_o_i;

      temp_carry := ci_o_i;

      temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;

      adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(temp_sum(7 DOWNTO 0),8);

   END PROCESS u_11combo_proc;

   -- ModuleWare code(v1.9) for instance 'U_0' of 'adff'

   adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;

   u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)

   BEGIN

      IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN

         mw_U_0reg_cval <= "00000000";

      ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN

         IF (load_o_i = '1' OR load_o_i = 'H') THEN

            mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0);

         END IF;

      END IF;

   END PROCESS u_0seq_proc;

   -- ModuleWare code(v1.9) for instance 'U_4' of 'adff'

   adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval;

   u_4seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)

   BEGIN

      IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN

         mw_U_4reg_cval <= "00000000";

      ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN

         IF (load3_o_i = '1' OR load3_o_i = 'H') THEN

            mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8);

         END IF;

      END IF;

   END PROCESS u_4seq_proc;

   -- ModuleWare code(v1.9) for instance 'U_6' of 'and'

   load_o_i <= ld_pc_i AND ld_i(0);

   -- ModuleWare code(v1.9) for instance 'U_7' of 'and'

   load3_o_i <= ld_pc_i AND ld_i(1);

   -- ModuleWare code(v1.9) for instance 'U_10' of 'and'

   ci_o_i <= cout_pc_o_i AND ld_pc_i;

   -- ModuleWare code(v1.9) for instance 'U_1' of 'constval'

   val_zero <= "00000000";

   -- ModuleWare code(v1.9) for instance 'U_9' of 'constval'

   val_one <= "00000001";

   -- ModuleWare code(v1.9) for instance 'U_8' of 'mux'

   u_8combo_proc: PROCESS(adr_pc_o_internal, adr_i, sel_pc_in_i)

   BEGIN

      CASE sel_pc_in_i IS

      WHEN '0'|'L' => adr_pc_o_i <= adr_pc_o_internal;

      WHEN '1'|'H' => adr_pc_o_i <= adr_i;

      WHEN OTHERS => adr_pc_o_i <= (OTHERS => 'X');

      END CASE;

   END PROCESS u_8combo_proc;

   -- ModuleWare code(v1.9) for instance 'U_13' of 'mux'

   u_13combo_proc: PROCESS(val_one, val_zero, offset_low_o_i,

                           sel_pc_val_i)

   BEGIN

      CASE sel_pc_val_i IS

      WHEN "00"|"L0"|"0L"|"LL" => val_o_i <= val_one;

      WHEN "01"|"L1"|"0H"|"LH" => val_o_i <= val_zero;

      WHEN "10"|"H0"|"1L"|"HL" => val_o_i <= offset_low_o_i;

      WHEN "11"|"H1"|"1H"|"HH" => val_o_i <= val_zero;

      WHEN OTHERS => val_o_i <= (OTHERS => 'X');

      END CASE;

   END PROCESS u_13combo_proc;

   -- ModuleWare code(v1.9) for instance 'U_3' of 'split'

   mw_U_3temp_din <= adr_pc_o_i;

   u_3combo_proc: PROCESS (mw_U_3temp_din)

   VARIABLE temp_din: std_logic_vector(15 DOWNTO 0);

   BEGIN

      temp_din := mw_U_3temp_din(15 DOWNTO 0);

      adr_pc_low_o_i <= temp_din(7 DOWNTO 0);

      adr_pc_high_o_i <= temp_din(15 DOWNTO 8);

   END PROCESS u_3combo_proc;

   -- ModuleWare code(v1.9) for instance 'U_5' of 'split'

   mw_U_5temp_din <= offset_i;

   u_5combo_proc: PROCESS (mw_U_5temp_din)

   VARIABLE temp_din: std_logic_vector(15 DOWNTO 0);

   BEGIN

      temp_din := mw_U_5temp_din(15 DOWNTO 0);

      offset_low_o_i <= temp_din(7 DOWNTO 0);

      offset_high_o_i <= temp_din(15 DOWNTO 8);

   END PROCESS u_5combo_proc;

   -- Instance port mappings.

   -- Implicit buffered output assignments

   adr_pc_o     <= adr_pc_o_internal;

   adr_nxt_pc_o <= adr_nxt_pc_o_internal;

END struct;