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[/] [cpu6502_true_cycle/] [trunk/] [rtl/] [vhdl/] [reg_pc.vhd] - Blame information for rev 2

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1 2 fpga_is_fu
-- VHDL Entity R6502_TC.Reg_PC.symbol
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--
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-- Created:
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--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
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--          at - 19:06:52 08.04.2008
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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entity Reg_PC is
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   port(
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      adr_i        : in     std_logic_vector (15 downto 0);
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      clk_clk_i    : in     std_logic;
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      ld_i         : in     std_logic_vector (1 downto 0);
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      ld_pc_i      : in     std_logic;
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      offset_i     : in     std_logic_vector (15 downto 0);
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      rst_rst_i    : in     std_logic;
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      sel_pc_as_i  : in     std_logic;
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      sel_pc_in_i  : in     std_logic;
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      sel_pc_val_i : in     std_logic_vector (1 downto 0);
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      adr_nxt_pc_o : out    std_logic_vector (15 downto 0);
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      adr_pc_o     : out    std_logic_vector (15 downto 0);
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      cout_pc_o    : out    std_logic
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   );
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-- Declarations
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end Reg_PC ;
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-- Jens-D. Gutschmidt     Project:  R6502_TC  
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-- scantara2003@yahoo.de                      
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-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG                                                                                     
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--                                                                                                                                             
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by   
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-- the Free Software Foundation, either version 3 of the License, or any later version.                                                        
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--                                                                                                                                             
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of              
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.                                  
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--                                                                                                                                             
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-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.     
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--                                                                                                                                             
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-- CVS Revisins History                                                                                                                        
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--                                                                                                                                             
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-- $Log: not supported by cvs2svn $                                                                                                                                       
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--                                                                                                                                             
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-- Title:  Program Counter Logic  
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-- Path:  R6502_TC/Reg_PC/struct  
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-- Edited:  by eda on 08 Apr 2008  
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--
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-- VHDL Architecture R6502_TC.Reg_PC.struct
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--
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-- Created:
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--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)
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--          at - 19:06:53 08.04.2008
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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architecture struct of Reg_PC is
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   -- Architecture declarations
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   -- Internal signal declarations
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   signal d        : std_logic_vector(7 downto 0);
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   signal d1       : std_logic_vector(7 downto 0);
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   signal dout     : std_logic;
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   signal dout1    : std_logic_vector(7 downto 0);
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   signal dout3    : std_logic;
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   signal dout5    : std_logic_vector(7 downto 0);
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   signal dout6    : std_logic_vector(7 downto 0);
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   signal load     : std_logic;
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   signal load3    : std_logic;
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   signal val_one  : std_logic_vector(7 downto 0);
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   signal val_two  : std_logic_vector(7 downto 0);
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   signal val_zero : std_logic_vector(7 downto 0);
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   -- Implicit buffer signal declarations
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   signal adr_pc_o_internal  : std_logic_vector (15 downto 0);
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   signal cout_pc_o_internal : std_logic;
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   -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'
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   signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
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   -- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'
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   signal mw_U_4reg_cval : std_logic_vector(7 downto 0);
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begin
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   -- Architecture concurrent statements
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   -- HDL Embedded Text Block 1 eb1
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   -- eb1 1
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   adr_nxt_pc_o(7 DOWNTO 0) <= d;
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   -- HDL Embedded Text Block 2 eb2
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   -- eb1 1
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   val_zero (7 downto 0) <= X"00";
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   val_one (7 downto 0) <= X"01";
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   val_two (7 downto 0) <= X"02";
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   -- HDL Embedded Text Block 3 eb3
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   -- eb1 1
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   adr_nxt_pc_o(15 DOWNTO 8) <= d1;
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   -- ModuleWare code(v1.9) for instance 'U_11' of 'addsub'
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   u_11combo_proc: process (dout5, dout1, dout3, val_zero(0))
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   variable temp_din0 : std_logic_vector(8 downto 0);
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   variable temp_din1 : std_logic_vector(8 downto 0);
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   variable temp_sum : unsigned(8 downto 0);
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   variable temp_carry : std_logic;
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   variable temp_cout : std_logic;
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   begin
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      temp_din0 := '0' & dout5;
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      temp_din1 := '0' & dout1;
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      temp_carry := val_zero(0);
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      if (dout3 = '1') then
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         temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
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         temp_cout := temp_sum(8) ;
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      else
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         temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry;
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         temp_cout := temp_sum(8) ;
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      end if;
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      d <= conv_std_logic_vector(temp_sum(7 downto 0),8);
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      cout_pc_o_internal <= temp_cout;
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   end process u_11combo_proc;
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   -- ModuleWare code(v1.9) for instance 'U_12' of 'addsub'
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   u_12combo_proc: process (dout6, offset_i(15 DOWNTO 8), dout3, dout)
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   variable temp_din0 : std_logic_vector(8 downto 0);
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   variable temp_din1 : std_logic_vector(8 downto 0);
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   variable temp_sum : unsigned(8 downto 0);
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   variable temp_carry : std_logic;
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   begin
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      temp_din0 := '0' & dout6;
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      temp_din1 := '0' & offset_i(15 DOWNTO 8);
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      temp_carry := dout;
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      if (dout3 = '1') then
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         temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
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      else
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         temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry;
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      end if;
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      d1 <= conv_std_logic_vector(temp_sum(7 downto 0),8);
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   end process u_12combo_proc;
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   -- ModuleWare code(v1.9) for instance 'U_0' of 'adff'
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   adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
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   u_0seq_proc: process (clk_clk_i, rst_rst_i)
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   begin
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      if (rst_rst_i = '1') then
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         mw_U_0reg_cval <= "00000000";
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      elsif (clk_clk_i'event and clk_clk_i='1') then
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         if (load = '1') then
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            mw_U_0reg_cval <= d;
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         end if;
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      end if;
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   end process u_0seq_proc;
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   -- ModuleWare code(v1.9) for instance 'U_4' of 'adff'
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   adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval;
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   u_4seq_proc: process (clk_clk_i, rst_rst_i)
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   begin
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      if (rst_rst_i = '1') then
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         mw_U_4reg_cval <= "00000000";
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      elsif (clk_clk_i'event and clk_clk_i='1') then
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         if (load3 = '1') then
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            mw_U_4reg_cval <= d1;
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         end if;
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      end if;
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   end process u_4seq_proc;
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   -- ModuleWare code(v1.9) for instance 'U_6' of 'and'
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   load <= ld_pc_i and ld_i(0);
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   -- ModuleWare code(v1.9) for instance 'U_7' of 'and'
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   load3 <= ld_pc_i and ld_i(1);
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   -- ModuleWare code(v1.9) for instance 'U_10' of 'and'
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   dout <= cout_pc_o_internal and ld_pc_i;
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   -- ModuleWare code(v1.9) for instance 'U_2' of 'inv'
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   dout3 <= not(sel_pc_as_i);
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   -- ModuleWare code(v1.9) for instance 'U_5' of 'mux'
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   u_5combo_proc: process(val_one, val_two, offset_i(7 DOWNTO 0),
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                          val_zero, sel_pc_val_i)
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   begin
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      case sel_pc_val_i is
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      when "00" => dout1 <= val_one;
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      when "01" => dout1 <= val_two;
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      when "10" => dout1 <= offset_i(7 DOWNTO 0);
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      when "11" => dout1 <= val_zero;
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      when others => dout1 <= (others => 'X');
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      end case;
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   end process u_5combo_proc;
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   -- ModuleWare code(v1.9) for instance 'U_8' of 'mux'
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   u_8combo_proc: process(adr_pc_o_internal(7 DOWNTO 0),
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                          adr_i(7 DOWNTO 0), sel_pc_in_i)
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   begin
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      case sel_pc_in_i is
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      when '0' => dout5 <= adr_pc_o_internal(7 DOWNTO 0);
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      when '1' => dout5 <= adr_i(7 DOWNTO 0);
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      when others => dout5 <= (others => 'X');
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      end case;
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   end process u_8combo_proc;
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   -- ModuleWare code(v1.9) for instance 'U_9' of 'mux'
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   u_9combo_proc: process(adr_pc_o_internal(15 DOWNTO 8),
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                          adr_i(15 DOWNTO 8), sel_pc_in_i)
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   begin
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      case sel_pc_in_i is
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      when '0' => dout6 <= adr_pc_o_internal(15 DOWNTO 8);
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      when '1' => dout6 <= adr_i(15 DOWNTO 8);
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      when others => dout6 <= (others => 'X');
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      end case;
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   end process u_9combo_proc;
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   -- Instance port mappings.
227
 
228
   -- Implicit buffered output assignments
229
   adr_pc_o  <= adr_pc_o_internal;
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   cout_pc_o <= cout_pc_o_internal;
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end struct;

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