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-- VHDL Entity R6502_TC.RegBank_AXY.symbol

--

-- Created:

--          by - eda.UNKNOWN (TEST)

--          at - 19:25:32 10.02.2009

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

--

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ENTITY RegBank_AXY IS

   PORT(

      clk_clk_i    : IN     std_logic;

      d_regs_in_i  : IN     std_logic_vector (7 DOWNTO 0);

      load_regs_i  : IN     std_logic;

      rst_rst_n_i  : IN     std_logic;

      sel_rb_in_i  : IN     std_logic_vector (1 DOWNTO 0);

      sel_rb_out_i : IN     std_logic_vector (1 DOWNTO 0);

      sel_reg_i    : IN     std_logic_vector (1 DOWNTO 0);

      d_regs_out_o : OUT    std_logic_vector (7 DOWNTO 0);

      q_a_o        : OUT    std_logic_vector (7 DOWNTO 0);

      q_x_o        : OUT    std_logic_vector (7 DOWNTO 0);

      q_y_o        : OUT    std_logic_vector (7 DOWNTO 0)

   );

-- Declarations

END RegBank_AXY ;

-- Jens-D. Gutschmidt     Project:  R6502_TC  

-- scantara2003@yahoo.de                      

-- COPYRIGHT (C) 2008-2009 by Jens Gutschmidt and OPENCORES.ORG                                                                                

--                                                                                                                                             

-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by   

-- the Free Software Foundation, either version 3 of the License, or any later version.                                                        

--                                                                                                                                             

-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of              

-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.                                  

--                                                                                                                                             

-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.     

--                                                                                                                                             

-- CVS Revisins History                                                                                                                        

--                                                                                                                                             

-- $Log: not supported by cvs2svn $                                                                                                                         

--   <<-- more -->>                                                                                                                            

-- Title:  Register Bank for register A, X and Y  

-- Path:  R6502_TC/RegBank_AXY/struct  

-- Edited:  by eda on 10 Feb 2009  

--

-- VHDL Architecture R6502_TC.RegBank_AXY.struct

--

-- Created:

--          by - eda.UNKNOWN (TEST)

--          at - 19:25:32 10.02.2009

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

--

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

ARCHITECTURE struct OF RegBank_AXY IS

   -- Architecture declarations

   -- Internal signal declarations

   SIGNAL ld        : std_logic_vector(2 DOWNTO 0);

   SIGNAL load1_o_i : std_logic;

   SIGNAL load2_o_i : std_logic;

   SIGNAL load_o_i  : std_logic;

   SIGNAL q_mux_o_i : std_logic_vector(7 DOWNTO 0);

   SIGNAL val_zero  : std_logic_vector(7 DOWNTO 0);

   -- Implicit buffer signal declarations

   SIGNAL q_a_o_internal : std_logic_vector (7 DOWNTO 0);

   SIGNAL q_x_o_internal : std_logic_vector (7 DOWNTO 0);

   SIGNAL q_y_o_internal : std_logic_vector (7 DOWNTO 0);

   -- ModuleWare signal declarations(v1.9) for instance 'U_0' of 'adff'

   SIGNAL mw_U_0reg_cval : std_logic_vector(7 DOWNTO 0);

   -- ModuleWare signal declarations(v1.9) for instance 'U_4' of 'adff'

   SIGNAL mw_U_4reg_cval : std_logic_vector(7 DOWNTO 0);

   -- ModuleWare signal declarations(v1.9) for instance 'U_5' of 'adff'

   SIGNAL mw_U_5reg_cval : std_logic_vector(7 DOWNTO 0);

BEGIN

   -- ModuleWare code(v1.9) for instance 'U_0' of 'adff'

   q_a_o_internal <= mw_U_0reg_cval;

   u_0seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)

   BEGIN

      IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN

         mw_U_0reg_cval <= "00000000";

      ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN

         IF (load_o_i = '1' OR load_o_i = 'H') THEN

            mw_U_0reg_cval <= q_mux_o_i;

         END IF;

      END IF;

   END PROCESS u_0seq_proc;

   -- ModuleWare code(v1.9) for instance 'U_4' of 'adff'

   q_x_o_internal <= mw_U_4reg_cval;

   u_4seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)

   BEGIN

      IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN

         mw_U_4reg_cval <= "00000000";

      ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN

         IF (load1_o_i = '1' OR load1_o_i = 'H') THEN

            mw_U_4reg_cval <= q_mux_o_i;

         END IF;

      END IF;

   END PROCESS u_4seq_proc;

   -- ModuleWare code(v1.9) for instance 'U_5' of 'adff'

   q_y_o_internal <= mw_U_5reg_cval;

   u_5seq_proc: PROCESS (clk_clk_i, rst_rst_n_i)

   BEGIN

      IF (rst_rst_n_i = '0' OR rst_rst_n_i = 'L') THEN

         mw_U_5reg_cval <= "00000000";

      ELSIF (clk_clk_i'EVENT AND clk_clk_i='1') THEN

         IF (load2_o_i = '1' OR load2_o_i = 'H') THEN

            mw_U_5reg_cval <= q_mux_o_i;

         END IF;

      END IF;

   END PROCESS u_5seq_proc;

   -- ModuleWare code(v1.9) for instance 'U_6' of 'and'

   load_o_i <= load_regs_i AND ld(0);

   -- ModuleWare code(v1.9) for instance 'U_7' of 'and'

   load1_o_i <= load_regs_i AND ld(1);

   -- ModuleWare code(v1.9) for instance 'U_8' of 'and'

   load2_o_i <= load_regs_i AND ld(2);

   -- ModuleWare code(v1.9) for instance 'U_11' of 'constval'

   val_zero <= "00000000";

   -- ModuleWare code(v1.9) for instance 'U_1' of 'decoder1'

   u_1combo_proc: PROCESS (sel_reg_i)

   BEGIN

      ld <= (OTHERS => '0');

      CASE sel_reg_i IS

         WHEN "00" => ld(0) <= '1';

         WHEN "01" => ld(1) <= '1';

         WHEN "10" => ld(2) <= '1';

         WHEN OTHERS => ld <= (OTHERS => '0');

      END CASE;

   END PROCESS u_1combo_proc;

   -- ModuleWare code(v1.9) for instance 'U_2' of 'mux'

   u_2combo_proc: PROCESS(q_a_o_internal, q_x_o_internal, q_y_o_internal,

                          val_zero, sel_rb_out_i)

   BEGIN

      CASE sel_rb_out_i IS

      WHEN "00"|"L0"|"0L"|"LL" => d_regs_out_o <= q_a_o_internal;

      WHEN "01"|"L1"|"0H"|"LH" => d_regs_out_o <= q_x_o_internal;

      WHEN "10"|"H0"|"1L"|"HL" => d_regs_out_o <= q_y_o_internal;

      WHEN "11"|"H1"|"1H"|"HH" => d_regs_out_o <= val_zero;

      WHEN OTHERS => d_regs_out_o <= (OTHERS => 'X');

      END CASE;

   END PROCESS u_2combo_proc;

   -- ModuleWare code(v1.9) for instance 'U_3' of 'mux'

   u_3combo_proc: PROCESS(q_a_o_internal, q_y_o_internal, q_x_o_internal,

                          d_regs_in_i, sel_rb_in_i)

   BEGIN

      CASE sel_rb_in_i IS

      WHEN "00"|"L0"|"0L"|"LL" => q_mux_o_i <= q_a_o_internal;

      WHEN "01"|"L1"|"0H"|"LH" => q_mux_o_i <= q_y_o_internal;

      WHEN "10"|"H0"|"1L"|"HL" => q_mux_o_i <= q_x_o_internal;

      WHEN "11"|"H1"|"1H"|"HH" => q_mux_o_i <= d_regs_in_i;

      WHEN OTHERS => q_mux_o_i <= (OTHERS => 'X');

      END CASE;

   END PROCESS u_3combo_proc;

   -- Instance port mappings.

   -- Implicit buffered output assignments

   q_a_o <= q_a_o_internal;

   q_x_o <= q_x_o_internal;

   q_y_o <= q_y_o_internal;

END struct;