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BODY {     /* main_body */
  background:#FFFFFF;
  color:#000000;
}
 
/* verilog/vhdl language elements */
SPAN.C       { color:#0000FF; }                         /* comment */
SPAN.K       { color:#CC3300; }                         /* keyword */
SPAN.S       { color:#009900; }                         /* string  */
SPAN.T       { color:#660033; }                         /* type  */
SPAN.A       { color:RED; }                             /* attribute */
SPAN.D       { color:#AA0026; font-weight:bold; }       /* Compiler Directives */

Line No.	Rev	Author	Line
1	2	fpga_is_fu	`BODY { /* main_body */`
2			`background:#FFFFFF;`
3			`color:#000000;`
4			`}`
5
6			`/* verilog/vhdl language elements */`
7			`SPAN.C { color:#0000FF; } /* comment */`
8			`SPAN.K { color:#CC3300; } /* keyword */`
9			`SPAN.S { color:#009900; } /* string */`
10			`SPAN.T { color:#660033; } /* type */`
11			`SPAN.A { color:RED; } /* attribute */`
12			`SPAN.D { color:#AA0026; font-weight:bold; } /* Compiler Directives */`

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[/] [cpu65c02_true_cycle/] [branches/] [avendor/] [doc/] [HTML/] [scripts/] [hdl2html.css] - Blame information for rev 15