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-- VHDL Entity R65C02_TC.ALU.symbol

--

-- Created:

--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)

--          at - 20:01:56 12.08.2008

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

--

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

entity ALU is

   port(

      ch_a_i           : in     std_logic_vector (7 downto 0);

      ch_b_i           : in     std_logic_vector (7 downto 0);

      reg_0flag_core_i : in     std_logic;

      reg_3flag_core_i : in     std_logic;

      reg_7flag_core_i : in     std_logic;

      sel_alu_as_i     : in     std_logic;

      sel_alu_out_i    : in     std_logic_vector (2 downto 0);

      d_alu_o          : out    std_logic_vector (7 downto 0);

      reg_0flag_o      : out    std_logic;

      reg_1flag_o      : out    std_logic;

      reg_6flag_o      : out    std_logic;

      reg_7flag_o      : out    std_logic

   );

-- Declarations

end ALU ;

-- Jens-D. Gutschmidt     Project:  R65C02_TC  

-- scantara2003@yahoo.de                       

-- COPYRIGHT (C) 2008 by Jens Gutschmidt and OPENCORES.ORG                                                                                     

--                                                                                                                                             

-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by   

-- the Free Software Foundation, either version 3 of the License, or any later version.                                                        

--                                                                                                                                             

-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of              

-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.                                  

--                                                                                                                                             

-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.     

--                                                                                                                                             

-- CVS Revisins History                                                                                                                        

--                                                                                                                                             

-- $Log: not supported by cvs2svn $                                                                                                                                       

--                                                                                                                                             

-- Title:  ALU  

-- Path:  R65C02_TC/ALU/struct  

-- Edited:  by eda on 11 Aug 2008  

--

-- VHDL Architecture R65C02_TC.ALU.struct

--

-- Created:

--          by - eda.UNKNOWN (ENTWICKL4-XP-PR)

--          at - 20:01:57 12.08.2008

--

-- Generated by Mentor Graphics' HDL Designer(TM) 2007.1a (Build 13)

--

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE ieee.std_logic_arith.all;

library R65C02_TC;

architecture struct of ALU is

   -- Architecture declarations

   -- Internal signal declarations

   signal decode_neg_o_i : std_logic_vector(7 downto 0);

   signal decode_o_i     : std_logic_vector(7 downto 0);

   signal din0_o_i       : std_logic;

   signal din1_o_i       : std_logic;

   signal din2_o_i       : std_logic;

   signal din3_o_i       : std_logic;

   signal din_o_i        : std_logic;

   signal dout_o_i       : std_logic;

   signal q_a_o_i        : std_logic_vector(7 downto 0);

   signal q_and_o_i      : std_logic_vector(7 downto 0);

   signal q_or_o_i       : std_logic_vector(7 downto 0);

   signal q_xor_o_i      : std_logic_vector(7 downto 0);

   signal sel_o_i        : std_logic_vector(1 downto 0);

   signal val_one        : std_logic_vector(7 downto 0);

   signal val_two        : std_logic_vector(7 downto 0);

   signal val_zero       : std_logic_vector(7 downto 0);

   -- Implicit buffer signal declarations

   signal d_alu_o_internal : std_logic_vector (7 downto 0);

   -- Component Declarations

   component ADD_SUB

   port (

      d_in      : in     std_logic_vector ( 7 downto 0 ) := X"00";

      reg_0F_in : in     std_logic                       := '0';

      reg_7F_in : in     std_logic                       := '0';

      reg_a_in  : in     std_logic_vector ( 7 downto 0 ) := X"00";

      sel       : in     std_logic_vector ( 1 downto 0 ) := "00";

      reg_0F    : out    std_logic                       := '0';

      reg_6F    : out    std_logic                       := '0';

      reg_a     : out    std_logic_vector ( 7 downto 0 ) := X"00";

      zw_alu    : inout  std_logic_vector ( 8 downto 0 ) := '0' & X"00";

      zw_alu1   : inout  std_logic_vector ( 8 downto 0 ) := '0' & X"00";

      zw_alu2   : inout  std_logic_vector ( 8 downto 0 ) := '0' & X"00";

      zw_alu3   : inout  std_logic_vector ( 8 downto 0 ) := '0' & X"00";

      zw_alu4   : inout  std_logic_vector ( 8 downto 0 ) := '0' & X"00"

   );

   end component;

   -- Optional embedded configurations

   -- pragma synthesis_off

   for all : ADD_SUB use entity R65C02_TC.ADD_SUB;

   -- pragma synthesis_on

begin

   -- Architecture concurrent statements

   -- HDL Embedded Text Block 3 eb3

   -- eb1 1

   val_zero (7 downto 0) <= X"00";

   val_one (7 downto 0) <= X"01";

   val_two (7 downto 0) <= X"02";

   sel_o_i(0) <= reg_3flag_core_i AND sel_alu_out_i(0);

   sel_o_i(1) <= sel_alu_as_i;

   -- ModuleWare code(v1.9) for instance 'U_15' of 'decoder1'

   u_15combo_proc: process (ch_a_i(2 DOWNTO 0))

   begin

      decode_o_i <= (others => '0');

      case ch_a_i(2 DOWNTO 0) is

         when "000" => decode_o_i(0) <= '1';

         when "001" => decode_o_i(1) <= '1';

         when "010" => decode_o_i(2) <= '1';

         when "011" => decode_o_i(3) <= '1';

         when "100" => decode_o_i(4) <= '1';

         when "101" => decode_o_i(5) <= '1';

         when "110" => decode_o_i(6) <= '1';

         when "111" => decode_o_i(7) <= '1';

         when others => decode_o_i <= (others => '0');

      end case;

   end process u_15combo_proc;

   -- ModuleWare code(v1.9) for instance 'U_4' of 'inv'

   decode_neg_o_i <= not(decode_o_i);

   -- ModuleWare code(v1.9) for instance 'U_8' of 'inv'

   reg_1flag_o <= not(din_o_i);

   -- ModuleWare code(v1.9) for instance 'U_9' of 'inv'

   reg_7flag_o <= not(din1_o_i);

   -- ModuleWare code(v1.9) for instance 'U_10' of 'inv'

   din1_o_i <= not(d_alu_o_internal(7));

   -- ModuleWare code(v1.9) for instance 'U_14' of 'inv'

   din3_o_i <= not(sel_alu_out_i(0));

   -- ModuleWare code(v1.9) for instance 'U_5' of 'mux'

   u_5combo_proc: process(q_and_o_i, q_or_o_i, q_xor_o_i, decode_o_i,

                          decode_neg_o_i, q_a_o_i, val_zero,

                          sel_alu_out_i)

   begin

      case sel_alu_out_i is

      when "000" => d_alu_o_internal <= q_and_o_i;

      when "001" => d_alu_o_internal <= q_or_o_i;

      when "010" => d_alu_o_internal <= q_xor_o_i;

      when "011" => d_alu_o_internal <= decode_o_i;

      when "100" => d_alu_o_internal <= decode_neg_o_i;

      when "101" => d_alu_o_internal <= q_a_o_i;

      when "110" => d_alu_o_internal <= q_a_o_i;

      when "111" => d_alu_o_internal <= val_zero;

      when others => d_alu_o_internal <= (others => 'X');

      end case;

   end process u_5combo_proc;

   -- ModuleWare code(v1.9) for instance 'U_7' of 'por'

   din_o_i <= d_alu_o_internal(0) or  d_alu_o_internal(1) or  d_alu_o_internal(2) or  d_alu_o_internal(3) or  d_alu_o_internal(4) or  d_alu_o_internal(5) or  d_alu_o_internal(6) or  d_alu_o_internal(7);

   -- ModuleWare code(v1.9) for instance 'U_0' of 'sand'

   q_and_o_i <= ch_a_i and ch_b_i;

   -- ModuleWare code(v1.9) for instance 'U_11' of 'sand'

   din0_o_i <= sel_alu_out_i(0) and reg_0flag_core_i;

   -- ModuleWare code(v1.9) for instance 'U_13' of 'sand'

   din2_o_i <= din3_o_i and sel_alu_as_i;

   -- ModuleWare code(v1.9) for instance 'U_1' of 'sor'

   q_or_o_i <= ch_a_i or ch_b_i;

   -- ModuleWare code(v1.9) for instance 'U_12' of 'sor'

   dout_o_i <= din0_o_i or din2_o_i;

   -- ModuleWare code(v1.9) for instance 'U_2' of 'sxor'

   q_xor_o_i <= ch_a_i xor ch_b_i;

   -- Instance port mappings.

   U_6 : ADD_SUB

      port map (

         d_in      => ch_b_i,

         reg_0F_in => dout_o_i,

         reg_7F_in => reg_7flag_core_i,

         reg_a_in  => ch_a_i,

         sel       => sel_o_i,

         reg_0F    => reg_0flag_o,

         reg_6F    => reg_6flag_o,

         reg_a     => q_a_o_i,

         zw_alu    => open,

         zw_alu1   => open,

         zw_alu2   => open,

         zw_alu3   => open,

         zw_alu4   => open

      );

   -- Implicit buffered output assignments

   d_alu_o <= d_alu_o_internal;

end struct;