URL https://opencores.org/ocsvn/cpu65c02_true_cycle/cpu65c02_true_cycle/trunk

Subversion Repositories cpu65c02_true_cycle

[/] [cpu65c02_true_cycle/] [tags/] [arelease/] [TO_DO_list.txt] - Blame information for rev 15

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(August, 5th 2008)
- (DONE) Rename all port names (_i, _o, _o_i)
- (DONE) Test and verify all Op Codes
- (DONE) Optimize core for speed
- (DONE) Implement same improvements like cpu6502_tc (graphical design, source
  utilisation...)
- (75%) Finish working for Specification of cpu65C02_tc
- Create high level testbench in assembler and hardware for
  testing all Op Codes (include accurate cycle timing)
- Create simulation files for Modelsim
- Create a simple .wlf file to demonstrate the cpu65C02_tc
- Update the HDL Designer files for better viewing and understanding

Line No.	Rev	Author	Line
1	2	fpga_is_fu	`(August, 5th 2008)`
2	4	fpga_is_fu	`- (DONE) Rename all port names (_i, _o, _o_i)`
3			`- (DONE) Test and verify all Op Codes`
4			`- (DONE) Optimize core for speed`
5			`- (DONE) Implement same improvements like cpu6502_tc (graphical design, source`
6	2	fpga_is_fu	`utilisation...)`
7	4	fpga_is_fu	`- (75%) Finish working for Specification of cpu65C02_tc`
8	2	fpga_is_fu	`- Create high level testbench in assembler and hardware for`
9			`testing all Op Codes (include accurate cycle timing)`
10			`- Create simulation files for Modelsim`
11			`- Create a simple .wlf file to demonstrate the cpu65C02_tc`
12			`- Update the HDL Designer files for better viewing and understanding`

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Subversion Repositories cpu65c02_true_cycle

[/] [cpu65c02_true_cycle/] [tags/] [arelease/] [TO_DO_list.txt] - Blame information for rev 15