Subversion Repositories cpu65c02_true_cycle

(September 09th 2018)

- (WORKING) Performance improvements

- (WORKING) Creating test strategy for RDY signal

- (DONE) Working on reported Bugs/Requests: JMP, Branches, Interrupts, ADC/SBC

- (DONE) Verifying all interrupts

- (90%)  Finish working for Specification of cpu65C02_tc

(July 31th 2013)

- (DONE) Transfer the project state from "BETA" to "RELEASE CANDIDATE"

- (DONE) Offer a high level testbench in assembler for testing all Op Codes

         Including Klaus Dormann's "65c02_*_test" suite

- (DONE) Because of translation errors the Verilog sources are no longer

         available

- (DONE) Create "golden" simulation files for Modelsim/QuestaSim

- (75%)  Finish working for Specification of cpu65C02_tc

- (85%)  Finish working for Specification of cpu65C02_tc

(February 25th 2009)

- (DONE) CORRECTED "RTI" (wrong: use of stack pointer)

- (DONE) CORRECTED "RMBx" & "SMBx" (wrong: bit translation)

- (DONE) RENAME all states of "FSM Execution Unit" for better reading

- (85%) Finish working for Specification of cpu65C02_tc

- (DONE) CORRECT timing for addressing mode "ABS,X" for "INC" (wrong: 6 cycles

         instead of 7)

- (DONE) OPTIMIZE end states of "STA" (s197,s207,s200,s213)

(January, 4th 2009)

- (DONE) Remove unused nets, register and modules

- (DONE) Update the HDL Designer files for better viewing and

  understanding

(August, 5th 2008)

- (DONE) Rename all port names (_i, _o, _o_i)

- (DONE) Test and verify all Op Codes

- (DONE) Optimize core for speed

- (DONE) Implement same improvements like cpu6502_tc (graphical design, source

  utilisation...)

- (75%) Finish working for Specification of cpu65C02_tc

- (WORKING) Create high level testbench in assembler and hardware for

  testing all Op Codes (include accurate cycle timing)

- (WORKING) Create simulation files for Modelsim

- (WORKING) Create a simple .wlf file to demonstrate the cpu65C02_tc

- Update the HDL Designer files for better viewing and understanding