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23 |
fpga_is_fu |
(October 15th 2018)
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| 2 |
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- (DONE) Add seperated area for BETA and RELEASE CANDIDATES
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| 3 |
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- (DONE) Performance improvements
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| 4 |
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- (WORKING) Creating test strategy for RDY signal
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| 5 |
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- (DONE) Finish working for Specification of cpu65C02_tc
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| 6 |
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| 7 |
20 |
fpga_is_fu |
(September 09th 2018)
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| 8 |
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- (WORKING) Performance improvements
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| 9 |
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- (WORKING) Creating test strategy for RDY signal
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| 10 |
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- (DONE) Working on reported Bugs/Requests: JMP, Branches, Interrupts, ADC/SBC
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| 11 |
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- (DONE) Verifying all interrupts
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| 12 |
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- (90%) Finish working for Specification of cpu65C02_tc
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| 13 |
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| 14 |
18 |
fpga_is_fu |
(July 31th 2013)
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| 15 |
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- (DONE) Transfer the project state from "BETA" to "RELEASE CANDIDATE"
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| 16 |
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- (DONE) Offer a high level testbench in assembler for testing all Op Codes
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Including Klaus Dormann's "65c02_*_test" suite
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| 18 |
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- (DONE) Because of translation errors the Verilog sources are no longer
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| 19 |
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available
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| 20 |
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- (DONE) Create "golden" simulation files for Modelsim/QuestaSim
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| 21 |
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- (75%) Finish working for Specification of cpu65C02_tc
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| 22 |
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- (85%) Finish working for Specification of cpu65C02_tc
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| 23 |
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| 24 |
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| 25 |
12 |
fpga_is_fu |
(February 25th 2009)
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| 26 |
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- (DONE) CORRECTED "RTI" (wrong: use of stack pointer)
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| 27 |
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- (DONE) CORRECTED "RMBx" & "SMBx" (wrong: bit translation)
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| 28 |
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- (DONE) RENAME all states of "FSM Execution Unit" for better reading
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| 29 |
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- (85%) Finish working for Specification of cpu65C02_tc
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| 30 |
18 |
fpga_is_fu |
- (DONE) CORRECT timing for addressing mode "ABS,X" for "INC" (wrong: 6 cycles
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| 31 |
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instead of 7)
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| 32 |
12 |
fpga_is_fu |
- (DONE) OPTIMIZE end states of "STA" (s197,s207,s200,s213)
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| 33 |
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| 34 |
7 |
fpga_is_fu |
(January, 4th 2009)
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| 35 |
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- (DONE) Remove unused nets, register and modules
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| 36 |
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- (DONE) Update the HDL Designer files for better viewing and
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| 37 |
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understanding
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| 38 |
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| 39 |
2 |
fpga_is_fu |
(August, 5th 2008)
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| 40 |
4 |
fpga_is_fu |
- (DONE) Rename all port names (_i, _o, _o_i)
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| 41 |
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- (DONE) Test and verify all Op Codes
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| 42 |
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- (DONE) Optimize core for speed
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| 43 |
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- (DONE) Implement same improvements like cpu6502_tc (graphical design, source
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| 44 |
2 |
fpga_is_fu |
utilisation...)
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| 45 |
4 |
fpga_is_fu |
- (75%) Finish working for Specification of cpu65C02_tc
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| 46 |
7 |
fpga_is_fu |
- (WORKING) Create high level testbench in assembler and hardware for
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| 47 |
2 |
fpga_is_fu |
testing all Op Codes (include accurate cycle timing)
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| 48 |
7 |
fpga_is_fu |
- (WORKING) Create simulation files for Modelsim
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| 49 |
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- (WORKING) Create a simple .wlf file to demonstrate the cpu65C02_tc
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| 50 |
2 |
fpga_is_fu |
- Update the HDL Designer files for better viewing and understanding
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