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[/] [cpu65c02_true_cycle/] [trunk/] [released/] [rtl/] [v1_53/] [vhdl/] [r65c02_tc.vhd] - Blame information for rev 24

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1 24 fpga_is_fu
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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entity r65c02_tc is
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   port(
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      clk_clk_i   : in     std_logic;
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      d_i         : in     std_logic_vector (7 downto 0);
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      irq_n_i     : in     std_logic;
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      nmi_n_i     : in     std_logic;
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      rdy_i       : in     std_logic;
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      rst_rst_n_i : in     std_logic;
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      so_n_i      : in     std_logic;
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      a_o         : out    std_logic_vector (15 downto 0);
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      d_o         : out    std_logic_vector (7 downto 0);
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      rd_o        : out    std_logic;
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      sync_o      : out    std_logic;
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      wr_n_o      : out    std_logic;
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      wr_o        : out    std_logic
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   );
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-- Declarations
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end r65c02_tc ;
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-- (C) 2008 - 2021 Jens Gutschmidt
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-- (email: opencores@vivare-services.com)
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-- 
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-- Versions:
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-- Revision 1.53  2021/01/08 22:20:00  jens
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-- - Bug Fix rdy_i='0' causes hang after res_res_n_i='0' -> '1'
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--   at state RES1/s545 and malfunction of:
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--   STA  ABS,Y state s208 -> no write of data
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--   STA  (IND,X) state s209 -> no write of data
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-- Revision 1.52  2018/09/10 12:14:00  jens
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-- - RESET generates SYNC now, 1 dead cycle delayed
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-- Revision 1.52  RC 2018/09/09 03:00:00  jens
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-- - ADC / SBC flags and A like R65C02 now
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-- Revision 1.52  BETA 2018/09/05 19:35:00  jens
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-- - BBRx/BBSx internal cycles like real 65C02 now
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-- - Bug Fix ADC and SBC in decimal mode (all op codes -
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--   1 cycle is missing
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-- - Bug Fix ADC and SBC in decimal mode (all op codes -
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--   "Overflow" flag was computed wrong)
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-- Revision 1.52  BETA 2018/09/02 18:49:00  jens
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-- - Interrupt NMI and IRQ processing via FETCH stage now
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-- Revision 1.52  BETA 2018/08/30 15:39:00  jens
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-- - Interrupt priority order is now: BRQ - NMI - IRQ
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-- - Performance improvements on-going (Mealy -> Moore)
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-- Revision 1.52  BETA 2018/08/23 20:27:00  jens
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-- - Bug Fixes All Branch Instructions 
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--   (BCC, BCS, BEQ, BNE, BPL, BMI, BVC, BVS, BRA)
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--   3 cycles now if branch forward occur and the branch
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--   instruction lies on a xxFEh location.
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--   (BBR, BBS) 6 cycles now if branch forward occur and the
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--   branch instruction lies on a xxFDh location.
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-- - Bug Fix Hardware Interrupts NMI & IRQ - 7 cycles & "SYNC" now
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-- - Bug Fix Now all cycles are delayable (WR and internal)
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-- 
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-- Revision 1.51  RC 2014/04/19 14:44:00  jens
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-- (never submitted to opencores)
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-- - Bug Fix JMP ABS - produced a 6502 like JMP (IND) PCH.
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--   When the ABS address data bytes cross the page
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--   boundary (e.g. $02FE JMP hhll reads hh from
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--   $02FF and ll from $0200, instead $02FF and $0300) 
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-- 
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-- Revision 1.5  RC 2013/08/01 11:00:00  jens
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-- - Change Block name to lower case
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-- - Bug Fix CMP (IND) - wrongly decoded as function AND
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-- - Bug Fix BRK should clear decimal flag in P Reg
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-- - Bug Fix JMP (ABS,X) - Low Address outputted twice - no
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--   High Address
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-- - Bug Fix Unknown Ops - Used always 1b2c NOP ($EA) -
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--   new NOPs created
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-- - Bug Fix DECIMAL ADC and SBC (all op codes - "C" flag
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--   was computed wrong)
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-- - Bug Fix INC/DEC ABS,X - N/Z flag wrongly computed
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-- - Bug Fix RTI - should increment stack pointer
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-- - Bug Fix "E" & "B" flags (Bits 5 & 4) - should be always "1"
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--   in P Reg. Change "RES", "RTI", "IRQ" & "NMI" substates.
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-- - Bug Fix ADC and SBC (all sub codes - "Overflow" flag was computed wrong)
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-- - Bug Fix RMB, SMB Bug - Bit position decoded wrong
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-- 
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-- Revision 1.4  2013/07/21 11:11:00  jens
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-- - Changing the title block and internal revision history
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-- - Bug Fix STA [(IND)] op$92 ($92 was missed in the con-
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--   nection list at state FETCH)
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-- 
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-- Revision 1.3  2009/01/04 10:20:50  eda
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-- Changes for cosmetic issues only
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-- 
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-- Revision 1.2  2009/01/04 09:23:12  eda
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-- - Delete unused nets and blocks (same as R6502_TC)
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-- - Rename blocks
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-- - Re-arrage FSM symbols in block FSM_Execution_Unit
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-- 
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-- Revision 1.1  2009/01/03 16:36:48  eda
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-- -- no description --
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--  
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-- 
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--
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-- r65c02_tc.r65c02_tc.struct
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--
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-- Date:    09.01.2021
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-- Time:    02:11:37
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-- By:        VIVARE GmbH, Switzerland
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--
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-- COPYRIGHT (C) 2008 - 2021 by Jens Gutschmidt
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-- 
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
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-- 
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.
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-- 
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-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.
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-- 
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-- 
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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library r65c02_tc;
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architecture struct of r65c02_tc is
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   -- Architecture declarations
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   -- Internal signal declarations
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   -- Component Declarations
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   component core
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   port (
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      clk_clk_i   : in     std_logic ;
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      d_i         : in     std_logic_vector (7 downto 0);
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      irq_n_i     : in     std_logic ;
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      nmi_n_i     : in     std_logic ;
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      rdy_i       : in     std_logic ;
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      rst_rst_n_i : in     std_logic ;
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      so_n_i      : in     std_logic ;
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      a_o         : out    std_logic_vector (15 downto 0);
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      d_o         : out    std_logic_vector (7 downto 0);
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      rd_o        : out    std_logic ;
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      sync_o      : out    std_logic ;
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      wr_n_o      : out    std_logic ;
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      wr_o        : out    std_logic
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   );
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   end component;
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   -- Optional embedded configurations
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   -- pragma synthesis_off
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   for all : core use entity r65c02_tc.core;
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   -- pragma synthesis_on
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begin
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   -- Instance port mappings.
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   U_0 : core
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      port map (
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         clk_clk_i   => clk_clk_i,
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         d_i         => d_i,
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         irq_n_i     => irq_n_i,
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         nmi_n_i     => nmi_n_i,
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         rdy_i       => rdy_i,
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         rst_rst_n_i => rst_rst_n_i,
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         so_n_i      => so_n_i,
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         a_o         => a_o,
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         d_o         => d_o,
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         rd_o        => rd_o,
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         sync_o      => sync_o,
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         wr_n_o      => wr_n_o,
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         wr_o        => wr_o
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      );
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end struct;

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