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[/] [cpu65c02_true_cycle/] [trunk/] [released/] [rtl/] [v1_53/] [vhdl/] [reg_pc.vhd] - Blame information for rev 24

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1 24 fpga_is_fu
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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entity reg_pc is
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   port(
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      adr_i        : in     std_logic_vector (15 downto 0);
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      clk_clk_i    : in     std_logic;
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      ld_i         : in     std_logic_vector (1 downto 0);
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      ld_pc_i      : in     std_logic;
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      offset_i     : in     std_logic_vector (15 downto 0);
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      rst_rst_n_i  : in     std_logic;
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      sel_pc_in_i  : in     std_logic;
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      sel_pc_val_i : in     std_logic_vector (1 downto 0);
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      adr_nxt_pc_o : out    std_logic_vector (15 downto 0);
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      adr_pc_o     : out    std_logic_vector (15 downto 0)
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   );
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-- Declarations
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end reg_pc ;
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-- (C) 2008 - 2021 Jens Gutschmidt
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-- (email: opencores@vivare-services.com)
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-- 
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-- Versions:
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-- Revision 1.7  2013/07/21 11:11:00  jens
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-- - Changing the title block and internal revision history
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-- 
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-- Revision 1.6  2009/01/04 10:20:47  eda
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-- Changes for cosmetic issues only
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-- 
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-- Revision 1.5  2009/01/04 09:23:10  eda
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-- - Delete unused nets and blocks (same as R6502_TC)
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-- - Rename blocks
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-- 
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-- Revision 1.4  2009/01/03 16:53:02  eda
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-- - Unused nets and blocks deleted
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-- - Renamed blocks
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-- 
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-- Revision 1.3  2009/01/03 16:42:02  eda
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-- - Unused nets and blocks deleted
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-- - Renamed blocks
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-- 
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-- Revision 1.2  2008/12/31 19:31:24  eda
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-- Production Release
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--  
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-- 
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--
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-- r65c02_tc.reg_pc.struct
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--
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-- Date:    09.01.2021
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-- Time:    16:56:45
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-- By:        VIVARE GmbH, Switzerland
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--
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-- COPYRIGHT (C) 2008 - 2021 by Jens Gutschmidt
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-- 
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-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
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-- 
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-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for more details.
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-- 
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-- You should have received a copy of the GNU General Public License along with this program.  If not, see <http://www.gnu.org/licenses/>.
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-- 
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-- 
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.std_logic_arith.all;
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architecture struct of reg_pc is
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   -- Architecture declarations
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   -- Internal signal declarations
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   signal adr_pc_high_o_i : std_logic_vector(7 downto 0);
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   signal adr_pc_low_o_i  : std_logic_vector(7 downto 0);
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   signal adr_pc_o_i      : std_logic_vector(15 downto 0);
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   signal ci_o_i          : std_logic;
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   signal cout_pc_o_i     : std_logic;
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   signal load3_o_i       : std_logic;
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   signal load_o_i        : std_logic;
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   signal offset_high_o_i : std_logic_vector(7 downto 0);
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   signal offset_low_o_i  : std_logic_vector(7 downto 0);
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   signal val_o_i         : std_logic_vector(7 downto 0);
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   signal val_one         : std_logic_vector(7 downto 0);
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   signal val_zero        : std_logic_vector(7 downto 0);
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   -- Implicit buffer signal declarations
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   signal adr_nxt_pc_o_internal : std_logic_vector (15 downto 0);
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   signal adr_pc_o_internal     : std_logic_vector (15 downto 0);
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91
 
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   -- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff'
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   signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
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   -- ModuleWare signal declarations(v1.12) for instance 'U_4' of 'adff'
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   signal mw_U_4reg_cval : std_logic_vector(15 downto 8);
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98
   -- ModuleWare signal declarations(v1.12) for instance 'U_3' of 'split'
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   signal mw_U_3temp_din : std_logic_vector(15 downto 0);
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101
   -- ModuleWare signal declarations(v1.12) for instance 'U_5' of 'split'
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   signal mw_U_5temp_din : std_logic_vector(15 downto 0);
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104
 
105
begin
106
 
107
   -- ModuleWare code(v1.12) for instance 'U_2' of 'add'
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   u_2combo_proc: process (adr_pc_low_o_i, val_o_i)
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   variable temp_din0 : std_logic_vector(8 downto 0);
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   variable temp_din1 : std_logic_vector(8 downto 0);
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   variable temp_sum : unsigned(8 downto 0);
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   variable temp_carry : std_logic;
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   begin
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      temp_din0 := '0' & adr_pc_low_o_i;
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      temp_din1 := '0' & val_o_i;
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      temp_carry := '0';
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      temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
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      adr_nxt_pc_o_internal(7 DOWNTO 0) <= conv_std_logic_vector(temp_sum(7 downto 0),8);
119
      cout_pc_o_i <= temp_sum(8) ;
120
   end process u_2combo_proc;
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   -- ModuleWare code(v1.12) for instance 'U_11' of 'add'
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   u_11combo_proc: process (adr_pc_high_o_i, offset_high_o_i, ci_o_i)
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   variable temp_din0 : std_logic_vector(8 downto 0);
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   variable temp_din1 : std_logic_vector(8 downto 0);
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   variable temp_sum : unsigned(8 downto 0);
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   variable temp_carry : std_logic;
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   begin
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      temp_din0 := '0' & adr_pc_high_o_i;
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      temp_din1 := '0' & offset_high_o_i;
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      temp_carry := ci_o_i;
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      temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
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      adr_nxt_pc_o_internal(15 DOWNTO 8) <= conv_std_logic_vector(temp_sum(7 downto 0),8);
134
   end process u_11combo_proc;
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   -- ModuleWare code(v1.12) for instance 'U_0' of 'adff'
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   adr_pc_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
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   u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
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   begin
140
      if (rst_rst_n_i = '0') then
141
         mw_U_0reg_cval <= "00000000";
142
      elsif (clk_clk_i'event and clk_clk_i='1') then
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         if (load_o_i = '1') then
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            mw_U_0reg_cval <= adr_nxt_pc_o_internal(7 DOWNTO 0);
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         end if;
146
      end if;
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   end process u_0seq_proc;
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   -- ModuleWare code(v1.12) for instance 'U_4' of 'adff'
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   adr_pc_o_internal(15 DOWNTO 8) <= mw_U_4reg_cval;
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   u_4seq_proc: process (clk_clk_i, rst_rst_n_i)
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   begin
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      if (rst_rst_n_i = '0') then
154
         mw_U_4reg_cval <= "00000000";
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      elsif (clk_clk_i'event and clk_clk_i='1') then
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         if (load3_o_i = '1') then
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            mw_U_4reg_cval <= adr_nxt_pc_o_internal(15 DOWNTO 8);
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         end if;
159
      end if;
160
   end process u_4seq_proc;
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   -- ModuleWare code(v1.12) for instance 'U_6' of 'and'
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   load_o_i <= ld_pc_i and ld_i(0);
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   -- ModuleWare code(v1.12) for instance 'U_7' of 'and'
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   load3_o_i <= ld_pc_i and ld_i(1);
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168
   -- ModuleWare code(v1.12) for instance 'U_10' of 'and'
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   ci_o_i <= cout_pc_o_i and ld_pc_i;
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   -- ModuleWare code(v1.12) for instance 'U_1' of 'constval'
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   val_zero <= "00000000";
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   -- ModuleWare code(v1.12) for instance 'U_9' of 'constval'
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   val_one <= "00000001";
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   -- ModuleWare code(v1.12) for instance 'U_8' of 'mux'
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   u_8combo_proc: process(adr_pc_o_internal, adr_i, sel_pc_in_i)
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   begin
180
      case sel_pc_in_i is
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      when '0' => adr_pc_o_i <= adr_pc_o_internal;
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      when '1' => adr_pc_o_i <= adr_i;
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      when others => adr_pc_o_i <= (others => 'X');
184
      end case;
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   end process u_8combo_proc;
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   -- ModuleWare code(v1.12) for instance 'U_13' of 'mux'
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   u_13combo_proc: process(val_one, val_zero, offset_low_o_i,
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                           sel_pc_val_i)
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   begin
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      case sel_pc_val_i is
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      when "00" => val_o_i <= val_one;
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      when "01" => val_o_i <= val_zero;
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      when "10" => val_o_i <= offset_low_o_i;
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      when "11" => val_o_i <= val_zero;
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      when others => val_o_i <= (others => 'X');
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      end case;
198
   end process u_13combo_proc;
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200
   -- ModuleWare code(v1.12) for instance 'U_3' of 'split'
201
   mw_U_3temp_din <= adr_pc_o_i;
202
   u_3combo_proc: process (mw_U_3temp_din)
203
   variable temp_din: std_logic_vector(15 downto 0);
204
   begin
205
      temp_din := mw_U_3temp_din(15 downto 0);
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      adr_pc_low_o_i <= temp_din(7 downto 0);
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      adr_pc_high_o_i <= temp_din(15 downto 8);
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   end process u_3combo_proc;
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   -- ModuleWare code(v1.12) for instance 'U_5' of 'split'
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   mw_U_5temp_din <= offset_i;
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   u_5combo_proc: process (mw_U_5temp_din)
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   variable temp_din: std_logic_vector(15 downto 0);
214
   begin
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      temp_din := mw_U_5temp_din(15 downto 0);
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      offset_low_o_i <= temp_din(7 downto 0);
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      offset_high_o_i <= temp_din(15 downto 8);
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   end process u_5combo_proc;
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   -- Instance port mappings.
221
 
222
   -- Implicit buffered output assignments
223
   adr_nxt_pc_o <= adr_nxt_pc_o_internal;
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   adr_pc_o     <= adr_pc_o_internal;
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end struct;

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