URL https://opencores.org/ocsvn/cpu8080/cpu8080/trunk

Subversion Repositories cpu8080

[/] [cpu8080/] [branches/] [samiam95124/] [project/] [cpu8080_tbw.tbw] - Blame information for rev 18

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version 3
C:/Xilinx/ISEexamples/cpu8080/testbench.v
testbench
VERILOG
VERILOG
cpu8080_tbw.xwv
Clocked
-
-
100000000000
ns
GSR:true
PRLD:false
100000000
CLOCK_LIST_BEGIN
clock
20000000
20000000
10000000
10000000
100000000
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
addr
clock
b
clock
data
clock
g
clock
hsync_n
clock
inta
clock
intr
clock
ps2_clk
clock
ps2_data
clock
r
clock
readio
clock
readmem
clock
reset
clock
reset_n
clock
vsync_n
clock
waitr
clock
writeio
clock
writemem
clock
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
addr_DIFF
b_DIFF
g_DIFF
hsync_n_DIFF
inta_DIFF
intr_DIFF
r_DIFF
readio_DIFF
readmem_DIFF
vsync_n_DIFF
writeio_DIFF
writemem_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clock
reset_n
waitr
inta
intr
readio
readmem
writeio
writemem
addr
data
b
g
r
hsync_n
vsync_n
ps2_clk
ps2_data
SIGNAL_ORDER_END
-X-X-X-
 

Line No.	Rev	Author	Line
1	11	samiam9512	`version 3`
2			`C:/Xilinx/ISEexamples/cpu8080/testbench.v`
3			`testbench`
4			`VERILOG`
5			`VERILOG`
6			`cpu8080_tbw.xwv`
7			`Clocked`
8			`-`
9			`-`
10			`100000000000`
11			`ns`
12			`GSR:true`
13			`PRLD:false`
14			`100000000`
15			`CLOCK_LIST_BEGIN`
16			`clock`
17			`20000000`
18			`20000000`
19			`10000000`
20			`10000000`
21			`100000000`
22			`RISING`
23			`CLOCK_LIST_END`
24			`SIGNAL_LIST_BEGIN`
25			`addr`
26			`clock`
27			`b`
28			`clock`
29			`data`
30			`clock`
31			`g`
32			`clock`
33			`hsync_n`
34			`clock`
35			`inta`
36			`clock`
37			`intr`
38			`clock`
39	18	samiam9512	`ps2_clk`
40			`clock`
41			`ps2_data`
42			`clock`
43	11	samiam9512	`r`
44			`clock`
45			`readio`
46			`clock`
47			`readmem`
48			`clock`
49			`reset`
50			`clock`
51			`reset_n`
52			`clock`
53			`vsync_n`
54			`clock`
55			`waitr`
56			`clock`
57			`writeio`
58			`clock`
59			`writemem`
60			`clock`
61			`SIGNAL_LIST_END`
62			`SIGNALS_NOT_ON_DISPLAY`
63			`addr_DIFF`
64			`b_DIFF`
65			`g_DIFF`
66			`hsync_n_DIFF`
67			`inta_DIFF`
68			`intr_DIFF`
69			`r_DIFF`
70			`readio_DIFF`
71			`readmem_DIFF`
72			`vsync_n_DIFF`
73			`writeio_DIFF`
74			`writemem_DIFF`
75			`SIGNALS_NOT_ON_DISPLAY_END`
76			`MARKER_LIST_BEGIN`
77			`MARKER_LIST_END`
78			`MEASURE_LIST_BEGIN`
79			`MEASURE_LIST_END`
80			`SIGNAL_ORDER_BEGIN`
81			`clock`
82			`reset_n`
83			`waitr`
84			`inta`
85			`intr`
86			`readio`
87			`readmem`
88			`writeio`
89			`writemem`
90			`addr`
91	18	samiam9512	`data`
92	11	samiam9512	`b`
93			`g`
94			`r`
95	18	samiam9512	`hsync_n`
96			`vsync_n`
97			`ps2_clk`
98			`ps2_data`
99	11	samiam9512	`SIGNAL_ORDER_END`
100			`-X-X-X-`
101

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Subversion Repositories cpu8080

[/] [cpu8080/] [branches/] [samiam95124/] [project/] [cpu8080_tbw.tbw] - Blame information for rev 18