Subversion Repositories cpu8080

Release 8.2.02i par I.33

Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

SCOTT-H-PC::  Thu Nov 16 20:11:54 2006

par -w -intstyle ise -ol std -t 1 testbench_map.ncd testbench.ncd testbench.pcf

Constraints file: testbench.pcf.

Loading device for application Rf_Device from file '3s1000.nph' in environment C:\Xilinx.

   "testbench" is an NCD, version 3.1, device xc3s1000, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)

Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par

   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all

   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For

   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a

   balance between the fastest runtime and best performance, set the effort level to "med".

Device speed data version:  "PRODUCTION 1.39 2006-07-07".

Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%

   Number of External IOBs            54 out of 173    31%

      Number of LOCed IOBs            46 out of 54     85%

   Number of MULT18X18s                2 out of 24      8%

   Number of RAMB16s                   4 out of 24     16%

   Number of Slices                 3445 out of 7680   44%

      Number of SLICEMs              958 out of 3840   24%

Overall effort level (-ol):   Standard

Placer effort level (-pl):    High

Placer cost table entry (-t): 1

Router effort level (-rl):    Standard

Starting Placer

Phase 1.1

Phase 1.1 (Checksum:99838d) REAL time: 8 secs

Phase 2.7

WARNING:Place:837 - Partially locked IO Bus is found.

    Following components of the bus are not locked:

         Comp: addr<15>

WARNING:Place:837 - Partially locked IO Bus is found.

    Following components of the bus are not locked:

         Comp: diag<6>

         Comp: diag<5>

         Comp: diag<4>

         Comp: diag<3>

         Comp: diag<2>

         Comp: diag<1>

         Comp: diag<0>

INFO:Place:834 - Only a subset of IOs are locked. Out of 54 IOs, 46 are locked and 8 are not locked. If you would like

   to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 2 (or more).

Phase 2.7 (Checksum:1312cfe) REAL time: 8 secs

Phase 3.31

Phase 3.31 (Checksum:1c9c37d) REAL time: 8 secs

Phase 4.2

.....

...................

Phase 4.2 (Checksum:98bdc7) REAL time: 16 secs

Phase 5.3

Phase 5.3 (Checksum:2faf07b) REAL time: 17 secs

Phase 6.5

Phase 6.5 (Checksum:39386fa) REAL time: 17 secs

Phase 7.8

......................................................................................................................................................................................

.........

.......................................................................................................................................................

..........

............

.......................

Phase 7.8 (Checksum:124efe7) REAL time: 1 mins 42 secs

Phase 8.5

Phase 8.5 (Checksum:4c4b3f8) REAL time: 1 mins 42 secs

Phase 9.18

Phase 9.18 (Checksum:55d4a77) REAL time: 2 mins 44 secs

Phase 10.5

Phase 10.5 (Checksum:5f5e0f6) REAL time: 2 mins 44 secs

Writing design to file testbench.ncd

Total REAL time to Placer completion: 2 mins 48 secs

Total CPU time to Placer completion: 2 mins 42 secs

Starting Router

Phase 1: 27650 unrouted;       REAL time: 2 mins 49 secs

Phase 2: 26038 unrouted;       REAL time: 2 mins 57 secs

Phase 3: 8278 unrouted;       REAL time: 3 mins 4 secs

Phase 4: 8278 unrouted; (42106)      REAL time: 3 mins 4 secs

Phase 5: 8305 unrouted; (0)      REAL time: 3 mins 7 secs

Phase 6: 0 unrouted; (8000)      REAL time: 3 mins 44 secs

Phase 7: 0 unrouted; (8000)      REAL time: 3 mins 47 secs

Phase 8: 0 unrouted; (5730)      REAL time: 4 mins

Phase 9: 0 unrouted; (5730)      REAL time: 4 mins 9 secs

WARNING:Route:447 - CLK Net:reset_n_BUFGP may have excessive skew because

   462 NON-CLK pins failed to route using a CLK template.

Total REAL time to Router completion: 4 mins 9 secs

Total CPU time to Router completion: 3 mins 57 secs

Partition Implementation Status

-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************

Generating Clock Report

**************************

+---------------------+--------------+------+------+------------+-------------+

|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|

+---------------------+--------------+------+------+------------+-------------+

|         clock_BUFGP |      BUFGMUX3| No   | 1382 |  0.433     |  1.139      |

+---------------------+--------------+------+------+------------+-------------+

|       reset_n_BUFGP |      BUFGMUX5| No   |  478 |  0.155     |  1.085      |

+---------------------+--------------+------+------+------------+-------------+

|select1/selectc/_and |              |      |      |            |             |

|                0000 |         Local|      |    7 |  0.156     |  3.257      |

+---------------------+--------------+------+------+------------+-------------+

|select1/selecta/_and |              |      |      |            |             |

|                0000 |         Local|      |    7 |  0.085     |  2.938      |

+---------------------+--------------+------+------+------------+-------------+

|select1/selectd/_and |              |      |      |            |             |

|                0000 |         Local|      |    7 |  0.131     |  2.884      |

+---------------------+--------------+------+------+------------+-------------+

|select1/selectb/_and |              |      |      |            |             |

|                0000 |         Local|      |    7 |  0.079     |  2.261      |

+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing

only delays for the net. Note this is different from Clock Skew which

is reported in TRCE timing report. Clock Skew is the difference between

the minimum and maximum path delays which includes logic delays.

   The Delay Summary Report

The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        2.351

   The MAXIMUM PIN DELAY IS:                               9.448

   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   8.536

   Listing Pin Delays by value: (nsec)

    d < 2.00   < d < 4.00  < d < 6.00  < d < 8.00  < d < 10.00  d >= 10.00

   ---------   ---------   ---------   ---------   ---------   ---------

       14494        8705        3462        1202          93           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.

   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------

  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of

                                            |            |            | Levels | Slack      |errors

------------------------------------------------------------------------------------------------------

  Autotimespec constraint for clock net clo | N/A        | 20.711ns   | 4      | N/A        | N/A

  ck_BUFGP                                  |            |            |        |            |

------------------------------------------------------------------------------------------------------

All constraints were met.

INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the

   constraint does not cover any paths or that it has no requested value.

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 4 mins 20 secs

Total CPU time to PAR completion: 4 mins 2 secs

Peak Memory Usage:  283 MB

Placement: Completed - No errors found.

Routing: Completed - No errors found.

Number of error messages: 0

Number of warning messages: 3

Number of info messages: 2

Writing design to file testbench.ncd

PAR done!