URL https://opencores.org/ocsvn/cpu8080/cpu8080/trunk

Subversion Repositories cpu8080

[/] [cpu8080/] [tags/] [initial/] [project/] [cpu_tbw.tbw] - Blame information for rev 4

Go to most recent revision | Details | Compare with Previous | View Log


version 3
C:/Xilinx/ISEexamples/cpu8080/testbench.v
testbench
VERILOG
VERILOG
cpu_tbw.xwv
Clocked
-
-
10000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clock
100000000
100000000
15000000
15000000
 
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
addr
clock
data
clock
inta
clock
intr
clock
junk
clock
readio
clock
readmem
clock
reset
clock
waitr
clock
writeio
clock
writemem
clock
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
addr_DIFF
inta_DIFF
readio_DIFF
readmem_DIFF
writeio_DIFF
writemem_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clock
intr
reset
waitr
inta
readio
readmem
writeio
writemem
addr
data
SIGNAL_ORDER_END
-X-X-X-
 

Line No.	Rev	Author	Line
1	2	samiam9512	`version 3`
2			`C:/Xilinx/ISEexamples/cpu8080/testbench.v`
3			`testbench`
4			`VERILOG`
5			`VERILOG`
6			`cpu_tbw.xwv`
7			`Clocked`
8			`-`
9			`-`
10			`10000000000`
11			`ns`
12			`GSR:false`
13			`PRLD:false`
14			`100000000`
15			`CLOCK_LIST_BEGIN`
16			`clock`
17			`100000000`
18			`100000000`
19			`15000000`
20			`15000000`
21
22			`RISING`
23			`CLOCK_LIST_END`
24			`SIGNAL_LIST_BEGIN`
25			`addr`
26			`clock`
27			`data`
28			`clock`
29			`inta`
30			`clock`
31			`intr`
32			`clock`
33			`junk`
34			`clock`
35			`readio`
36			`clock`
37			`readmem`
38			`clock`
39			`reset`
40			`clock`
41			`waitr`
42			`clock`
43			`writeio`
44			`clock`
45			`writemem`
46			`clock`
47			`SIGNAL_LIST_END`
48			`SIGNALS_NOT_ON_DISPLAY`
49			`addr_DIFF`
50			`inta_DIFF`
51			`readio_DIFF`
52			`readmem_DIFF`
53			`writeio_DIFF`
54			`writemem_DIFF`
55			`SIGNALS_NOT_ON_DISPLAY_END`
56			`MARKER_LIST_BEGIN`
57			`MARKER_LIST_END`
58			`MEASURE_LIST_BEGIN`
59			`MEASURE_LIST_END`
60			`SIGNAL_ORDER_BEGIN`
61			`clock`
62			`intr`
63			`reset`
64			`waitr`
65			`inta`
66			`readio`
67			`readmem`
68			`writeio`
69			`writemem`
70			`addr`
71			`data`
72			`SIGNAL_ORDER_END`
73			`-X-X-X-`
74

Browse

Tools

Subversion Repositories cpu8080

[/] [cpu8080/] [tags/] [initial/] [project/] [cpu_tbw.tbw] - Blame information for rev 4