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[/] [cpu8080/] [trunk/] [project/] [_xmsgs/] [bitgen.xmsgs] - Blame information for rev 33

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Line No. Rev Author Line
1 11 samiam9512
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8 20 samiam9512
Gated clock. Clock net select1/selectc/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
9 11 samiam9512
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Gated clock. Clock net select1/selecta/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
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14 20 samiam9512
Gated clock. Clock net select1/selectd/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
15 11 samiam9512
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17 20 samiam9512
Gated clock. Clock net select1/selectb/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
18 11 samiam9512
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20 20 samiam9512
Dangling pin <DOA5> on block:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB16A>.
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Dangling pin <DOA6> on block:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB16A>.
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Dangling pin <DOA7> on block:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB16A>.
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29 11 samiam9512

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