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Logical network adm3a/display/inst_Mram_mem960/SPO has no load.

 
The above warning message base_net_load_rule is repeated 839 more times for the following (max. 5 shown):
adm3a/display/inst_Mram_mem1100/SPO,
adm3a/display/inst_Mram_mem2100/SPO,
adm3a/display/inst_Mram_mem3100/SPO,
adm3a/display/inst_Mram_mem4100/SPO,
adm3a/display/inst_Mram_mem5100/SPO
To see the details of these warning messages, please use the -detail switch.

 
No environment variables are currently set.

 
The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
BUFGP symbol "clock_BUFGP" (output signal=clock_BUFGP),
BUFGP symbol "reset_n_BUFGP" (output signal=reset_n_BUFGP)

 
All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.

 
Clock buffer is designated to drive clock loads. BUFGMUX symbol "physical_group_reset_n_BUFGP/reset_n_BUFGP/BUFG" (output signal=reset_n_BUFGP) has a mix of clock and non-clock loads. Some of the non-clock loads are (maximum of 5 listed):
Pin CLR of cpu/readmem
Pin CLR of cpu/inta
Pin CE of cpu/addr_0
Pin CE of cpu/addr_1
Pin CE of cpu/addr_2

 
Gated clock. Clock net select1/selectc/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.

 
Gated clock. Clock net select1/selecta/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.

 
Gated clock. Clock net select1/selectd/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.

 
Gated clock. Clock net select1/selectb/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.

 
Dangling pin <DOA5> on block:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB16A>.

 
Dangling pin <DOA6> on block:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB16A>.

 
Dangling pin <DOA7> on block:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB16A>.

 


Line No.	Rev	Author	Line
1	11	samiam9512
2
7
8			`Logical network adm3a/display/inst_Mram_mem960/SPO has no load.`
9
10
11			`The above warning message base_net_load_rule is repeated 839 more times for the following (max. 5 shown):`
12			`adm3a/display/inst_Mram_mem1100/SPO,`
13			`adm3a/display/inst_Mram_mem2100/SPO,`
14			`adm3a/display/inst_Mram_mem3100/SPO,`
15			`adm3a/display/inst_Mram_mem4100/SPO,`
16			`adm3a/display/inst_Mram_mem5100/SPO`
17			`To see the details of these warning messages, please use the -detail switch.`
18
19
20			`No environment variables are currently set.`
21
22
23			`The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:`
24	18	samiam9512	`BUFGP symbol "clock_BUFGP" (output signal=clock_BUFGP),`
25	11	samiam9512	`BUFGP symbol "reset_n_BUFGP" (output signal=reset_n_BUFGP)`
26
27
28			`All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.`
29
30
31			`Clock buffer is designated to drive clock loads. BUFGMUX symbol "physical_group_reset_n_BUFGP/reset_n_BUFGP/BUFG" (output signal=reset_n_BUFGP) has a mix of clock and non-clock loads. Some of the non-clock loads are (maximum of 5 listed):`
32	18	samiam9512	`Pin CLR of cpu/readmem`
33			`Pin CLR of cpu/inta`
34	11	samiam9512	`Pin CE of cpu/addr_0`
35			`Pin CE of cpu/addr_1`
36			`Pin CE of cpu/addr_2`
37
38
39	20	samiam9512	`Gated clock. Clock net select1/selectc/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.`
40	11	samiam9512
41
42	18	samiam9512	`Gated clock. Clock net select1/selecta/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.`
43
44
45	20	samiam9512	`Gated clock. Clock net select1/selectd/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.`
46	11	samiam9512
47
48	20	samiam9512	`Gated clock. Clock net select1/selectb/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.`
49	18	samiam9512
50
51	20	samiam9512	`Dangling pin <DOA5> on block:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB16A>.`
52
53
54			`Dangling pin <DOA6> on block:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB16A>.`
55
56
57			`Dangling pin <DOA7> on block:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB16A>.`
58
59
60	11	samiam9512

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[/] [cpu8080/] [trunk/] [project/] [_xmsgs/] [map.xmsgs] - Blame information for rev 24