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samiam9512 |
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| 7 |
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Logical network adm3a/display/inst_Mram_mem960/SPO has no load.
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| 11 |
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The above warning message base_net_load_rule is repeated 839 more times for the following (max. 5 shown):
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adm3a/display/inst_Mram_mem1100/SPO,
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adm3a/display/inst_Mram_mem2100/SPO,
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adm3a/display/inst_Mram_mem3100/SPO,
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adm3a/display/inst_Mram_mem4100/SPO,
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adm3a/display/inst_Mram_mem5100/SPO
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To see the details of these warning messages, please use the -detail switch.
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No environment variables are currently set.
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The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
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| 24 |
18 |
samiam9512 |
BUFGP symbol "clock_BUFGP" (output signal=clock_BUFGP),
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| 25 |
11 |
samiam9512 |
BUFGP symbol "reset_n_BUFGP" (output signal=reset_n_BUFGP)
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| 27 |
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| 28 |
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All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs in the schematic.
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| 31 |
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Clock buffer is designated to drive clock loads. BUFGMUX symbol "physical_group_reset_n_BUFGP/reset_n_BUFGP/BUFG" (output signal=reset_n_BUFGP) has a mix of clock and non-clock loads. Some of the non-clock loads are (maximum of 5 listed):
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| 32 |
18 |
samiam9512 |
Pin CLR of cpu/readmem
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| 33 |
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Pin CLR of cpu/inta
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| 34 |
11 |
samiam9512 |
Pin CE of cpu/addr_0
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Pin CE of cpu/addr_1
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Pin CE of cpu/addr_2
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| 38 |
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| 39 |
28 |
samiam9512 |
The function generator adm3a/display/chradr<5>35 failed to merge with F5 multiplexer adm3a/display/chradr<6>_f5_3. There is a conflict for the FXMUX. The design will exhibit suboptimal timing.
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The function generator cpu/_mux0003_SW1 failed to merge with F5 multiplexer cpu/_mux0007. There is a conflict for the FXMUX. The design will exhibit suboptimal timing.
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| 44 |
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| 45 |
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The function generator cpu/_mux0003_SW1 failed to merge with F5 multiplexer cpu/_mux00031_f5. There is a conflict for the FXMUX. The design will exhibit suboptimal timing.
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| 47 |
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| 48 |
20 |
samiam9512 |
Gated clock. Clock net select1/selectc/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
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| 49 |
11 |
samiam9512 |
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| 50 |
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| 51 |
18 |
samiam9512 |
Gated clock. Clock net select1/selecta/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
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| 53 |
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| 54 |
20 |
samiam9512 |
Gated clock. Clock net select1/selectd/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
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| 55 |
11 |
samiam9512 |
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| 56 |
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| 57 |
20 |
samiam9512 |
Gated clock. Clock net select1/selectb/_and0000 is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.
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| 58 |
18 |
samiam9512 |
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| 59 |
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| 60 |
20 |
samiam9512 |
Dangling pin <DOA5> on block:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB16A>.
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| 61 |
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| 62 |
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| 63 |
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Dangling pin <DOA6> on block:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB16A>.
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| 66 |
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Dangling pin <DOA7> on block:<adm3a/display/Mram_atrbuf1/adm3a/display/Mram_atrbuf1.A>:<RAMB16_RAMB16A>.
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| 68 |
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| 69 |
11 |
samiam9512 |
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