URL https://opencores.org/ocsvn/cpu8080/cpu8080/trunk

Subversion Repositories cpu8080

[/] [cpu8080/] [trunk/] [project/] [_xmsgs/] [netgen.xmsgs] - Blame information for rev 11

Line No.	Rev	Author	Line
1	2	samiam9512
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8	11	samiam9512	`The generated Verilog netlist contains Xilinx SIMPRIM simulation primitives and has to be used with SIMPRIM simulation library for correct compilation and simulation.`
9	2	samiam9512
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