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[/] [cpu8080/] [trunk/] [project/] [_xmsgs/] [xst.xmsgs] - Blame information for rev 20

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Line No. Rev Author Line
1 2 samiam9512
2
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8 9 samiam9512
Input <addr<9:8>> is never used.
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Input <addr<1>> is never used.
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Found 6-bit latch for signal <comp>.
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Found 8-bit latch for signal <mask>.
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Found 8-bit latch for signal <datai>.
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Signal <resi> is assigned but never used.
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Signal <keyrel_r> is assigned but never used.
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State 0XXXXX is never reached in FSM <state>.
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32 11 samiam9512
Signal <line_cnt> is assigned but never used.
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35 11 samiam9512
Signal <pixel_cnt<15:4>> is assigned but never used.
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Signal <curatr<4>> is assigned but never used.
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Signal <blank> is assigned but never used.
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HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
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47 20 samiam9512
HDL ADVISOR - Mux Selector <fchsta> of Case statement line 867 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
48 11 samiam9512
        - add an 'INIT' attribute on signal <fchsta> (optimization is then done without any risk)
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        - use the attribute 'signal_encoding user' to avoid onehot optimization
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        - use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
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53 20 samiam9512
"vgachr.v" line 939: The result of a 9x6-bit multiplication is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
54 11 samiam9512
55
 
56 18 samiam9512
Signal <parity> is assigned but never used.
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59 20 samiam9512
Signal <cmattri<7:5>> is assigned but never used.
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62 18 samiam9512
Signal <error> is assigned but never used.
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65 20 samiam9512
"vgachr.v" line 682: The result of a 9x8-bit multiplication is partially used. Only the 11 least significant bits are used. If you are doing this on purpose, you may safely ignore this warning. Otherwise, make sure you are not losing information, leading to unexpected circuit behavior.
66 18 samiam9512
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68 9 samiam9512
HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
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71 18 samiam9512
 FFs/Latches <curchr<7:7>> (without init value) have a constant value of 0 in block <chrmemmap>.
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74 11 samiam9512
 FFs/Latches <chrdatw<7:7>> (without init value) have a constant value of 0 in block <terminal>.
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77 20 samiam9512
 FFs/Latches <rowchr<7:7>> (without init value) have a constant value of 0 in block <terminal>.
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80 9 samiam9512
Address input of ROM <rom/Mrom__mux0000> is tied to register <cpu/addr>.
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The register is removed and the ROM is implemented as read-only block RAM.
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FF/Latch  <datai_0> (without init value) has a constant value of 0 in block <select>.
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Due to other FF/Latch trimming, FF/Latch  <datai_1> (without init value) has a constant value of 0 in block <select>.
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Due to other FF/Latch trimming, FF/Latch  <datai_2> (without init value) has a constant value of 0 in block <select>.
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Due to other FF/Latch trimming, FF/Latch  <datai_3> (without init value) has a constant value of 0 in block <select>.
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97
 
98 18 samiam9512
The FF/Latch <rgb_r_0> in Unit <vga> is equivalent to the following 8 FFs/Latches, which will be removed : <rgb_r_1> <rgb_r_2> <rgb_r_3> <rgb_r_4> <rgb_r_5> <rgb_r_6> <rgb_r_7> <rgb_r_8> 
99 11 samiam9512
100 9 samiam9512
 
101 20 samiam9512
FF/Latch <cmattri_5> is unconnected in block <terminal>.
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FF/Latch <cmattri_6> is unconnected in block <terminal>.
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FF/Latch <cmattri_7> is unconnected in block <terminal>.
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110 18 samiam9512
FF/Latch <blank_r_3> is unconnected in block <vgai>.
111 11 samiam9512
112
 
113 20 samiam9512
Unit <chrmemmap>: instances <Mcompar__cmp_ge0001>, <Mcompar__cmp_lt0000> of unit <LPM_COMPARE_5> and unit <LPM_COMPARE_7> are dual, second instance is removed
114 11 samiam9512
115
 
116 20 samiam9512
Unit <chrmemmap>: instances <Mcompar__cmp_ge0002>, <Mcompar__cmp_lt0001> of unit <LPM_COMPARE_6> and unit <LPM_COMPARE_8> are dual, second instance is removed
117 11 samiam9512
118
 
119 20 samiam9512
Unit <terminal>: instances <Mcompar__cmp_gt0000>, <Mcompar__cmp_gt0003> of unit <LPM_COMPARE_13> are equivalent, second instance is removed
120 11 samiam9512
121
 
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FF/Latch <lincnt_0> is unconnected in block <chrmemmap>.
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FF/Latch <lincnt_1> is unconnected in block <chrmemmap>.
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FF/Latch <lincnt_2> is unconnected in block <chrmemmap>.
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FF/Latch <lincnt_3> is unconnected in block <chrmemmap>.
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FF/Latch <lincnt_4> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8421> is unconnected in block <chrmemmap>.
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140 11 samiam9512
FF/Latch <inst_Mram_mem8401> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8411> is unconnected in block <chrmemmap>.
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146 20 samiam9512
FF/Latch <inst_Mram_mem8431> is unconnected in block <chrmemmap>.
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148
 
149 20 samiam9512
FF/Latch <inst_Mram_mem8441> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8451> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8461> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8471> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8481> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8491> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8501> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8511> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8521> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8531> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8541> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8551> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8561> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8571> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8581> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8591> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8601> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8611> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8621> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8631> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8641> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8651> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8661> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8671> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8681> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8691> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8701> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8711> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8721> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8731> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8741> is unconnected in block <chrmemmap>.
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242 20 samiam9512
FF/Latch <inst_Mram_mem8751> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8761> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8771> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8781> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8791> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8801> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8811> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8821> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8831> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8841> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8851> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8861> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8871> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8881> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8891> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8901> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8911> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8921> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8931> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8941> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8951> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8961> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8971> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8981> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem8991> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9001> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9011> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9021> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9051> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9031> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9041> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9061> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9071> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9081> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9091> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9101> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9111> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9121> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9131> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9141> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9151> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9161> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9171> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9181> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9191> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9201> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9211> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9221> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9231> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9241> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9251> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9261> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9271> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9281> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9291> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9301> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9311> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9321> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9331> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9361> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9341> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9351> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9371> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9381> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9391> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9401> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9411> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9421> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9431> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9441> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9451> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9461> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9471> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9481> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9491> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9501> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9511> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9521> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9531> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9541> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9551> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9561> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9571> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9581> is unconnected in block <chrmemmap>.
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FF/Latch <inst_Mram_mem9591> is unconnected in block <chrmemmap>.
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FF/Latch  <scnadr_0> (without init value) has a constant value of 0 in block <chrmemmap>.
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Due to other FF/Latch trimming, FF/Latch  <scnadr_1> (without init value) has a constant value of 0 in block <chrmemmap>.
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Due to other FF/Latch trimming, FF/Latch  <scnadr_2> (without init value) has a constant value of 0 in block <chrmemmap>.
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Due to other FF/Latch trimming, FF/Latch  <scnadr_3> (without init value) has a constant value of 0 in block <chrmemmap>.
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Unit testbench: 21 multi-source signals are replaced by logic (pull-up yes): 
510 11 samiam9512
 
511 20 samiam9512
Unit chrmemmap: 13 internal tristates are replaced by logic (pull-up yes): 
512 18 samiam9512
 
513
FF/Latch <adm3a/display/vgai/blank_r_3> is unconnected in block <testbench>.
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515
 
516 20 samiam9512
HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/state_FFd7> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
517 11 samiam9512
518
 
519 18 samiam9512
HDL ADVISOR - A 2-bit shift register was found for signal <cpu/state_FFd1> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
520 11 samiam9512
521
 
522 20 samiam9512
HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/vgai/sc_r_8> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
523 11 samiam9512
524
 
525 18 samiam9512
HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/vgai/ps2_clk_r_2> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
526 11 samiam9512
527
 
528
HDL ADVISOR - A 2-bit shift register was found for signal <adm3a/display/vgai/blank_r_2> and currently occupies 2 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
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530
 
531
HDL ADVISOR - A 3-bit shift register was found for signal <adm3a/display/vgai/hsync_r_3> and currently occupies 3 logic cells (1 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
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533
 
534 9 samiam9512
HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
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537 2 samiam9512

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