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É^lTKK6__OBJSTORE__/ProjectNavigatorGui/GuiProjectData_StrTbl!Module|testbenchtestbench/testbench/cpu - cpu8080/testbench/select1 - selecttestbench (testbench.v)/cpu_tbw/UUT - testbench/cpu - cpu8080/cpu_tbw/UUT - testbench/select1 - selectcpu_tbw (cpu_tbw.tbw)xc3s200-5pq208Design UtilitiesDESUT_UCFUser ConstraintsDESUT_VERILOGGenerate Programming FileImplement DesignImplement Design/FitImplement Design/Generate Programming FileImplement Design/MapImplement Design/Map/Generate Post-Map Simulation ModelImplement Design/Map/Generate Post-Map Static TimingImplement Design/Optional Implementation ToolsImplement Design/Place & RouteImplement Design/Place & Route/Back-annotate Pin LocationsImplement Design/Place & Route/Generate IBIS ModelImplement Design/Place & Route/Generate Post-Place & Route Simulation ModelImplement Design/Place & Route/Generate Post-Place & Route Static TimingImplement Design/Place & Route/Generate Power DataImplement Design/Place & Route/MPPR Results UtilitiesImplement Design/Synthesize - XSTImplement Design/TranslateSynthesize - XST/Generate Post-Synthesis Simulation ModelDESUT_TBWPK
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