| 1 |
2 |
samiam9512 |
<html><head><link type='text/css' href='style.css' rel='stylesheet'></head><body class='pgBgnd'>
|
| 2 |
|
|
<h3 align='center'>Equations</h3>
|
| 3 |
|
|
<table width='90%' align='center' border='1' cellpadding='0' cellspacing='0'>
|
| 4 |
|
|
<tr><td>
|
| 5 |
|
|
</td></tr><tr><td>
|
| 6 |
|
|
********** UnMapped Logic **********
|
| 7 |
|
|
</td></tr><tr><td>
|
| 8 |
|
|
** Outputs **
|
| 9 |
|
|
</td></tr><tr><td>
|
| 10 |
|
|
FTCPE_addr0: FTCPE port map (addr(0),addr_T(0),clock,'0','0','1');
|
| 11 |
|
|
<br/> addr_T(0) <= ((addr(0) AND N_PZ_1066 AND NOT addrhold(0))
|
| 12 |
|
|
<br/> OR (addr(0) AND NOT pc(0) AND N_PZ_1065)
|
| 13 |
|
|
<br/> OR (NOT addr(0) AND N_PZ_1066 AND addrhold(0))
|
| 14 |
|
|
<br/> OR (NOT addr(0) AND pc(0) AND N_PZ_1065)
|
| 15 |
|
|
<br/> OR (NOT reset AND addr(0) AND state(3) AND NOT state(2) AND
|
| 16 |
|
|
<br/> NOT state(4) AND state(1) AND state(0) AND _xor0000)
|
| 17 |
|
|
<br/> OR (NOT reset AND NOT addr(0) AND state(3) AND NOT state(2) AND
|
| 18 |
|
|
<br/> NOT state(4) AND state(1) AND state(0) AND NOT _xor0000));
|
| 19 |
|
|
</td></tr><tr><td>
|
| 20 |
|
|
FDCPE_addr1: FDCPE port map (addr(1),addr_D(1),clock,'0','0','1');
|
| 21 |
|
|
<br/> addr_D(1) <= ((N_PZ_1066 AND addrhold(1))
|
| 22 |
|
|
<br/> OR (pc(1) AND N_PZ_1065)
|
| 23 |
|
|
<br/> OR (N_PZ_1246 AND addr(1)));
|
| 24 |
|
|
</td></tr><tr><td>
|
| 25 |
|
|
FTCPE_addr2: FTCPE port map (addr(2),addr_T(2),clock,'0','0','1');
|
| 26 |
|
|
<br/> addr_T(2) <= ((N_PZ_1066 AND addrhold(2) AND NOT addr(2))
|
| 27 |
|
|
<br/> OR (N_PZ_1066 AND NOT addrhold(2) AND addr(2))
|
| 28 |
|
|
<br/> OR (pc(2) AND N_PZ_1065 AND NOT addr(2))
|
| 29 |
|
|
<br/> OR (NOT pc(2) AND N_PZ_1065 AND addr(2))
|
| 30 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND
|
| 31 |
|
|
<br/> state(1) AND state(0) AND addr(2)));
|
| 32 |
|
|
</td></tr><tr><td>
|
| 33 |
|
|
FDCPE_addr3: FDCPE port map (addr(3),addr_D(3),clock,'0','0','1');
|
| 34 |
|
|
<br/> addr_D(3) <= ((N_PZ_1066 AND addrhold(3))
|
| 35 |
|
|
<br/> OR (pc(3) AND N_PZ_1065)
|
| 36 |
|
|
<br/> OR (N_PZ_1246 AND addr(3)));
|
| 37 |
|
|
</td></tr><tr><td>
|
| 38 |
|
|
FTCPE_addr4: FTCPE port map (addr(4),addr_T(4),clock,'0','0','1');
|
| 39 |
|
|
<br/> addr_T(4) <= ((N_PZ_1066 AND addrhold(4) AND NOT addr(4))
|
| 40 |
|
|
<br/> OR (N_PZ_1066 AND NOT addrhold(4) AND addr(4))
|
| 41 |
|
|
<br/> OR (pc(4) AND N_PZ_1065 AND NOT addr(4))
|
| 42 |
|
|
<br/> OR (NOT pc(4) AND N_PZ_1065 AND addr(4))
|
| 43 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND
|
| 44 |
|
|
<br/> state(1) AND state(0) AND addr(4)));
|
| 45 |
|
|
</td></tr><tr><td>
|
| 46 |
|
|
FDCPE_addr5: FDCPE port map (addr(5),addr_D(5),clock,'0','0','1');
|
| 47 |
|
|
<br/> addr_D(5) <= ((N_PZ_1066 AND addrhold(5))
|
| 48 |
|
|
<br/> OR (pc(5) AND N_PZ_1065)
|
| 49 |
|
|
<br/> OR (N_PZ_1246 AND addr(5)));
|
| 50 |
|
|
</td></tr><tr><td>
|
| 51 |
|
|
FTCPE_addr6: FTCPE port map (addr(6),addr_T(6),clock,'0','0','1');
|
| 52 |
|
|
<br/> addr_T(6) <= ((N_PZ_1066 AND addrhold(6) AND NOT addr(6))
|
| 53 |
|
|
<br/> OR (N_PZ_1066 AND NOT addrhold(6) AND addr(6))
|
| 54 |
|
|
<br/> OR (pc(6) AND N_PZ_1065 AND NOT addr(6))
|
| 55 |
|
|
<br/> OR (NOT pc(6) AND N_PZ_1065 AND addr(6))
|
| 56 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND
|
| 57 |
|
|
<br/> state(1) AND state(0) AND addr(6)));
|
| 58 |
|
|
</td></tr><tr><td>
|
| 59 |
|
|
FDCPE_addr7: FDCPE port map (addr(7),addr_D(7),clock,'0','0','1');
|
| 60 |
|
|
<br/> addr_D(7) <= ((N_PZ_1066 AND addrhold(7))
|
| 61 |
|
|
<br/> OR (pc(7) AND N_PZ_1065)
|
| 62 |
|
|
<br/> OR (N_PZ_1246 AND addr(7)));
|
| 63 |
|
|
</td></tr><tr><td>
|
| 64 |
|
|
FTCPE_addr8: FTCPE port map (addr(8),addr_T(8),clock,'0','0','1');
|
| 65 |
|
|
<br/> addr_T(8) <= ((N_PZ_1066 AND addrhold(8) AND NOT addr(8))
|
| 66 |
|
|
<br/> OR (N_PZ_1066 AND NOT addrhold(8) AND addr(8))
|
| 67 |
|
|
<br/> OR (pc(8) AND N_PZ_1065 AND NOT addr(8))
|
| 68 |
|
|
<br/> OR (NOT pc(8) AND N_PZ_1065 AND addr(8))
|
| 69 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND
|
| 70 |
|
|
<br/> state(1) AND state(0) AND addr(8)));
|
| 71 |
|
|
</td></tr><tr><td>
|
| 72 |
|
|
FDCPE_addr9: FDCPE port map (addr(9),addr_D(9),clock,'0','0','1');
|
| 73 |
|
|
<br/> addr_D(9) <= ((N_PZ_1066 AND addrhold(9))
|
| 74 |
|
|
<br/> OR (pc(9) AND N_PZ_1065)
|
| 75 |
|
|
<br/> OR (N_PZ_1246 AND addr(9)));
|
| 76 |
|
|
</td></tr><tr><td>
|
| 77 |
|
|
FTCPE_addr10: FTCPE port map (addr(10),addr_T(10),clock,'0','0','1');
|
| 78 |
|
|
<br/> addr_T(10) <= ((N_PZ_1066 AND addrhold(10) AND NOT addr(10))
|
| 79 |
|
|
<br/> OR (N_PZ_1066 AND NOT addrhold(10) AND addr(10))
|
| 80 |
|
|
<br/> OR (pc(10) AND N_PZ_1065 AND NOT addr(10))
|
| 81 |
|
|
<br/> OR (NOT pc(10) AND N_PZ_1065 AND addr(10))
|
| 82 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND
|
| 83 |
|
|
<br/> state(1) AND state(0) AND addr(10)));
|
| 84 |
|
|
</td></tr><tr><td>
|
| 85 |
|
|
FDCPE_addr11: FDCPE port map (addr(11),addr_D(11),clock,'0','0','1');
|
| 86 |
|
|
<br/> addr_D(11) <= ((N_PZ_1066 AND addrhold(11))
|
| 87 |
|
|
<br/> OR (pc(11) AND N_PZ_1065)
|
| 88 |
|
|
<br/> OR (addr(11) AND N_PZ_1246));
|
| 89 |
|
|
</td></tr><tr><td>
|
| 90 |
|
|
FTCPE_addr12: FTCPE port map (addr(12),addr_T(12),clock,'0','0','1');
|
| 91 |
|
|
<br/> addr_T(12) <= ((N_PZ_1066 AND addrhold(12) AND NOT addr(12))
|
| 92 |
|
|
<br/> OR (N_PZ_1066 AND NOT addrhold(12) AND addr(12))
|
| 93 |
|
|
<br/> OR (pc(12) AND N_PZ_1065 AND NOT addr(12))
|
| 94 |
|
|
<br/> OR (NOT pc(12) AND N_PZ_1065 AND addr(12))
|
| 95 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND
|
| 96 |
|
|
<br/> state(1) AND state(0) AND addr(12)));
|
| 97 |
|
|
</td></tr><tr><td>
|
| 98 |
|
|
FDCPE_addr13: FDCPE port map (addr(13),addr_D(13),clock,'0','0','1');
|
| 99 |
|
|
<br/> addr_D(13) <= ((N_PZ_1066 AND addrhold(13))
|
| 100 |
|
|
<br/> OR (pc(13) AND N_PZ_1065)
|
| 101 |
|
|
<br/> OR (N_PZ_1246 AND addr(13)));
|
| 102 |
|
|
</td></tr><tr><td>
|
| 103 |
|
|
FTCPE_addr14: FTCPE port map (addr(14),addr_T(14),clock,'0','0','1');
|
| 104 |
|
|
<br/> addr_T(14) <= ((N_PZ_1066 AND addrhold(14) AND NOT addr(14))
|
| 105 |
|
|
<br/> OR (N_PZ_1066 AND NOT addrhold(14) AND addr(14))
|
| 106 |
|
|
<br/> OR (pc(14) AND N_PZ_1065 AND NOT addr(14))
|
| 107 |
|
|
<br/> OR (NOT pc(14) AND N_PZ_1065 AND addr(14))
|
| 108 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND
|
| 109 |
|
|
<br/> state(1) AND state(0) AND addr(14)));
|
| 110 |
|
|
</td></tr><tr><td>
|
| 111 |
|
|
FDCPE_addr15: FDCPE port map (addr(15),addr_D(15),clock,'0','0','1');
|
| 112 |
|
|
<br/> addr_D(15) <= ((N_PZ_1066 AND addrhold(15))
|
| 113 |
|
|
<br/> OR (pc(15) AND N_PZ_1065)
|
| 114 |
|
|
<br/> OR (N_PZ_1246 AND addr(15)));
|
| 115 |
|
|
</td></tr><tr><td>
|
| 116 |
|
|
FTCPE_data0: FTCPE port map (data_I(0),data_T(0),clock,'0','0','1');
|
| 117 |
|
|
<br/> data_T(0) <= ((NOT reset AND state(3) AND state(2) AND state(4) AND
|
| 118 |
|
|
<br/> state(1) AND NOT state(0) AND regfil_4_0 AND NOT data(0))
|
| 119 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND state(4) AND
|
| 120 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_4_0 AND data(0))
|
| 121 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND
|
| 122 |
|
|
<br/> state(1) AND NOT state(0) AND regfil_5_0 AND NOT data(0))
|
| 123 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND
|
| 124 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_5_0 AND data(0))
|
| 125 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 126 |
|
|
<br/> state(1) AND NOT state(0) AND _COND_18(0) AND data(0))
|
| 127 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 128 |
|
|
<br/> state(1) AND NOT state(0) AND NOT _COND_18(0) AND NOT data(0)));
|
| 129 |
|
|
<br/> data(0) <= data_I(0) when data_OE(0) = '1' else 'Z';
|
| 130 |
|
|
<br/> data_OE(0) <= dataeno;
|
| 131 |
|
|
</td></tr><tr><td>
|
| 132 |
|
|
FTCPE_data1: FTCPE port map (data_I(1),data_T(1),clock,'0','0','1');
|
| 133 |
|
|
<br/> data_T(1) <= ((NOT reset AND state(3) AND state(2) AND state(4) AND
|
| 134 |
|
|
<br/> state(1) AND NOT state(0) AND regfil_4_1 AND NOT data(1))
|
| 135 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND state(4) AND
|
| 136 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_4_1 AND data(1))
|
| 137 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND
|
| 138 |
|
|
<br/> state(1) AND NOT state(0) AND regfil_5_1 AND NOT data(1))
|
| 139 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND
|
| 140 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_5_1 AND data(1))
|
| 141 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 142 |
|
|
<br/> state(1) AND NOT state(0) AND _COND_18(1) AND data(1))
|
| 143 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 144 |
|
|
<br/> state(1) AND NOT state(0) AND NOT _COND_18(1) AND NOT data(1)));
|
| 145 |
|
|
<br/> data(1) <= data_I(1) when data_OE(1) = '1' else 'Z';
|
| 146 |
|
|
<br/> data_OE(1) <= dataeno;
|
| 147 |
|
|
</td></tr><tr><td>
|
| 148 |
|
|
FTCPE_data2: FTCPE port map (data_I(2),data_T(2),clock,'0','0','1');
|
| 149 |
|
|
<br/> data_T(2) <= ((NOT reset AND state(3) AND state(2) AND state(4) AND
|
| 150 |
|
|
<br/> state(1) AND NOT state(0) AND regfil_4_2 AND NOT data(2))
|
| 151 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND state(4) AND
|
| 152 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_4_2 AND data(2))
|
| 153 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND
|
| 154 |
|
|
<br/> state(1) AND NOT state(0) AND regfil_5_2 AND NOT data(2))
|
| 155 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND
|
| 156 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_5_2 AND data(2))
|
| 157 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 158 |
|
|
<br/> state(1) AND NOT state(0) AND _COND_18(2) AND data(2))
|
| 159 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 160 |
|
|
<br/> state(1) AND NOT state(0) AND NOT _COND_18(2) AND NOT data(2)));
|
| 161 |
|
|
<br/> data(2) <= data_I(2) when data_OE(2) = '1' else 'Z';
|
| 162 |
|
|
<br/> data_OE(2) <= dataeno;
|
| 163 |
|
|
</td></tr><tr><td>
|
| 164 |
|
|
FTCPE_data3: FTCPE port map (data_I(3),data_T(3),clock,'0','0','1');
|
| 165 |
|
|
<br/> data_T(3) <= ((NOT reset AND state(3) AND state(2) AND state(4) AND
|
| 166 |
|
|
<br/> state(1) AND NOT state(0) AND regfil_4_3 AND NOT data(3))
|
| 167 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND state(4) AND
|
| 168 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_4_3 AND data(3))
|
| 169 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND
|
| 170 |
|
|
<br/> state(1) AND NOT state(0) AND regfil_5_3 AND NOT data(3))
|
| 171 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND
|
| 172 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_5_3 AND data(3))
|
| 173 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 174 |
|
|
<br/> state(1) AND NOT state(0) AND _COND_18(3) AND data(3))
|
| 175 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 176 |
|
|
<br/> state(1) AND NOT state(0) AND NOT _COND_18(3) AND NOT data(3)));
|
| 177 |
|
|
<br/> data(3) <= data_I(3) when data_OE(3) = '1' else 'Z';
|
| 178 |
|
|
<br/> data_OE(3) <= dataeno;
|
| 179 |
|
|
</td></tr><tr><td>
|
| 180 |
|
|
FTCPE_data4: FTCPE port map (data_I(4),data_T(4),clock,'0','0','1');
|
| 181 |
|
|
<br/> data_T(4) <= ((NOT reset AND state(3) AND state(2) AND state(4) AND
|
| 182 |
|
|
<br/> state(1) AND NOT state(0) AND regfil_4_4 AND NOT data(4))
|
| 183 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND state(4) AND
|
| 184 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_4_4 AND data(4))
|
| 185 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND
|
| 186 |
|
|
<br/> state(1) AND NOT state(0) AND regfil_5_4 AND NOT data(4))
|
| 187 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND
|
| 188 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_5_4 AND data(4))
|
| 189 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 190 |
|
|
<br/> state(1) AND NOT state(0) AND _COND_18(4) AND data(4))
|
| 191 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 192 |
|
|
<br/> state(1) AND NOT state(0) AND NOT _COND_18(4) AND NOT data(4)));
|
| 193 |
|
|
<br/> data(4) <= data_I(4) when data_OE(4) = '1' else 'Z';
|
| 194 |
|
|
<br/> data_OE(4) <= dataeno;
|
| 195 |
|
|
</td></tr><tr><td>
|
| 196 |
|
|
FTCPE_data5: FTCPE port map (data_I(5),data_T(5),clock,'0','0','1');
|
| 197 |
|
|
<br/> data_T(5) <= ((NOT reset AND state(3) AND state(2) AND state(4) AND
|
| 198 |
|
|
<br/> state(1) AND NOT state(0) AND regfil_4_5 AND NOT data(5))
|
| 199 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND state(4) AND
|
| 200 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_4_5 AND data(5))
|
| 201 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND
|
| 202 |
|
|
<br/> state(1) AND NOT state(0) AND regfil_5_5 AND NOT data(5))
|
| 203 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND
|
| 204 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_5_5 AND data(5))
|
| 205 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 206 |
|
|
<br/> state(1) AND NOT state(0) AND _COND_18(5) AND data(5))
|
| 207 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 208 |
|
|
<br/> state(1) AND NOT state(0) AND NOT _COND_18(5) AND NOT data(5)));
|
| 209 |
|
|
<br/> data(5) <= data_I(5) when data_OE(5) = '1' else 'Z';
|
| 210 |
|
|
<br/> data_OE(5) <= dataeno;
|
| 211 |
|
|
</td></tr><tr><td>
|
| 212 |
|
|
FTCPE_data6: FTCPE port map (data_I(6),data_T(6),clock,'0','0','1');
|
| 213 |
|
|
<br/> data_T(6) <= ((NOT reset AND state(3) AND state(2) AND state(4) AND
|
| 214 |
|
|
<br/> state(1) AND NOT state(0) AND regfil_4_6 AND NOT data(6))
|
| 215 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND state(4) AND
|
| 216 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_4_6 AND data(6))
|
| 217 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND
|
| 218 |
|
|
<br/> state(1) AND NOT state(0) AND regfil_5_6 AND NOT data(6))
|
| 219 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND
|
| 220 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_5_6 AND data(6))
|
| 221 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 222 |
|
|
<br/> state(1) AND NOT state(0) AND _COND_18(6) AND data(6))
|
| 223 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 224 |
|
|
<br/> state(1) AND NOT state(0) AND NOT _COND_18(6) AND NOT data(6)));
|
| 225 |
|
|
<br/> data(6) <= data_I(6) when data_OE(6) = '1' else 'Z';
|
| 226 |
|
|
<br/> data_OE(6) <= dataeno;
|
| 227 |
|
|
</td></tr><tr><td>
|
| 228 |
|
|
FTCPE_data7: FTCPE port map (data_I(7),data_T(7),clock,'0','0','1');
|
| 229 |
|
|
<br/> data_T(7) <= ((NOT reset AND state(3) AND state(2) AND state(4) AND
|
| 230 |
|
|
<br/> state(1) AND NOT state(0) AND regfil_4_7 AND NOT data(7))
|
| 231 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND state(4) AND
|
| 232 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_4_7 AND data(7))
|
| 233 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND
|
| 234 |
|
|
<br/> state(1) AND NOT state(0) AND regfil_5_7 AND NOT data(7))
|
| 235 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND state(4) AND
|
| 236 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_5_7 AND data(7))
|
| 237 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 238 |
|
|
<br/> state(1) AND NOT state(0) AND _COND_18(7) AND data(7))
|
| 239 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 240 |
|
|
<br/> state(1) AND NOT state(0) AND NOT _COND_18(7) AND NOT data(7)));
|
| 241 |
|
|
<br/> data(7) <= data_I(7) when data_OE(7) = '1' else 'Z';
|
| 242 |
|
|
<br/> data_OE(7) <= dataeno;
|
| 243 |
|
|
</td></tr><tr><td>
|
| 244 |
|
|
FTCPE_inta: FTCPE port map (inta,inta_T,clock,'0','0','1');
|
| 245 |
|
|
<br/> inta_T <= ((reset AND inta)
|
| 246 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND NOT state(1) AND
|
| 247 |
|
|
<br/> state(0) AND inta AND NOT intr)
|
| 248 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 249 |
|
|
<br/> NOT state(1) AND state(0) AND NOT inta AND intr));
|
| 250 |
|
|
</td></tr><tr><td>
|
| 251 |
|
|
</td></tr><tr><td>
|
| 252 |
|
|
readio <= '0';
|
| 253 |
|
|
</td></tr><tr><td>
|
| 254 |
|
|
FDCPE_readmem: FDCPE port map (readmem,readmem_D,clock,'0','0','1');
|
| 255 |
|
|
<br/> readmem_D <= NOT N_PZ_1246
|
| 256 |
|
|
<br/> XOR ((state(3) AND state(1) AND N_PZ_1066 AND NOT N_PZ_1246 AND
|
| 257 |
|
|
<br/> NOT readmem)
|
| 258 |
|
|
<br/> OR (NOT state(4) AND state(1) AND N_PZ_1066 AND NOT N_PZ_1246 AND
|
| 259 |
|
|
<br/> NOT readmem)
|
| 260 |
|
|
<br/> OR (NOT reset AND state(3) AND state(1) AND NOT state(0) AND
|
| 261 |
|
|
<br/> N_PZ_1246 AND readmem)
|
| 262 |
|
|
<br/> OR (NOT reset AND NOT state(2) AND state(4) AND state(1) AND
|
| 263 |
|
|
<br/> N_PZ_1246 AND readmem)
|
| 264 |
|
|
<br/> OR (NOT reset AND NOT state(2) AND NOT state(1) AND NOT state(0) AND
|
| 265 |
|
|
<br/> N_PZ_1246 AND readmem)
|
| 266 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(4) AND NOT state(1) AND
|
| 267 |
|
|
<br/> state(0) AND N_PZ_1246 AND readmem)
|
| 268 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(1) AND state(0) AND
|
| 269 |
|
|
<br/> NOT N_PZ_1948 AND N_PZ_1246 AND readmem)
|
| 270 |
|
|
<br/> OR (NOT reset AND state(2) AND state(4) AND NOT N_PZ_1066 AND
|
| 271 |
|
|
<br/> NOT N_PZ_1948 AND N_PZ_1246 AND readmem));
|
| 272 |
|
|
</td></tr><tr><td>
|
| 273 |
|
|
</td></tr><tr><td>
|
| 274 |
|
|
writeio <= '0';
|
| 275 |
|
|
</td></tr><tr><td>
|
| 276 |
|
|
FTCPE_writemem: FTCPE port map (writemem,writemem_T,clock,'0','0','1');
|
| 277 |
|
|
<br/> writemem_T <= ((reset AND writemem)
|
| 278 |
|
|
<br/> OR (NOT state(2) AND NOT state(4) AND NOT state(1) AND NOT state(0) AND
|
| 279 |
|
|
<br/> writemem)
|
| 280 |
|
|
<br/> OR (NOT reset AND state(3) AND state(4) AND state(1) AND
|
| 281 |
|
|
<br/> state(0) AND NOT writemem)
|
| 282 |
|
|
<br/> OR (state(3) AND state(2) AND state(4) AND NOT state(1) AND
|
| 283 |
|
|
<br/> NOT state(0) AND writemem)
|
| 284 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 285 |
|
|
<br/> state(1) AND state(0) AND NOT writemem));
|
| 286 |
|
|
</td></tr><tr><td>
|
| 287 |
|
|
** Buried Nodes **
|
| 288 |
|
|
</td></tr><tr><td>
|
| 289 |
|
|
</td></tr><tr><td>
|
| 290 |
|
|
Madd__AUX_10_Mxor_Result(12)__xor0000 <= (regfil_5_7 AND regfil_4_2 AND regfil_4_1 AND
|
| 291 |
|
|
<br/> regfil_4_0 AND regfil_4_3);
|
| 292 |
|
|
</td></tr><tr><td>
|
| 293 |
|
|
</td></tr><tr><td>
|
| 294 |
|
|
Madd__AUX_10__or0010 <= ((NOT regfil_4_3)
|
| 295 |
|
|
<br/> OR (regfil_5_7 AND regfil_4_2 AND regfil_4_1 AND
|
| 296 |
|
|
<br/> regfil_4_0));
|
| 297 |
|
|
</td></tr><tr><td>
|
| 298 |
|
|
</td></tr><tr><td>
|
| 299 |
|
|
Madd__AUX_11__or0001 <= ((regfil_5_2 AND sp(2))
|
| 300 |
|
|
<br/> OR (regfil_5_2 AND NOT sp(2) AND N_PZ_1725)
|
| 301 |
|
|
<br/> OR (NOT regfil_5_2 AND sp(2) AND N_PZ_1725));
|
| 302 |
|
|
</td></tr><tr><td>
|
| 303 |
|
|
</td></tr><tr><td>
|
| 304 |
|
|
Madd__AUX_11__or0006 <= ((NOT sp(7) AND N_PZ_1982)
|
| 305 |
|
|
<br/> OR (N_PZ_2108 AND N_PZ_2169 AND NOT N_PZ_1982)
|
| 306 |
|
|
<br/> OR (NOT N_PZ_2169 AND NOT sp(6) AND NOT N_PZ_1982));
|
| 307 |
|
|
</td></tr><tr><td>
|
| 308 |
|
|
</td></tr><tr><td>
|
| 309 |
|
|
Madd__AUX_11__or0008 <= ((NOT regfil_4_1 AND NOT sp(9))
|
| 310 |
|
|
<br/> OR (NOT regfil_4_1 AND NOT N_PZ_2362)
|
| 311 |
|
|
<br/> OR (NOT sp(9) AND NOT N_PZ_2362));
|
| 312 |
|
|
</td></tr><tr><td>
|
| 313 |
|
|
</td></tr><tr><td>
|
| 314 |
|
|
Madd__AUX_11__or0009 <= ((NOT regfil_4_2 AND NOT sp(10))
|
| 315 |
|
|
<br/> OR (NOT regfil_4_2 AND Madd__AUX_11__or0008)
|
| 316 |
|
|
<br/> OR (NOT sp(10) AND Madd__AUX_11__or0008));
|
| 317 |
|
|
</td></tr><tr><td>
|
| 318 |
|
|
</td></tr><tr><td>
|
| 319 |
|
|
Madd__AUX_11__or0010 <= ((NOT regfil_4_3 AND NOT sp(11))
|
| 320 |
|
|
<br/> OR (regfil_4_3 AND NOT sp(11) AND Madd__AUX_11__or0009)
|
| 321 |
|
|
<br/> OR (NOT regfil_4_3 AND sp(11) AND Madd__AUX_11__or0009));
|
| 322 |
|
|
</td></tr><tr><td>
|
| 323 |
|
|
</td></tr><tr><td>
|
| 324 |
|
|
Madd__AUX_11__or0012 <= ((N_PZ_1848 AND NOT sp(13))
|
| 325 |
|
|
<br/> OR (Madd__AUX_11__or0010 AND NOT N_PZ_1929 AND NOT N_PZ_1848)
|
| 326 |
|
|
<br/> OR (N_PZ_1929 AND NOT sp(12) AND NOT N_PZ_1848));
|
| 327 |
|
|
</td></tr><tr><td>
|
| 328 |
|
|
</td></tr><tr><td>
|
| 329 |
|
|
Madd__AUX_8__or0008 <= ((regfil_0_1 AND _addsub0000(9))
|
| 330 |
|
|
<br/> OR (regfil_4_1 AND regfil_0_0 AND N_PZ_1870)
|
| 331 |
|
|
<br/> OR (regfil_0_1 AND regfil_0_0 AND N_PZ_1870));
|
| 332 |
|
|
</td></tr><tr><td>
|
| 333 |
|
|
</td></tr><tr><td>
|
| 334 |
|
|
Madd__AUX_8__or0009 <= ((NOT regfil_0_2 AND NOT Madd__AUX_8__or0008)
|
| 335 |
|
|
<br/> OR (regfil_4_2 AND NOT regfil_0_2 AND N_PZ_1913)
|
| 336 |
|
|
<br/> OR (regfil_4_2 AND N_PZ_1913 AND NOT Madd__AUX_8__or0008)
|
| 337 |
|
|
<br/> OR (NOT regfil_4_2 AND NOT regfil_0_2 AND NOT N_PZ_1913)
|
| 338 |
|
|
<br/> OR (NOT regfil_4_2 AND NOT N_PZ_1913 AND NOT Madd__AUX_8__or0008));
|
| 339 |
|
|
</td></tr><tr><td>
|
| 340 |
|
|
</td></tr><tr><td>
|
| 341 |
|
|
Madd__AUX_8__or0010 <= ((NOT _addsub0000(11) AND Madd__AUX_8__or0009)
|
| 342 |
|
|
<br/> OR (NOT regfil_0_3 AND _addsub0000(11) AND
|
| 343 |
|
|
<br/> Madd__AUX_8__or0009)
|
| 344 |
|
|
<br/> OR (NOT regfil_0_3 AND NOT _addsub0000(11) AND
|
| 345 |
|
|
<br/> NOT Madd__AUX_8__or0009));
|
| 346 |
|
|
</td></tr><tr><td>
|
| 347 |
|
|
</td></tr><tr><td>
|
| 348 |
|
|
Madd__AUX_8__or0011 <= ((NOT regfil_0_4 AND NOT _addsub0000(12))
|
| 349 |
|
|
<br/> OR (NOT regfil_0_4 AND Madd__AUX_8__or0010)
|
| 350 |
|
|
<br/> OR (NOT _addsub0000(12) AND Madd__AUX_8__or0010));
|
| 351 |
|
|
</td></tr><tr><td>
|
| 352 |
|
|
</td></tr><tr><td>
|
| 353 |
|
|
Madd__AUX_9__or0008 <= (NOT regfil_4_1 AND N_PZ_2057)
|
| 354 |
|
|
<br/> XOR ((NOT regfil_2_1 AND NOT N_PZ_2057)
|
| 355 |
|
|
<br/> OR (regfil_4_0 AND NOT Madd__addsub0001__or0006 AND
|
| 356 |
|
|
<br/> N_PZ_2057));
|
| 357 |
|
|
</td></tr><tr><td>
|
| 358 |
|
|
</td></tr><tr><td>
|
| 359 |
|
|
Madd__AUX_9__or0011 <= ((NOT regfil_2_4 AND NOT _addsub0001(12))
|
| 360 |
|
|
<br/> OR (NOT regfil_2_3 AND NOT regfil_2_4 AND NOT N_PZ_2052)
|
| 361 |
|
|
<br/> OR (NOT regfil_2_3 AND NOT _addsub0001(12) AND NOT N_PZ_2052)
|
| 362 |
|
|
<br/> OR (NOT regfil_2_4 AND NOT _addsub0001(11) AND N_PZ_2052)
|
| 363 |
|
|
<br/> OR (NOT _addsub0001(11) AND NOT _addsub0001(12) AND N_PZ_2052));
|
| 364 |
|
|
</td></tr><tr><td>
|
| 365 |
|
|
</td></tr><tr><td>
|
| 366 |
|
|
Madd__addsub0000__or0000 <= ((regfil_5_1 AND regfil_1_1)
|
| 367 |
|
|
<br/> OR (regfil_5_0 AND regfil_1_0 AND regfil_5_1)
|
| 368 |
|
|
<br/> OR (regfil_5_0 AND regfil_1_0 AND regfil_1_1));
|
| 369 |
|
|
</td></tr><tr><td>
|
| 370 |
|
|
</td></tr><tr><td>
|
| 371 |
|
|
Madd__addsub0000__or0002 <= ((NOT regfil_5_3 AND NOT regfil_1_3)
|
| 372 |
|
|
<br/> OR (NOT regfil_5_3 AND N_PZ_2004)
|
| 373 |
|
|
<br/> OR (NOT regfil_1_3 AND N_PZ_2004));
|
| 374 |
|
|
</td></tr><tr><td>
|
| 375 |
|
|
</td></tr><tr><td>
|
| 376 |
|
|
Madd__addsub0000__or0004 <= ((NOT regfil_5_5 AND NOT regfil_1_5)
|
| 377 |
|
|
<br/> OR (regfil_5_5 AND NOT regfil_1_5 AND N_PZ_2148)
|
| 378 |
|
|
<br/> OR (NOT regfil_5_5 AND regfil_1_5 AND N_PZ_2148));
|
| 379 |
|
|
</td></tr><tr><td>
|
| 380 |
|
|
</td></tr><tr><td>
|
| 381 |
|
|
Madd__addsub0000__or0006 <= ((NOT regfil_5_7 AND NOT regfil_1_7)
|
| 382 |
|
|
<br/> OR (regfil_5_7 AND NOT regfil_1_7 AND N_PZ_2147)
|
| 383 |
|
|
<br/> OR (NOT regfil_5_7 AND regfil_1_7 AND N_PZ_2147));
|
| 384 |
|
|
</td></tr><tr><td>
|
| 385 |
|
|
</td></tr><tr><td>
|
| 386 |
|
|
Madd__addsub0001__or0000 <= ((regfil_3_1 AND regfil_5_1)
|
| 387 |
|
|
<br/> OR (regfil_5_0 AND regfil_3_0 AND regfil_3_1)
|
| 388 |
|
|
<br/> OR (regfil_5_0 AND regfil_3_0 AND regfil_5_1));
|
| 389 |
|
|
</td></tr><tr><td>
|
| 390 |
|
|
</td></tr><tr><td>
|
| 391 |
|
|
Madd__addsub0001__or0006 <= ((NOT regfil_5_7 AND N_PZ_2050)
|
| 392 |
|
|
<br/> OR (NOT regfil_3_7 AND NOT N_PZ_2050));
|
| 393 |
|
|
</td></tr><tr><td>
|
| 394 |
|
|
</td></tr><tr><td>
|
| 395 |
|
|
N_PZ_1038 <= ((aluoprb(5) AND NOT aluopra(5))
|
| 396 |
|
|
<br/> OR (NOT aluoprb(5) AND aluopra(5)));
|
| 397 |
|
|
</td></tr><tr><td>
|
| 398 |
|
|
</td></tr><tr><td>
|
| 399 |
|
|
N_PZ_1041 <= ((aluoprb(2) AND aluopra(2))
|
| 400 |
|
|
<br/> OR (NOT aluoprb(2) AND NOT aluopra(2)));
|
| 401 |
|
|
</td></tr><tr><td>
|
| 402 |
|
|
</td></tr><tr><td>
|
| 403 |
|
|
N_PZ_1043 <= ((aluoprb(1) AND NOT aluopra(1))
|
| 404 |
|
|
<br/> OR (NOT aluoprb(1) AND aluopra(1)));
|
| 405 |
|
|
</td></tr><tr><td>
|
| 406 |
|
|
</td></tr><tr><td>
|
| 407 |
|
|
N_PZ_1054 <= ((aluopra(4) AND NOT aluoprb(4))
|
| 408 |
|
|
<br/> OR (NOT aluopra(4) AND aluoprb(4)));
|
| 409 |
|
|
</td></tr><tr><td>
|
| 410 |
|
|
</td></tr><tr><td>
|
| 411 |
|
|
N_PZ_1059 <= ((aluoprb(6) AND NOT aluopra(6))
|
| 412 |
|
|
<br/> OR (NOT aluoprb(6) AND aluopra(6)));
|
| 413 |
|
|
</td></tr><tr><td>
|
| 414 |
|
|
</td></tr><tr><td>
|
| 415 |
|
|
N_PZ_1060 <= ((NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND
|
| 416 |
|
|
<br/> state(1) AND NOT state(0))
|
| 417 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 418 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND regd(0)));
|
| 419 |
|
|
</td></tr><tr><td>
|
| 420 |
|
|
</td></tr><tr><td>
|
| 421 |
|
|
N_PZ_1061 <= ((NOT reset AND state(3) AND NOT state(2) AND state(4) AND
|
| 422 |
|
|
<br/> NOT state(1) AND state(0))
|
| 423 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 424 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0)));
|
| 425 |
|
|
</td></tr><tr><td>
|
| 426 |
|
|
</td></tr><tr><td>
|
| 427 |
|
|
N_PZ_1062 <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 428 |
|
|
<br/> state(1) AND state(0))
|
| 429 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 430 |
|
|
<br/> NOT state(1) AND state(0) AND N_PZ_1129));
|
| 431 |
|
|
</td></tr><tr><td>
|
| 432 |
|
|
</td></tr><tr><td>
|
| 433 |
|
|
N_PZ_1065 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 434 |
|
|
<br/> state(1) AND NOT state(0))
|
| 435 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 436 |
|
|
<br/> NOT state(1) AND NOT state(0))
|
| 437 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 438 |
|
|
<br/> NOT state(1) AND state(0)));
|
| 439 |
|
|
</td></tr><tr><td>
|
| 440 |
|
|
</td></tr><tr><td>
|
| 441 |
|
|
N_PZ_1066 <= ((NOT reset AND state(3) AND NOT state(2) AND state(4) AND
|
| 442 |
|
|
<br/> NOT state(0))
|
| 443 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 444 |
|
|
<br/> NOT state(0))
|
| 445 |
|
|
<br/> OR (NOT reset AND state(2) AND state(4) AND state(1) AND
|
| 446 |
|
|
<br/> NOT state(0)));
|
| 447 |
|
|
</td></tr><tr><td>
|
| 448 |
|
|
</td></tr><tr><td>
|
| 449 |
|
|
N_PZ_1076 <= ((aluoprb(0) AND NOT aluopra(0))
|
| 450 |
|
|
<br/> OR (NOT aluoprb(0) AND aluopra(0)));
|
| 451 |
|
|
</td></tr><tr><td>
|
| 452 |
|
|
</td></tr><tr><td>
|
| 453 |
|
|
N_PZ_1082 <= ((aluoprb(3) AND NOT aluopra(3))
|
| 454 |
|
|
<br/> OR (NOT aluoprb(3) AND aluopra(3)));
|
| 455 |
|
|
</td></tr><tr><td>
|
| 456 |
|
|
</td></tr><tr><td>
|
| 457 |
|
|
N_PZ_1092 <= ((aluoprb(7) AND NOT aluopra(7))
|
| 458 |
|
|
<br/> OR (NOT aluoprb(7) AND aluopra(7)));
|
| 459 |
|
|
</td></tr><tr><td>
|
| 460 |
|
|
</td></tr><tr><td>
|
| 461 |
|
|
N_PZ_1099 <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 462 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN)
|
| 463 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 464 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND
|
| 465 |
|
|
<br/> NOT data(6).PIN));
|
| 466 |
|
|
</td></tr><tr><td>
|
| 467 |
|
|
</td></tr><tr><td>
|
| 468 |
|
|
N_PZ_1100 <= ((N_PZ_1528)
|
| 469 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 470 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 471 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN));
|
| 472 |
|
|
</td></tr><tr><td>
|
| 473 |
|
|
</td></tr><tr><td>
|
| 474 |
|
|
N_PZ_1117 <= ((reset)
|
| 475 |
|
|
<br/> OR (NOT N_PZ_1209)
|
| 476 |
|
|
<br/> OR (NOT state(0) AND data(0).PIN AND data(6).PIN AND
|
| 477 |
|
|
<br/> data(7).PIN));
|
| 478 |
|
|
</td></tr><tr><td>
|
| 479 |
|
|
</td></tr><tr><td>
|
| 480 |
|
|
N_PZ_1122 <= (regfil_5_3 AND regfil_5_0 AND regfil_5_1 AND
|
| 481 |
|
|
<br/> regfil_5_2 AND regfil_5_4);
|
| 482 |
|
|
</td></tr><tr><td>
|
| 483 |
|
|
</td></tr><tr><td>
|
| 484 |
|
|
N_PZ_1129 <= (regd(2) AND NOT regd(1) AND regd(0));
|
| 485 |
|
|
</td></tr><tr><td>
|
| 486 |
|
|
</td></tr><tr><td>
|
| 487 |
|
|
N_PZ_1133 <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 488 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 489 |
|
|
<br/> NOT _cmp_eq0004 AND N_PZ_1921)
|
| 490 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 491 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(2).PIN AND data(1).PIN AND
|
| 492 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT data(5).PIN));
|
| 493 |
|
|
</td></tr><tr><td>
|
| 494 |
|
|
</td></tr><tr><td>
|
| 495 |
|
|
N_PZ_1141 <= ((alusel(1) AND alusel(2) AND aluopra(5))
|
| 496 |
|
|
<br/> OR (NOT alusel(1) AND m1/Mmux__old_resi_28_I3_Result28 AND
|
| 497 |
|
|
<br/> m1/_addsub0000(5))
|
| 498 |
|
|
<br/> OR (alusel(1) AND NOT alusel(0) AND alusel(2) AND aluoprb(5))
|
| 499 |
|
|
<br/> OR (alusel(1) AND NOT alusel(2) AND m1/Msub__AUX_23__xor0013 AND
|
| 500 |
|
|
<br/> m1/Msub__AUX_23__xor0010)
|
| 501 |
|
|
<br/> OR (alusel(1) AND NOT alusel(2) AND m1/Msub__AUX_23__xor0013 AND
|
| 502 |
|
|
<br/> NOT N_PZ_1999)
|
| 503 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND alusel(2) AND N_PZ_1038)
|
| 504 |
|
|
<br/> OR (NOT alusel(1) AND NOT alusel(2) AND NOT m1/_addsub0000(4) AND
|
| 505 |
|
|
<br/> m1/_addsub0000(5))
|
| 506 |
|
|
<br/> OR (NOT alusel(0) AND alusel(2) AND aluoprb(5) AND aluopra(5))
|
| 507 |
|
|
<br/> OR (NOT alusel(1) AND NOT alusel(2) AND
|
| 508 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I3_Result28 AND m1/_addsub0000(4) AND NOT m1/_addsub0000(5))
|
| 509 |
|
|
<br/> OR (alusel(1) AND m1/Mmux__old_resi_28_I3_Result28 AND
|
| 510 |
|
|
<br/> NOT m1/Msub__AUX_23__xor0013 AND NOT m1/Msub__AUX_23__xor0010 AND
|
| 511 |
|
|
<br/> NOT m1/Msub__AUX_23__xor0007 AND NOT N_PZ_1926 AND N_PZ_2177));
|
| 512 |
|
|
</td></tr><tr><td>
|
| 513 |
|
|
</td></tr><tr><td>
|
| 514 |
|
|
N_PZ_1143 <= (regfil_5_5 AND regfil_5_6 AND N_PZ_1122);
|
| 515 |
|
|
</td></tr><tr><td>
|
| 516 |
|
|
</td></tr><tr><td>
|
| 517 |
|
|
N_PZ_1145 <= ((NOT N_PZ_1117)
|
| 518 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 519 |
|
|
<br/> state(1) AND NOT state(0) AND N_PZ_2236));
|
| 520 |
|
|
</td></tr><tr><td>
|
| 521 |
|
|
</td></tr><tr><td>
|
| 522 |
|
|
N_PZ_1157 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 523 |
|
|
<br/> NOT state(1) AND state(0) AND alures(3))
|
| 524 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 525 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 526 |
|
|
<br/> NOT _cmp_eq0004 AND NOT N_PZ_1373 AND NOT _COND_18(3)));
|
| 527 |
|
|
</td></tr><tr><td>
|
| 528 |
|
|
</td></tr><tr><td>
|
| 529 |
|
|
N_PZ_1209 <= ((reset)
|
| 530 |
|
|
<br/> OR (state(3) AND state(2) AND NOT state(4) AND state(1) AND
|
| 531 |
|
|
<br/> state(0))
|
| 532 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND state(4) AND NOT state(1) AND
|
| 533 |
|
|
<br/> state(0))
|
| 534 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 535 |
|
|
<br/> NOT state(0)));
|
| 536 |
|
|
</td></tr><tr><td>
|
| 537 |
|
|
</td></tr><tr><td>
|
| 538 |
|
|
N_PZ_1213 <= (NOT alusel(1) AND NOT alusel(2) AND m1/_addsub0000(2))
|
| 539 |
|
|
<br/> XOR ((alusel(1) AND alusel(2) AND aluopra(2))
|
| 540 |
|
|
<br/> OR (alusel(1) AND NOT alusel(0) AND alusel(2) AND aluoprb(2))
|
| 541 |
|
|
<br/> OR (alusel(1) AND NOT alusel(0) AND NOT alusel(2) AND N_PZ_1926)
|
| 542 |
|
|
<br/> OR (alusel(1) AND NOT alusel(2) AND N_PZ_1926 AND NOT N_PZ_2177)
|
| 543 |
|
|
<br/> OR (alusel(1) AND m1/Mmux__old_resi_28_I7_Result30 AND
|
| 544 |
|
|
<br/> NOT N_PZ_1926 AND N_PZ_2177)
|
| 545 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND alusel(2) AND NOT N_PZ_1041)
|
| 546 |
|
|
<br/> OR (NOT alusel(1) AND alusel(2) AND
|
| 547 |
|
|
<br/> m1/Mmux__old_resi_28_I7_Result30 AND m1/_addsub0000(2))
|
| 548 |
|
|
<br/> OR (NOT alusel(0) AND alusel(2) AND aluoprb(2) AND aluopra(2))
|
| 549 |
|
|
<br/> OR (NOT alusel(1) AND NOT alusel(2) AND
|
| 550 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I7_Result30 AND N_PZ_1076 AND N_PZ_1043));
|
| 551 |
|
|
</td></tr><tr><td>
|
| 552 |
|
|
</td></tr><tr><td>
|
| 553 |
|
|
N_PZ_1214 <= (alusel(1) AND NOT alusel(2) AND m1/Msub__AUX_23__xor0019)
|
| 554 |
|
|
<br/> XOR ((alusel(1) AND alusel(2) AND aluopra(7))
|
| 555 |
|
|
<br/> OR (alusel(1) AND NOT alusel(0) AND alusel(2) AND aluoprb(7))
|
| 556 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND alusel(2) AND N_PZ_1092)
|
| 557 |
|
|
<br/> OR (NOT alusel(1) AND NOT alusel(2) AND NOT m1/_addsub0000(6) AND
|
| 558 |
|
|
<br/> m1/_addsub0000(7))
|
| 559 |
|
|
<br/> OR (NOT alusel(1) AND m1/Mmux__old_resi_28_I3_Result28 AND
|
| 560 |
|
|
<br/> m1/_addsub0000(6) AND m1/_addsub0000(7))
|
| 561 |
|
|
<br/> OR (NOT alusel(0) AND alusel(2) AND aluoprb(7) AND aluopra(7))
|
| 562 |
|
|
<br/> OR (NOT alusel(1) AND NOT alusel(2) AND NOT m1/_addsub0000(4) AND
|
| 563 |
|
|
<br/> m1/_addsub0000(6) AND m1/_addsub0000(7))
|
| 564 |
|
|
<br/> OR (NOT alusel(1) AND NOT alusel(2) AND m1/_addsub0000(6) AND
|
| 565 |
|
|
<br/> NOT m1/_addsub0000(5) AND m1/_addsub0000(7))
|
| 566 |
|
|
<br/> OR (alusel(1) AND NOT alusel(2) AND m1/Msub__AUX_23__xor0019 AND
|
| 567 |
|
|
<br/> NOT m1/Msub__AUX_23__xor0016 AND NOT m1/Msub__AUX_23__xor0013 AND
|
| 568 |
|
|
<br/> NOT m1/Msub__AUX_23__xor0010 AND N_PZ_1999)
|
| 569 |
|
|
<br/> OR (NOT alusel(1) AND NOT alusel(2) AND
|
| 570 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I3_Result28 AND m1/_addsub0000(4) AND m1/_addsub0000(6) AND
|
| 571 |
|
|
<br/> m1/_addsub0000(5) AND NOT m1/_addsub0000(7))
|
| 572 |
|
|
<br/> OR (alusel(1) AND m1/Mmux__old_resi_28_I3_Result28 AND
|
| 573 |
|
|
<br/> NOT m1/Msub__AUX_23__xor0019 AND NOT m1/Msub__AUX_23__xor0016 AND
|
| 574 |
|
|
<br/> NOT m1/Msub__AUX_23__xor0013 AND NOT m1/Msub__AUX_23__xor0010 AND
|
| 575 |
|
|
<br/> NOT m1/Msub__AUX_23__xor0007 AND NOT N_PZ_1926 AND N_PZ_2177));
|
| 576 |
|
|
</td></tr><tr><td>
|
| 577 |
|
|
</td></tr><tr><td>
|
| 578 |
|
|
N_PZ_1223 <= (N_PZ_2021 AND pc(10) AND pc(8) AND pc(9) AND pc(11));
|
| 579 |
|
|
</td></tr><tr><td>
|
| 580 |
|
|
</td></tr><tr><td>
|
| 581 |
|
|
N_PZ_1246 <= ((N_PZ_1209)
|
| 582 |
|
|
<br/> OR (state(4) AND state(0))
|
| 583 |
|
|
<br/> OR (state(3) AND NOT state(1) AND state(0))
|
| 584 |
|
|
<br/> OR (NOT state(3) AND NOT N_PZ_1066 AND NOT N_PZ_1065)
|
| 585 |
|
|
<br/> OR (NOT N_PZ_1066 AND NOT state(0) AND NOT N_PZ_1065));
|
| 586 |
|
|
</td></tr><tr><td>
|
| 587 |
|
|
</td></tr><tr><td>
|
| 588 |
|
|
N_PZ_1260 <= (NOT alusel(1) AND NOT alusel(2) AND m1/_addsub0000(3))
|
| 589 |
|
|
<br/> XOR ((alusel(1) AND alusel(2) AND aluopra(3))
|
| 590 |
|
|
<br/> OR (alusel(1) AND NOT alusel(0) AND alusel(2) AND aluoprb(3))
|
| 591 |
|
|
<br/> OR (alusel(1) AND NOT alusel(0) AND NOT alusel(2) AND
|
| 592 |
|
|
<br/> m1/Msub__AUX_23__xor0007)
|
| 593 |
|
|
<br/> OR (alusel(1) AND NOT alusel(2) AND m1/Msub__AUX_23__xor0007 AND
|
| 594 |
|
|
<br/> N_PZ_1926)
|
| 595 |
|
|
<br/> OR (alusel(1) AND NOT alusel(2) AND m1/Msub__AUX_23__xor0007 AND
|
| 596 |
|
|
<br/> NOT N_PZ_2177)
|
| 597 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND alusel(2) AND N_PZ_1082)
|
| 598 |
|
|
<br/> OR (NOT alusel(0) AND alusel(2) AND aluoprb(3) AND aluopra(3))
|
| 599 |
|
|
<br/> OR (alusel(1) AND m1/Mmux__old_resi_28_I7_Result30 AND
|
| 600 |
|
|
<br/> NOT m1/Msub__AUX_23__xor0007 AND NOT N_PZ_1926 AND N_PZ_2177)
|
| 601 |
|
|
<br/> OR (NOT alusel(1) AND alusel(2) AND
|
| 602 |
|
|
<br/> m1/Mmux__old_resi_28_I7_Result30 AND m1/_addsub0000(2) AND m1/_addsub0000(3))
|
| 603 |
|
|
<br/> OR (NOT alusel(1) AND NOT alusel(2) AND
|
| 604 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I7_Result30 AND N_PZ_1076 AND N_PZ_1043 AND m1/_addsub0000(2)));
|
| 605 |
|
|
</td></tr><tr><td>
|
| 606 |
|
|
</td></tr><tr><td>
|
| 607 |
|
|
N_PZ_1261 <= (alusel(1) AND NOT alusel(2) AND m1/Msub__AUX_23__xor0016)
|
| 608 |
|
|
<br/> XOR ((alusel(1) AND alusel(2) AND aluopra(6))
|
| 609 |
|
|
<br/> OR (NOT alusel(1) AND m1/Mmux__old_resi_28_I3_Result28 AND
|
| 610 |
|
|
<br/> m1/_addsub0000(6))
|
| 611 |
|
|
<br/> OR (alusel(1) AND NOT alusel(0) AND alusel(2) AND aluoprb(6))
|
| 612 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND alusel(2) AND N_PZ_1059)
|
| 613 |
|
|
<br/> OR (NOT alusel(1) AND NOT alusel(2) AND NOT m1/_addsub0000(4) AND
|
| 614 |
|
|
<br/> m1/_addsub0000(6))
|
| 615 |
|
|
<br/> OR (NOT alusel(1) AND NOT alusel(2) AND m1/_addsub0000(6) AND
|
| 616 |
|
|
<br/> NOT m1/_addsub0000(5))
|
| 617 |
|
|
<br/> OR (NOT alusel(0) AND alusel(2) AND aluoprb(6) AND aluopra(6))
|
| 618 |
|
|
<br/> OR (alusel(1) AND m1/Mmux__old_resi_28_I3_Result28 AND
|
| 619 |
|
|
<br/> NOT m1/Msub__AUX_23__xor0016 AND NOT m1/Msub__AUX_23__xor0013 AND
|
| 620 |
|
|
<br/> NOT m1/Msub__AUX_23__xor0010)
|
| 621 |
|
|
<br/> OR (alusel(1) AND NOT alusel(2) AND
|
| 622 |
|
|
<br/> m1/Mmux__old_resi_28_I3_Result28 AND m1/Msub__AUX_23__xor0016 AND
|
| 623 |
|
|
<br/> NOT m1/Msub__AUX_23__xor0013 AND NOT m1/Msub__AUX_23__xor0010)
|
| 624 |
|
|
<br/> OR (NOT alusel(1) AND NOT alusel(2) AND
|
| 625 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I3_Result28 AND m1/_addsub0000(4) AND NOT m1/_addsub0000(6) AND
|
| 626 |
|
|
<br/> m1/_addsub0000(5)));
|
| 627 |
|
|
</td></tr><tr><td>
|
| 628 |
|
|
</td></tr><tr><td>
|
| 629 |
|
|
N_PZ_1262 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 630 |
|
|
<br/> NOT state(1) AND state(0) AND alures(1))
|
| 631 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 632 |
|
|
<br/> NOT state(1) AND state(0) AND data(1).PIN)
|
| 633 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 634 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 635 |
|
|
<br/> NOT _cmp_eq0004 AND NOT N_PZ_1373 AND NOT _COND_18(1)));
|
| 636 |
|
|
</td></tr><tr><td>
|
| 637 |
|
|
</td></tr><tr><td>
|
| 638 |
|
|
N_PZ_1265 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 639 |
|
|
<br/> NOT state(1) AND state(0) AND alures(5))
|
| 640 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 641 |
|
|
<br/> NOT state(1) AND state(0) AND data(5).PIN)
|
| 642 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 643 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 644 |
|
|
<br/> NOT _cmp_eq0004 AND NOT N_PZ_1373 AND NOT _COND_18(5)));
|
| 645 |
|
|
</td></tr><tr><td>
|
| 646 |
|
|
</td></tr><tr><td>
|
| 647 |
|
|
N_PZ_1266 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 648 |
|
|
<br/> NOT state(1) AND state(0) AND alures(7))
|
| 649 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 650 |
|
|
<br/> NOT state(1) AND state(0) AND data(7).PIN)
|
| 651 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 652 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 653 |
|
|
<br/> NOT _cmp_eq0004 AND NOT _COND_18(7) AND NOT N_PZ_1373));
|
| 654 |
|
|
</td></tr><tr><td>
|
| 655 |
|
|
</td></tr><tr><td>
|
| 656 |
|
|
N_PZ_1268 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 657 |
|
|
<br/> NOT state(1) AND state(0) AND NOT alures(0))
|
| 658 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 659 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(0).PIN)
|
| 660 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 661 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 662 |
|
|
<br/> NOT _cmp_eq0004 AND _COND_18(0) AND NOT N_PZ_1373));
|
| 663 |
|
|
</td></tr><tr><td>
|
| 664 |
|
|
</td></tr><tr><td>
|
| 665 |
|
|
N_PZ_1347 <= (regfil_4_2 AND regfil_4_1 AND regfil_4_0 AND
|
| 666 |
|
|
<br/> regfil_4_3 AND regfil_4_6 AND regfil_4_5 AND regfil_4_4);
|
| 667 |
|
|
</td></tr><tr><td>
|
| 668 |
|
|
</td></tr><tr><td>
|
| 669 |
|
|
N_PZ_1373 <= (regs(2) AND regs(1) AND NOT regs(0));
|
| 670 |
|
|
</td></tr><tr><td>
|
| 671 |
|
|
</td></tr><tr><td>
|
| 672 |
|
|
N_PZ_1432 <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 673 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND data(3).PIN AND
|
| 674 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 675 |
|
|
<br/> NOT data(7).PIN AND NOT data(5).PIN);
|
| 676 |
|
|
</td></tr><tr><td>
|
| 677 |
|
|
</td></tr><tr><td>
|
| 678 |
|
|
N_PZ_1527 <= ((NOT alusel(2))
|
| 679 |
|
|
<br/> OR (NOT N_PZ_1054 AND NOT aluoprb(4))
|
| 680 |
|
|
<br/> OR (alusel(1) AND alusel(0) AND NOT aluopra(4))
|
| 681 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND NOT N_PZ_1054)
|
| 682 |
|
|
<br/> OR (NOT alusel(1) AND NOT alusel(0) AND N_PZ_1054));
|
| 683 |
|
|
</td></tr><tr><td>
|
| 684 |
|
|
</td></tr><tr><td>
|
| 685 |
|
|
N_PZ_1528 <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 686 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(2).PIN AND data(1).PIN AND
|
| 687 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819);
|
| 688 |
|
|
</td></tr><tr><td>
|
| 689 |
|
|
</td></tr><tr><td>
|
| 690 |
|
|
N_PZ_1533 <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 691 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 692 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 693 |
|
|
<br/> NOT data(7).PIN AND NOT data(5).PIN);
|
| 694 |
|
|
</td></tr><tr><td>
|
| 695 |
|
|
</td></tr><tr><td>
|
| 696 |
|
|
N_PZ_1536 <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 697 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 698 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 699 |
|
|
<br/> NOT data(7).PIN AND data(5).PIN);
|
| 700 |
|
|
</td></tr><tr><td>
|
| 701 |
|
|
</td></tr><tr><td>
|
| 702 |
|
|
N_PZ_1580 <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 703 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(1).PIN AND data(0).PIN AND
|
| 704 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1916);
|
| 705 |
|
|
</td></tr><tr><td>
|
| 706 |
|
|
</td></tr><tr><td>
|
| 707 |
|
|
N_PZ_1725 <= ((regfil_5_1 AND sp(1))
|
| 708 |
|
|
<br/> OR (regfil_5_0 AND regfil_5_1 AND sp(0))
|
| 709 |
|
|
<br/> OR (regfil_5_0 AND sp(0) AND sp(1)));
|
| 710 |
|
|
</td></tr><tr><td>
|
| 711 |
|
|
</td></tr><tr><td>
|
| 712 |
|
|
N_PZ_1799 <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 713 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND
|
| 714 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 715 |
|
|
<br/> NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1 AND
|
| 716 |
|
|
<br/> regfil_0_1 AND regfil_1_3 AND regfil_1_6 AND regfil_1_4 AND
|
| 717 |
|
|
<br/> regfil_0_3 AND regfil_1_5 AND regfil_1_7 AND regfil_0_2 AND
|
| 718 |
|
|
<br/> regfil_0_0 AND regfil_0_4);
|
| 719 |
|
|
</td></tr><tr><td>
|
| 720 |
|
|
</td></tr><tr><td>
|
| 721 |
|
|
N_PZ_1819 <= (NOT data(4).PIN AND data(5).PIN);
|
| 722 |
|
|
</td></tr><tr><td>
|
| 723 |
|
|
</td></tr><tr><td>
|
| 724 |
|
|
N_PZ_1848 <= ((regfil_4_5 AND sp(13))
|
| 725 |
|
|
<br/> OR (NOT regfil_4_5 AND NOT sp(13)));
|
| 726 |
|
|
</td></tr><tr><td>
|
| 727 |
|
|
</td></tr><tr><td>
|
| 728 |
|
|
N_PZ_1849 <= ((regfil_4_7 AND sp(15))
|
| 729 |
|
|
<br/> OR (NOT regfil_4_7 AND NOT sp(15)));
|
| 730 |
|
|
</td></tr><tr><td>
|
| 731 |
|
|
</td></tr><tr><td>
|
| 732 |
|
|
N_PZ_1870 <= ((regfil_4_0 AND Madd__addsub0000__or0006)
|
| 733 |
|
|
<br/> OR (NOT regfil_4_0 AND NOT Madd__addsub0000__or0006));
|
| 734 |
|
|
</td></tr><tr><td>
|
| 735 |
|
|
</td></tr><tr><td>
|
| 736 |
|
|
N_PZ_1887 <= (NOT regfil_7_5 AND NOT regfil_7_6);
|
| 737 |
|
|
</td></tr><tr><td>
|
| 738 |
|
|
</td></tr><tr><td>
|
| 739 |
|
|
N_PZ_1888 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 740 |
|
|
<br/> NOT state(1) AND state(0) AND alures(6))
|
| 741 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 742 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 743 |
|
|
<br/> NOT _cmp_eq0004 AND NOT N_PZ_1373 AND NOT _COND_18(6)));
|
| 744 |
|
|
</td></tr><tr><td>
|
| 745 |
|
|
</td></tr><tr><td>
|
| 746 |
|
|
N_PZ_1890 <= ((regfil_7_1 AND NOT regfil_7_2)
|
| 747 |
|
|
<br/> OR (NOT regfil_7_1 AND regfil_7_2));
|
| 748 |
|
|
</td></tr><tr><td>
|
| 749 |
|
|
</td></tr><tr><td>
|
| 750 |
|
|
N_PZ_1891 <= (NOT state(0) AND data(0).PIN AND data(6).PIN AND
|
| 751 |
|
|
<br/> data(7).PIN AND NOT N_PZ_2236);
|
| 752 |
|
|
</td></tr><tr><td>
|
| 753 |
|
|
</td></tr><tr><td>
|
| 754 |
|
|
N_PZ_1894 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 755 |
|
|
<br/> NOT state(1) AND state(0))
|
| 756 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND
|
| 757 |
|
|
<br/> state(1) AND NOT state(0)));
|
| 758 |
|
|
</td></tr><tr><td>
|
| 759 |
|
|
</td></tr><tr><td>
|
| 760 |
|
|
N_PZ_1905 <= regfil_4_6
|
| 761 |
|
|
<br/> XOR ((NOT regfil_4_5 AND regfil_2_6)
|
| 762 |
|
|
<br/> OR (regfil_2_6 AND _addsub0001(13))
|
| 763 |
|
|
<br/> OR (regfil_4_5 AND NOT regfil_2_6 AND NOT _addsub0001(13)));
|
| 764 |
|
|
</td></tr><tr><td>
|
| 765 |
|
|
</td></tr><tr><td>
|
| 766 |
|
|
N_PZ_1913 <= (regfil_4_1 AND NOT _addsub0000(9));
|
| 767 |
|
|
</td></tr><tr><td>
|
| 768 |
|
|
</td></tr><tr><td>
|
| 769 |
|
|
N_PZ_1916 <= (data(3).PIN AND NOT data(2).PIN AND N_PZ_1819);
|
| 770 |
|
|
</td></tr><tr><td>
|
| 771 |
|
|
</td></tr><tr><td>
|
| 772 |
|
|
N_PZ_1921 <= ((N_PZ_1373)
|
| 773 |
|
|
<br/> OR (regd(2) AND regd(1) AND NOT regd(0)));
|
| 774 |
|
|
</td></tr><tr><td>
|
| 775 |
|
|
</td></tr><tr><td>
|
| 776 |
|
|
N_PZ_1926 <= ((m1/Msub__sub0000__or0001 AND N_PZ_1041)
|
| 777 |
|
|
<br/> OR (NOT m1/Msub__sub0000__or0001 AND NOT N_PZ_1041));
|
| 778 |
|
|
</td></tr><tr><td>
|
| 779 |
|
|
</td></tr><tr><td>
|
| 780 |
|
|
N_PZ_1929 <= ((regfil_4_4 AND sp(12))
|
| 781 |
|
|
<br/> OR (NOT regfil_4_4 AND NOT sp(12)));
|
| 782 |
|
|
</td></tr><tr><td>
|
| 783 |
|
|
</td></tr><tr><td>
|
| 784 |
|
|
N_PZ_1941 <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 785 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 786 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 787 |
|
|
<br/> NOT data(5).PIN);
|
| 788 |
|
|
</td></tr><tr><td>
|
| 789 |
|
|
</td></tr><tr><td>
|
| 790 |
|
|
N_PZ_1943 <= ((N_PZ_1157)
|
| 791 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 792 |
|
|
<br/> NOT state(1) AND state(0) AND data(3).PIN));
|
| 793 |
|
|
</td></tr><tr><td>
|
| 794 |
|
|
</td></tr><tr><td>
|
| 795 |
|
|
N_PZ_1944 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 796 |
|
|
<br/> NOT state(1) AND state(0) AND alures(2))
|
| 797 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 798 |
|
|
<br/> NOT state(1) AND state(0) AND data(2).PIN)
|
| 799 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 800 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 801 |
|
|
<br/> NOT _cmp_eq0004 AND NOT N_PZ_1373 AND NOT _COND_18(2)));
|
| 802 |
|
|
</td></tr><tr><td>
|
| 803 |
|
|
</td></tr><tr><td>
|
| 804 |
|
|
N_PZ_1945 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 805 |
|
|
<br/> NOT state(1) AND state(0) AND NOT alures(2))
|
| 806 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 807 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(2).PIN)
|
| 808 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 809 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 810 |
|
|
<br/> NOT _cmp_eq0004 AND NOT N_PZ_1373 AND _COND_18(2)));
|
| 811 |
|
|
</td></tr><tr><td>
|
| 812 |
|
|
</td></tr><tr><td>
|
| 813 |
|
|
N_PZ_1946 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 814 |
|
|
<br/> NOT state(1) AND state(0) AND NOT alures(1))
|
| 815 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 816 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(1).PIN)
|
| 817 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 818 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 819 |
|
|
<br/> NOT _cmp_eq0004 AND NOT N_PZ_1373 AND _COND_18(1)));
|
| 820 |
|
|
</td></tr><tr><td>
|
| 821 |
|
|
</td></tr><tr><td>
|
| 822 |
|
|
N_PZ_1948 <= ((NOT reset AND state(3) AND NOT state(2) AND state(4) AND
|
| 823 |
|
|
<br/> state(1) AND NOT state(0))
|
| 824 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 825 |
|
|
<br/> state(1) AND state(0)));
|
| 826 |
|
|
</td></tr><tr><td>
|
| 827 |
|
|
</td></tr><tr><td>
|
| 828 |
|
|
N_PZ_1954 <= ((NOT aluopra(1) AND NOT m1/Msub__sub0000__or0001 AND
|
| 829 |
|
|
<br/> NOT aluopra(0))
|
| 830 |
|
|
<br/> OR (alusel(1) AND alusel(0) AND NOT aluopra(1) AND NOT aluopra(0))
|
| 831 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND NOT N_PZ_1076 AND NOT N_PZ_1043)
|
| 832 |
|
|
<br/> OR (NOT alusel(1) AND NOT alusel(0) AND N_PZ_1076 AND
|
| 833 |
|
|
<br/> NOT m1/Madd__addsub0000__or0000)
|
| 834 |
|
|
<br/> OR (NOT alusel(1) AND NOT alusel(0) AND
|
| 835 |
|
|
<br/> NOT m1/Madd__addsub0000__or0000 AND NOT aluopra(0)));
|
| 836 |
|
|
</td></tr><tr><td>
|
| 837 |
|
|
</td></tr><tr><td>
|
| 838 |
|
|
N_PZ_1966 <= ((NOT data(0).PIN AND data(7).PIN AND N_PZ_1916 AND parity)
|
| 839 |
|
|
<br/> OR (NOT data(4).PIN AND NOT data(3).PIN AND NOT data(2).PIN AND
|
| 840 |
|
|
<br/> data(0).PIN AND data(7).PIN AND NOT data(5).PIN)
|
| 841 |
|
|
<br/> OR (NOT data(4).PIN AND NOT data(3).PIN AND NOT data(2).PIN AND
|
| 842 |
|
|
<br/> data(7).PIN AND NOT data(5).PIN AND NOT zero)
|
| 843 |
|
|
<br/> OR (NOT data(3).PIN AND NOT data(2).PIN AND NOT data(0).PIN AND
|
| 844 |
|
|
<br/> data(7).PIN AND N_PZ_1819 AND NOT parity)
|
| 845 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 846 |
|
|
<br/> NOT data(0).PIN AND data(7).PIN AND data(5).PIN AND sign)
|
| 847 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 848 |
|
|
<br/> NOT data(0).PIN AND data(7).PIN AND NOT data(5).PIN AND carry)
|
| 849 |
|
|
<br/> OR (data(4).PIN AND NOT data(3).PIN AND NOT data(2).PIN AND
|
| 850 |
|
|
<br/> NOT data(0).PIN AND data(7).PIN AND data(5).PIN AND NOT sign)
|
| 851 |
|
|
<br/> OR (data(4).PIN AND NOT data(3).PIN AND NOT data(2).PIN AND
|
| 852 |
|
|
<br/> NOT data(0).PIN AND data(7).PIN AND NOT data(5).PIN AND NOT carry)
|
| 853 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 854 |
|
|
<br/> NOT data(0).PIN AND data(7).PIN AND NOT data(5).PIN AND zero));
|
| 855 |
|
|
</td></tr><tr><td>
|
| 856 |
|
|
</td></tr><tr><td>
|
| 857 |
|
|
N_PZ_1981 <= ((regfil_5_5 AND sp(5))
|
| 858 |
|
|
<br/> OR (NOT regfil_5_5 AND NOT sp(5)));
|
| 859 |
|
|
</td></tr><tr><td>
|
| 860 |
|
|
</td></tr><tr><td>
|
| 861 |
|
|
N_PZ_1982 <= ((regfil_5_7 AND sp(7))
|
| 862 |
|
|
<br/> OR (NOT regfil_5_7 AND NOT sp(7)));
|
| 863 |
|
|
</td></tr><tr><td>
|
| 864 |
|
|
</td></tr><tr><td>
|
| 865 |
|
|
N_PZ_1986 <= ((NOT regfil_7_3)
|
| 866 |
|
|
<br/> OR (NOT regfil_7_1 AND NOT regfil_7_2));
|
| 867 |
|
|
</td></tr><tr><td>
|
| 868 |
|
|
</td></tr><tr><td>
|
| 869 |
|
|
N_PZ_1995 <= (regfil_4_5 AND regfil_4_4 AND N_PZ_1143 AND
|
| 870 |
|
|
<br/> Madd__AUX_10_Mxor_Result(12)__xor0000);
|
| 871 |
|
|
</td></tr><tr><td>
|
| 872 |
|
|
</td></tr><tr><td>
|
| 873 |
|
|
N_PZ_1996 <= ((NOT reset AND state(2) AND NOT state(4) AND NOT state(1) AND
|
| 874 |
|
|
<br/> state(0))
|
| 875 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(4) AND state(1) AND
|
| 876 |
|
|
<br/> NOT N_PZ_1066 AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 877 |
|
|
<br/> NOT _cmp_eq0004 AND NOT N_PZ_1373));
|
| 878 |
|
|
</td></tr><tr><td>
|
| 879 |
|
|
</td></tr><tr><td>
|
| 880 |
|
|
N_PZ_1997 <= N_PZ_1141
|
| 881 |
|
|
<br/> XOR ((N_PZ_1260 AND N_PZ_1214 AND NOT N_PZ_2124)
|
| 882 |
|
|
<br/> OR (N_PZ_1260 AND NOT N_PZ_1214 AND N_PZ_2124)
|
| 883 |
|
|
<br/> OR (NOT N_PZ_1260 AND N_PZ_1214 AND N_PZ_2124)
|
| 884 |
|
|
<br/> OR (NOT N_PZ_1260 AND NOT N_PZ_1214 AND NOT N_PZ_2124));
|
| 885 |
|
|
</td></tr><tr><td>
|
| 886 |
|
|
</td></tr><tr><td>
|
| 887 |
|
|
N_PZ_1999 <= (alusel(0) AND NOT m1/Msub__AUX_23__xor0007 AND NOT N_PZ_1926 AND
|
| 888 |
|
|
<br/> N_PZ_2177);
|
| 889 |
|
|
</td></tr><tr><td>
|
| 890 |
|
|
</td></tr><tr><td>
|
| 891 |
|
|
N_PZ_2000 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 892 |
|
|
<br/> NOT state(1) AND state(0) AND NOT alures(5))
|
| 893 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 894 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(5).PIN)
|
| 895 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 896 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 897 |
|
|
<br/> NOT _cmp_eq0004 AND NOT N_PZ_1373 AND _COND_18(5)));
|
| 898 |
|
|
</td></tr><tr><td>
|
| 899 |
|
|
</td></tr><tr><td>
|
| 900 |
|
|
N_PZ_2001 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 901 |
|
|
<br/> NOT state(1) AND state(0) AND NOT alures(7))
|
| 902 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 903 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(7).PIN)
|
| 904 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 905 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 906 |
|
|
<br/> NOT _cmp_eq0004 AND _COND_18(7) AND NOT N_PZ_1373));
|
| 907 |
|
|
</td></tr><tr><td>
|
| 908 |
|
|
</td></tr><tr><td>
|
| 909 |
|
|
N_PZ_2004 <= ((NOT regfil_5_2 AND NOT regfil_1_2)
|
| 910 |
|
|
<br/> OR (NOT regfil_5_2 AND NOT Madd__addsub0000__or0000)
|
| 911 |
|
|
<br/> OR (NOT regfil_1_2 AND NOT Madd__addsub0000__or0000));
|
| 912 |
|
|
</td></tr><tr><td>
|
| 913 |
|
|
</td></tr><tr><td>
|
| 914 |
|
|
N_PZ_2021 <= (pc(7) AND pc(3) AND pc(6) AND pc(4) AND N_PZ_2033 AND
|
| 915 |
|
|
<br/> pc(5));
|
| 916 |
|
|
</td></tr><tr><td>
|
| 917 |
|
|
</td></tr><tr><td>
|
| 918 |
|
|
N_PZ_2031 <= ((NOT regfil_2_5 AND Madd__AUX_9__or0011)
|
| 919 |
|
|
<br/> OR (NOT regfil_2_5 AND NOT _addsub0001(13))
|
| 920 |
|
|
<br/> OR (Madd__AUX_9__or0011 AND NOT _addsub0001(13)));
|
| 921 |
|
|
</td></tr><tr><td>
|
| 922 |
|
|
</td></tr><tr><td>
|
| 923 |
|
|
N_PZ_2033 <= (pc(0) AND pc(1) AND pc(2));
|
| 924 |
|
|
</td></tr><tr><td>
|
| 925 |
|
|
</td></tr><tr><td>
|
| 926 |
|
|
N_PZ_2046 <= (regfil_4_5 AND regfil_4_4 AND NOT Madd__AUX_10__or0010 AND
|
| 927 |
|
|
<br/> Madd__AUX_10_Mxor_Result(12)__xor0000);
|
| 928 |
|
|
</td></tr><tr><td>
|
| 929 |
|
|
</td></tr><tr><td>
|
| 930 |
|
|
N_PZ_2047 <= regfil_5_4
|
| 931 |
|
|
<br/> XOR ((NOT regfil_5_3 AND NOT regfil_3_3)
|
| 932 |
|
|
<br/> OR (NOT regfil_5_3 AND NOT N_PZ_2358)
|
| 933 |
|
|
<br/> OR (NOT regfil_3_3 AND NOT N_PZ_2358));
|
| 934 |
|
|
</td></tr><tr><td>
|
| 935 |
|
|
</td></tr><tr><td>
|
| 936 |
|
|
N_PZ_2048 <= regfil_5_5
|
| 937 |
|
|
<br/> XOR ((NOT regfil_5_4 AND N_PZ_2047)
|
| 938 |
|
|
<br/> OR (NOT regfil_3_4 AND NOT N_PZ_2047));
|
| 939 |
|
|
</td></tr><tr><td>
|
| 940 |
|
|
</td></tr><tr><td>
|
| 941 |
|
|
N_PZ_2049 <= regfil_5_6
|
| 942 |
|
|
<br/> XOR ((NOT regfil_5_5 AND N_PZ_2048)
|
| 943 |
|
|
<br/> OR (NOT regfil_3_5 AND NOT N_PZ_2048));
|
| 944 |
|
|
</td></tr><tr><td>
|
| 945 |
|
|
</td></tr><tr><td>
|
| 946 |
|
|
N_PZ_2050 <= regfil_5_7
|
| 947 |
|
|
<br/> XOR ((NOT regfil_3_6 AND NOT N_PZ_2049)
|
| 948 |
|
|
<br/> OR (NOT regfil_5_6 AND N_PZ_2049));
|
| 949 |
|
|
</td></tr><tr><td>
|
| 950 |
|
|
</td></tr><tr><td>
|
| 951 |
|
|
N_PZ_2052 <= _addsub0001(11)
|
| 952 |
|
|
<br/> XOR ((NOT regfil_2_2 AND NOT _addsub0001(10))
|
| 953 |
|
|
<br/> OR (NOT regfil_2_2 AND Madd__AUX_9__or0008)
|
| 954 |
|
|
<br/> OR (NOT _addsub0001(10) AND Madd__AUX_9__or0008));
|
| 955 |
|
|
</td></tr><tr><td>
|
| 956 |
|
|
</td></tr><tr><td>
|
| 957 |
|
|
N_PZ_2054 <= _addsub0000(14)
|
| 958 |
|
|
<br/> XOR ((NOT regfil_0_5 AND Madd__AUX_8__or0011)
|
| 959 |
|
|
<br/> OR (NOT regfil_0_5 AND NOT _addsub0000(13))
|
| 960 |
|
|
<br/> OR (Madd__AUX_8__or0011 AND NOT _addsub0000(13)));
|
| 961 |
|
|
</td></tr><tr><td>
|
| 962 |
|
|
</td></tr><tr><td>
|
| 963 |
|
|
N_PZ_2055 <= _addsub0001(15)
|
| 964 |
|
|
<br/> XOR ((NOT regfil_2_6 AND NOT N_PZ_1905)
|
| 965 |
|
|
<br/> OR (N_PZ_1905 AND N_PZ_2031));
|
| 966 |
|
|
</td></tr><tr><td>
|
| 967 |
|
|
</td></tr><tr><td>
|
| 968 |
|
|
N_PZ_2056 <= _addsub0000(15)
|
| 969 |
|
|
<br/> XOR ((NOT regfil_0_6 AND NOT N_PZ_2054)
|
| 970 |
|
|
<br/> OR (N_PZ_2054 AND NOT _addsub0000(14)));
|
| 971 |
|
|
</td></tr><tr><td>
|
| 972 |
|
|
</td></tr><tr><td>
|
| 973 |
|
|
N_PZ_2057 <= regfil_4_1
|
| 974 |
|
|
<br/> XOR ((NOT regfil_4_0 AND NOT regfil_2_0)
|
| 975 |
|
|
<br/> OR (NOT regfil_4_0 AND Madd__addsub0001__or0006)
|
| 976 |
|
|
<br/> OR (NOT regfil_2_0 AND Madd__addsub0001__or0006));
|
| 977 |
|
|
</td></tr><tr><td>
|
| 978 |
|
|
</td></tr><tr><td>
|
| 979 |
|
|
N_PZ_2067 <= ((N_PZ_1209 AND NOT N_PZ_1145)
|
| 980 |
|
|
<br/> OR (N_PZ_1209 AND N_PZ_1223 AND pc(12)));
|
| 981 |
|
|
</td></tr><tr><td>
|
| 982 |
|
|
</td></tr><tr><td>
|
| 983 |
|
|
N_PZ_2105 <= ((regfil_4_6 AND NOT sp(14))
|
| 984 |
|
|
<br/> OR (NOT regfil_4_6 AND sp(14)));
|
| 985 |
|
|
</td></tr><tr><td>
|
| 986 |
|
|
</td></tr><tr><td>
|
| 987 |
|
|
N_PZ_2106 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 988 |
|
|
<br/> NOT state(1) AND state(0) AND NOT alures(6))
|
| 989 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 990 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(6).PIN)
|
| 991 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 992 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 993 |
|
|
<br/> NOT _cmp_eq0004 AND NOT N_PZ_1373 AND _COND_18(6)));
|
| 994 |
|
|
</td></tr><tr><td>
|
| 995 |
|
|
</td></tr><tr><td>
|
| 996 |
|
|
N_PZ_2108 <= ((NOT sp(5) AND N_PZ_1981)
|
| 997 |
|
|
<br/> OR (NOT sp(4) AND NOT N_PZ_2168 AND NOT N_PZ_1981)
|
| 998 |
|
|
<br/> OR (N_PZ_2168 AND NOT N_PZ_1981 AND N_PZ_2111));
|
| 999 |
|
|
</td></tr><tr><td>
|
| 1000 |
|
|
</td></tr><tr><td>
|
| 1001 |
|
|
N_PZ_2111 <= ((NOT regfil_5_3 AND NOT sp(3))
|
| 1002 |
|
|
<br/> OR (NOT regfil_5_3 AND NOT Madd__AUX_11__or0001)
|
| 1003 |
|
|
<br/> OR (NOT sp(3) AND NOT Madd__AUX_11__or0001));
|
| 1004 |
|
|
</td></tr><tr><td>
|
| 1005 |
|
|
</td></tr><tr><td>
|
| 1006 |
|
|
N_PZ_2114 <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 1007 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 1008 |
|
|
<br/> data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND
|
| 1009 |
|
|
<br/> N_PZ_1819);
|
| 1010 |
|
|
</td></tr><tr><td>
|
| 1011 |
|
|
</td></tr><tr><td>
|
| 1012 |
|
|
N_PZ_2124 <= ((N_PZ_1213 AND
|
| 1013 |
|
|
<br/> NOT m1/Mxor__xor0001_Mxor__xor0000__xor0001)
|
| 1014 |
|
|
<br/> OR (NOT N_PZ_1213 AND
|
| 1015 |
|
|
<br/> m1/Mxor__xor0001_Mxor__xor0000__xor0001));
|
| 1016 |
|
|
</td></tr><tr><td>
|
| 1017 |
|
|
</td></tr><tr><td>
|
| 1018 |
|
|
N_PZ_2147 <= ((NOT regfil_5_6 AND NOT regfil_1_6)
|
| 1019 |
|
|
<br/> OR (NOT regfil_5_6 AND Madd__addsub0000__or0004)
|
| 1020 |
|
|
<br/> OR (NOT regfil_1_6 AND Madd__addsub0000__or0004));
|
| 1021 |
|
|
</td></tr><tr><td>
|
| 1022 |
|
|
</td></tr><tr><td>
|
| 1023 |
|
|
N_PZ_2148 <= ((NOT regfil_5_4 AND NOT regfil_1_4)
|
| 1024 |
|
|
<br/> OR (NOT regfil_5_4 AND Madd__addsub0000__or0002)
|
| 1025 |
|
|
<br/> OR (NOT regfil_1_4 AND Madd__addsub0000__or0002));
|
| 1026 |
|
|
</td></tr><tr><td>
|
| 1027 |
|
|
</td></tr><tr><td>
|
| 1028 |
|
|
N_PZ_2155 <= ((NOT N_PZ_2114)
|
| 1029 |
|
|
<br/> OR (data(4).PIN AND NOT data(2).PIN AND data(1).PIN AND
|
| 1030 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT data(5).PIN));
|
| 1031 |
|
|
</td></tr><tr><td>
|
| 1032 |
|
|
</td></tr><tr><td>
|
| 1033 |
|
|
N_PZ_2168 <= ((regfil_5_4 AND NOT sp(4))
|
| 1034 |
|
|
<br/> OR (NOT regfil_5_4 AND sp(4)));
|
| 1035 |
|
|
</td></tr><tr><td>
|
| 1036 |
|
|
</td></tr><tr><td>
|
| 1037 |
|
|
N_PZ_2169 <= ((regfil_5_6 AND NOT sp(6))
|
| 1038 |
|
|
<br/> OR (NOT regfil_5_6 AND sp(6)));
|
| 1039 |
|
|
</td></tr><tr><td>
|
| 1040 |
|
|
</td></tr><tr><td>
|
| 1041 |
|
|
N_PZ_2177 <= (NOT N_PZ_1076 AND NOT N_PZ_1043 AND alucin);
|
| 1042 |
|
|
</td></tr><tr><td>
|
| 1043 |
|
|
</td></tr><tr><td>
|
| 1044 |
|
|
N_PZ_2180 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 1045 |
|
|
<br/> NOT state(1) AND state(0) AND NOT alures(3))
|
| 1046 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 1047 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(3).PIN)
|
| 1048 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 1049 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 1050 |
|
|
<br/> NOT _cmp_eq0004 AND NOT N_PZ_1373 AND _COND_18(3)));
|
| 1051 |
|
|
</td></tr><tr><td>
|
| 1052 |
|
|
</td></tr><tr><td>
|
| 1053 |
|
|
N_PZ_2181 <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 1054 |
|
|
<br/> NOT state(1) AND state(0) AND NOT alures(4))
|
| 1055 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 1056 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(4).PIN)
|
| 1057 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 1058 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 1059 |
|
|
<br/> NOT _cmp_eq0004 AND NOT N_PZ_1373 AND _COND_18(4)));
|
| 1060 |
|
|
</td></tr><tr><td>
|
| 1061 |
|
|
</td></tr><tr><td>
|
| 1062 |
|
|
N_PZ_2186 <= ((NOT reset AND state(2) AND NOT state(4) AND NOT state(1) AND
|
| 1063 |
|
|
<br/> state(0) AND regd(2) AND regd(1) AND NOT regd(0))
|
| 1064 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 1065 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 1066 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND NOT regd(0) AND NOT N_PZ_1373));
|
| 1067 |
|
|
</td></tr><tr><td>
|
| 1068 |
|
|
</td></tr><tr><td>
|
| 1069 |
|
|
N_PZ_2196 <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 1070 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 1071 |
|
|
<br/> NOT _cmp_eq0004 AND NOT N_PZ_1373 AND N_PZ_1129);
|
| 1072 |
|
|
</td></tr><tr><td>
|
| 1073 |
|
|
</td></tr><tr><td>
|
| 1074 |
|
|
N_PZ_2226 <= ((regfil_2_7 AND NOT N_PZ_2055)
|
| 1075 |
|
|
<br/> OR (N_PZ_2055 AND _addsub0001(15)));
|
| 1076 |
|
|
</td></tr><tr><td>
|
| 1077 |
|
|
</td></tr><tr><td>
|
| 1078 |
|
|
N_PZ_2232 <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 1079 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(2).PIN AND data(1).PIN AND
|
| 1080 |
|
|
<br/> NOT data(0).PIN AND data(6).PIN AND data(7).PIN)
|
| 1081 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 1082 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(3).PIN AND
|
| 1083 |
|
|
<br/> NOT data(2).PIN AND data(1).PIN AND data(6).PIN AND data(7).PIN AND
|
| 1084 |
|
|
<br/> NOT data(5).PIN));
|
| 1085 |
|
|
</td></tr><tr><td>
|
| 1086 |
|
|
</td></tr><tr><td>
|
| 1087 |
|
|
N_PZ_2236 <= ((NOT data(2).PIN AND data(1).PIN)
|
| 1088 |
|
|
<br/> OR (NOT data(1).PIN AND NOT N_PZ_1916));
|
| 1089 |
|
|
</td></tr><tr><td>
|
| 1090 |
|
|
</td></tr><tr><td>
|
| 1091 |
|
|
N_PZ_2358 <= ((regfil_3_2 AND regfil_5_2)
|
| 1092 |
|
|
<br/> OR (regfil_3_2 AND Madd__addsub0001__or0000)
|
| 1093 |
|
|
<br/> OR (regfil_5_2 AND Madd__addsub0001__or0000));
|
| 1094 |
|
|
</td></tr><tr><td>
|
| 1095 |
|
|
</td></tr><tr><td>
|
| 1096 |
|
|
N_PZ_2362 <= ((regfil_4_0 AND sp(8))
|
| 1097 |
|
|
<br/> OR (regfil_4_0 AND NOT sp(8) AND NOT Madd__AUX_11__or0006)
|
| 1098 |
|
|
<br/> OR (NOT regfil_4_0 AND sp(8) AND NOT Madd__AUX_11__or0006));
|
| 1099 |
|
|
</td></tr><tr><td>
|
| 1100 |
|
|
</td></tr><tr><td>
|
| 1101 |
|
|
N_PZ_2405 <= (addrhold(7) AND addrhold(3) AND addrhold(0) AND
|
| 1102 |
|
|
<br/> addrhold(9) AND addrhold(8) AND addrhold(1) AND addrhold(2) AND
|
| 1103 |
|
|
<br/> addrhold(10) AND addrhold(4) AND addrhold(11) AND addrhold(5) AND
|
| 1104 |
|
|
<br/> addrhold(6) AND N_PZ_1948);
|
| 1105 |
|
|
</td></tr><tr><td>
|
| 1106 |
|
|
</td></tr><tr><td>
|
| 1107 |
|
|
_COND_18(0) <= ((N_PZ_1373 AND NOT regfil_6_0)
|
| 1108 |
|
|
<br/> OR (regs(2) AND regs(1) AND NOT regfil_7_0 AND regs(0))
|
| 1109 |
|
|
<br/> OR (regs(2) AND NOT regs(1) AND NOT regfil_5_0 AND regs(0))
|
| 1110 |
|
|
<br/> OR (regs(2) AND NOT regs(1) AND NOT regfil_4_0 AND NOT regs(0))
|
| 1111 |
|
|
<br/> OR (NOT regs(2) AND regs(1) AND NOT regfil_3_0 AND regs(0))
|
| 1112 |
|
|
<br/> OR (NOT regs(2) AND regs(1) AND NOT regs(0) AND NOT regfil_2_0)
|
| 1113 |
|
|
<br/> OR (NOT regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_1_0)
|
| 1114 |
|
|
<br/> OR (NOT regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_0_0));
|
| 1115 |
|
|
</td></tr><tr><td>
|
| 1116 |
|
|
</td></tr><tr><td>
|
| 1117 |
|
|
_COND_18(1) <= ((N_PZ_1373 AND NOT regfil_6_1)
|
| 1118 |
|
|
<br/> OR (regs(2) AND regs(1) AND NOT regfil_7_1 AND regs(0))
|
| 1119 |
|
|
<br/> OR (regs(2) AND NOT regs(1) AND NOT regfil_4_1 AND NOT regs(0))
|
| 1120 |
|
|
<br/> OR (regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_5_1)
|
| 1121 |
|
|
<br/> OR (NOT regs(2) AND regs(1) AND regs(0) AND NOT regfil_3_1)
|
| 1122 |
|
|
<br/> OR (NOT regs(2) AND regs(1) AND NOT regs(0) AND NOT regfil_2_1)
|
| 1123 |
|
|
<br/> OR (NOT regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_1_1)
|
| 1124 |
|
|
<br/> OR (NOT regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_0_1));
|
| 1125 |
|
|
</td></tr><tr><td>
|
| 1126 |
|
|
</td></tr><tr><td>
|
| 1127 |
|
|
_COND_18(2) <= ((N_PZ_1373 AND NOT regfil_6_2)
|
| 1128 |
|
|
<br/> OR (regs(2) AND regs(1) AND NOT regfil_7_2 AND regs(0))
|
| 1129 |
|
|
<br/> OR (regs(2) AND NOT regs(1) AND NOT regfil_4_2 AND NOT regs(0))
|
| 1130 |
|
|
<br/> OR (regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_5_2)
|
| 1131 |
|
|
<br/> OR (NOT regs(2) AND regs(1) AND regs(0) AND NOT regfil_3_2)
|
| 1132 |
|
|
<br/> OR (NOT regs(2) AND regs(1) AND NOT regs(0) AND NOT regfil_2_2)
|
| 1133 |
|
|
<br/> OR (NOT regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_1_2)
|
| 1134 |
|
|
<br/> OR (NOT regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_0_2));
|
| 1135 |
|
|
</td></tr><tr><td>
|
| 1136 |
|
|
</td></tr><tr><td>
|
| 1137 |
|
|
_COND_18(3) <= ((N_PZ_1373 AND NOT regfil_6_3)
|
| 1138 |
|
|
<br/> OR (regs(2) AND regs(1) AND NOT regfil_7_3 AND regs(0))
|
| 1139 |
|
|
<br/> OR (regs(2) AND NOT regs(1) AND NOT regfil_5_3 AND regs(0))
|
| 1140 |
|
|
<br/> OR (regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_4_3)
|
| 1141 |
|
|
<br/> OR (NOT regs(2) AND regs(1) AND regs(0) AND NOT regfil_3_3)
|
| 1142 |
|
|
<br/> OR (NOT regs(2) AND regs(1) AND NOT regs(0) AND NOT regfil_2_3)
|
| 1143 |
|
|
<br/> OR (NOT regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_1_3)
|
| 1144 |
|
|
<br/> OR (NOT regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_0_3));
|
| 1145 |
|
|
</td></tr><tr><td>
|
| 1146 |
|
|
</td></tr><tr><td>
|
| 1147 |
|
|
_COND_18(4) <= ((N_PZ_1373 AND NOT regfil_6_4)
|
| 1148 |
|
|
<br/> OR (regs(2) AND regs(1) AND regs(0) AND NOT regfil_7_4)
|
| 1149 |
|
|
<br/> OR (regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_5_4)
|
| 1150 |
|
|
<br/> OR (regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_4_4)
|
| 1151 |
|
|
<br/> OR (NOT regs(2) AND regs(1) AND regs(0) AND NOT regfil_3_4)
|
| 1152 |
|
|
<br/> OR (NOT regs(2) AND regs(1) AND NOT regs(0) AND NOT regfil_2_4)
|
| 1153 |
|
|
<br/> OR (NOT regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_1_4)
|
| 1154 |
|
|
<br/> OR (NOT regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_0_4));
|
| 1155 |
|
|
</td></tr><tr><td>
|
| 1156 |
|
|
</td></tr><tr><td>
|
| 1157 |
|
|
_COND_18(5) <= ((N_PZ_1373 AND NOT regfil_6_5)
|
| 1158 |
|
|
<br/> OR (regs(2) AND regs(1) AND regs(0) AND NOT regfil_7_5)
|
| 1159 |
|
|
<br/> OR (regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_5_5)
|
| 1160 |
|
|
<br/> OR (regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_4_5)
|
| 1161 |
|
|
<br/> OR (NOT regs(2) AND regs(1) AND regs(0) AND NOT regfil_3_5)
|
| 1162 |
|
|
<br/> OR (NOT regs(2) AND regs(1) AND NOT regs(0) AND NOT regfil_2_5)
|
| 1163 |
|
|
<br/> OR (NOT regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_1_5)
|
| 1164 |
|
|
<br/> OR (NOT regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_0_5));
|
| 1165 |
|
|
</td></tr><tr><td>
|
| 1166 |
|
|
</td></tr><tr><td>
|
| 1167 |
|
|
_COND_18(6) <= ((N_PZ_1373 AND NOT regfil_6_6)
|
| 1168 |
|
|
<br/> OR (regs(2) AND regs(1) AND regs(0) AND NOT regfil_7_6)
|
| 1169 |
|
|
<br/> OR (regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_5_6)
|
| 1170 |
|
|
<br/> OR (regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_4_6)
|
| 1171 |
|
|
<br/> OR (NOT regs(2) AND regs(1) AND regs(0) AND NOT regfil_3_6)
|
| 1172 |
|
|
<br/> OR (NOT regs(2) AND regs(1) AND NOT regs(0) AND NOT regfil_2_6)
|
| 1173 |
|
|
<br/> OR (NOT regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_1_6)
|
| 1174 |
|
|
<br/> OR (NOT regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_0_6));
|
| 1175 |
|
|
</td></tr><tr><td>
|
| 1176 |
|
|
</td></tr><tr><td>
|
| 1177 |
|
|
_COND_18(7) <= ((N_PZ_1373 AND NOT regfil_6_7)
|
| 1178 |
|
|
<br/> OR (regs(2) AND regs(1) AND regs(0) AND NOT regfil_7_7)
|
| 1179 |
|
|
<br/> OR (regs(2) AND NOT regs(1) AND NOT regfil_5_7 AND regs(0))
|
| 1180 |
|
|
<br/> OR (regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_4_7)
|
| 1181 |
|
|
<br/> OR (NOT regs(2) AND regs(1) AND regs(0) AND NOT regfil_3_7)
|
| 1182 |
|
|
<br/> OR (NOT regs(2) AND regs(1) AND NOT regs(0) AND NOT regfil_2_7)
|
| 1183 |
|
|
<br/> OR (NOT regs(2) AND NOT regs(1) AND regs(0) AND NOT regfil_1_7)
|
| 1184 |
|
|
<br/> OR (NOT regs(2) AND NOT regs(1) AND NOT regs(0) AND NOT regfil_0_7));
|
| 1185 |
|
|
</td></tr><tr><td>
|
| 1186 |
|
|
</td></tr><tr><td>
|
| 1187 |
|
|
_addsub0000(9) <= regfil_4_1
|
| 1188 |
|
|
<br/> XOR (regfil_4_0 AND NOT Madd__addsub0000__or0006);
|
| 1189 |
|
|
</td></tr><tr><td>
|
| 1190 |
|
|
</td></tr><tr><td>
|
| 1191 |
|
|
_addsub0000(11) <= regfil_4_3
|
| 1192 |
|
|
<br/> XOR (regfil_4_2 AND N_PZ_1913);
|
| 1193 |
|
|
</td></tr><tr><td>
|
| 1194 |
|
|
</td></tr><tr><td>
|
| 1195 |
|
|
_addsub0000(12) <= regfil_4_4
|
| 1196 |
|
|
<br/> XOR (regfil_4_3 AND NOT _addsub0000(11));
|
| 1197 |
|
|
</td></tr><tr><td>
|
| 1198 |
|
|
</td></tr><tr><td>
|
| 1199 |
|
|
_addsub0000(13) <= regfil_4_5
|
| 1200 |
|
|
<br/> XOR (regfil_4_4 AND NOT _addsub0000(12));
|
| 1201 |
|
|
</td></tr><tr><td>
|
| 1202 |
|
|
</td></tr><tr><td>
|
| 1203 |
|
|
_addsub0000(14) <= regfil_4_6
|
| 1204 |
|
|
<br/> XOR (regfil_4_5 AND NOT _addsub0000(13));
|
| 1205 |
|
|
</td></tr><tr><td>
|
| 1206 |
|
|
</td></tr><tr><td>
|
| 1207 |
|
|
_addsub0000(15) <= regfil_4_7
|
| 1208 |
|
|
<br/> XOR (regfil_4_6 AND NOT _addsub0000(14));
|
| 1209 |
|
|
</td></tr><tr><td>
|
| 1210 |
|
|
</td></tr><tr><td>
|
| 1211 |
|
|
_addsub0001(10) <= regfil_4_2
|
| 1212 |
|
|
<br/> XOR (regfil_4_1 AND regfil_4_0 AND
|
| 1213 |
|
|
<br/> NOT Madd__addsub0001__or0006);
|
| 1214 |
|
|
</td></tr><tr><td>
|
| 1215 |
|
|
</td></tr><tr><td>
|
| 1216 |
|
|
_addsub0001(11) <= regfil_4_3
|
| 1217 |
|
|
<br/> XOR (regfil_4_2 AND NOT _addsub0001(10));
|
| 1218 |
|
|
</td></tr><tr><td>
|
| 1219 |
|
|
</td></tr><tr><td>
|
| 1220 |
|
|
_addsub0001(12) <= regfil_4_4
|
| 1221 |
|
|
<br/> XOR (regfil_4_3 AND NOT _addsub0001(11));
|
| 1222 |
|
|
</td></tr><tr><td>
|
| 1223 |
|
|
</td></tr><tr><td>
|
| 1224 |
|
|
_addsub0001(13) <= regfil_4_5
|
| 1225 |
|
|
<br/> XOR (regfil_4_4 AND NOT _addsub0001(12));
|
| 1226 |
|
|
</td></tr><tr><td>
|
| 1227 |
|
|
</td></tr><tr><td>
|
| 1228 |
|
|
_addsub0001(15) <= regfil_4_7
|
| 1229 |
|
|
<br/> XOR (regfil_4_6 AND regfil_4_5 AND NOT _addsub0001(13));
|
| 1230 |
|
|
</td></tr><tr><td>
|
| 1231 |
|
|
</td></tr><tr><td>
|
| 1232 |
|
|
_cmp_eq0004 <= (data(4).PIN AND NOT data(3).PIN AND data(2).PIN AND
|
| 1233 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND data(6).PIN AND NOT data(7).PIN AND
|
| 1234 |
|
|
<br/> data(5).PIN);
|
| 1235 |
|
|
</td></tr><tr><td>
|
| 1236 |
|
|
</td></tr><tr><td>
|
| 1237 |
|
|
_mux000762 <= ((NOT state(3) AND NOT data(4).PIN AND data(0).PIN AND
|
| 1238 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND NOT N_PZ_1819 AND NOT N_PZ_2236 AND
|
| 1239 |
|
|
<br/> regfil_7_7)
|
| 1240 |
|
|
<br/> OR (NOT state(3) AND NOT data(3).PIN AND data(0).PIN AND
|
| 1241 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND NOT N_PZ_1819 AND
|
| 1242 |
|
|
<br/> NOT N_PZ_2236)
|
| 1243 |
|
|
<br/> OR (NOT state(3) AND NOT data(3).PIN AND data(0).PIN AND
|
| 1244 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND NOT N_PZ_1819 AND NOT N_PZ_2236 AND
|
| 1245 |
|
|
<br/> regfil_7_7)
|
| 1246 |
|
|
<br/> OR (NOT state(3) AND NOT data(3).PIN AND data(0).PIN AND
|
| 1247 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND NOT N_PZ_2236 AND regfil_7_7 AND
|
| 1248 |
|
|
<br/> NOT N_PZ_1887)
|
| 1249 |
|
|
<br/> OR (NOT state(3) AND NOT data(1).PIN AND data(0).PIN AND
|
| 1250 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND NOT N_PZ_2236 AND regfil_4_7 AND
|
| 1251 |
|
|
<br/> NOT regfil_4_6)
|
| 1252 |
|
|
<br/> OR (NOT state(3) AND NOT data(1).PIN AND data(0).PIN AND
|
| 1253 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND NOT N_PZ_2236 AND regfil_4_7 AND
|
| 1254 |
|
|
<br/> NOT N_PZ_2046)
|
| 1255 |
|
|
<br/> OR (NOT state(3) AND data(0).PIN AND NOT data(6).PIN AND
|
| 1256 |
|
|
<br/> NOT data(7).PIN AND data(5).PIN AND NOT carry AND NOT N_PZ_1819 AND NOT N_PZ_2236)
|
| 1257 |
|
|
<br/> OR (NOT state(3) AND data(4).PIN AND data(3).PIN AND
|
| 1258 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT data(5).PIN AND
|
| 1259 |
|
|
<br/> NOT N_PZ_2236 AND carryhold)
|
| 1260 |
|
|
<br/> OR (NOT state(3) AND NOT data(1).PIN AND data(0).PIN AND
|
| 1261 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND NOT N_PZ_2236 AND NOT regfil_4_7 AND
|
| 1262 |
|
|
<br/> regfil_4_6 AND N_PZ_2046)
|
| 1263 |
|
|
<br/> OR (NOT state(3) AND data(4).PIN AND data(3).PIN AND
|
| 1264 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1265 |
|
|
<br/> NOT data(7).PIN AND NOT data(5).PIN AND NOT regfil_4_7 AND N_PZ_2226)
|
| 1266 |
|
|
<br/> OR (NOT state(3) AND data(4).PIN AND data(3).PIN AND
|
| 1267 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1268 |
|
|
<br/> NOT data(7).PIN AND NOT data(5).PIN AND Madd__addsub0001__or0006 AND
|
| 1269 |
|
|
<br/> N_PZ_2226)
|
| 1270 |
|
|
<br/> OR (NOT state(3) AND data(4).PIN AND data(3).PIN AND
|
| 1271 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1272 |
|
|
<br/> NOT data(7).PIN AND NOT data(5).PIN AND NOT N_PZ_1347 AND N_PZ_2226)
|
| 1273 |
|
|
<br/> OR (NOT state(3) AND data(3).PIN AND NOT data(2).PIN AND
|
| 1274 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1275 |
|
|
<br/> data(5).PIN AND N_PZ_2236 AND N_PZ_1849 AND sp(15))
|
| 1276 |
|
|
<br/> OR (NOT state(3) AND NOT data(4).PIN AND data(3).PIN AND
|
| 1277 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1278 |
|
|
<br/> NOT data(7).PIN AND N_PZ_2236 AND NOT regfil_4_7 AND regfil_0_7 AND NOT N_PZ_2056)
|
| 1279 |
|
|
<br/> OR (NOT state(3) AND NOT data(4).PIN AND data(3).PIN AND
|
| 1280 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1281 |
|
|
<br/> NOT data(7).PIN AND N_PZ_2236 AND NOT regfil_4_7 AND N_PZ_2056 AND
|
| 1282 |
|
|
<br/> _addsub0000(15))
|
| 1283 |
|
|
<br/> OR (NOT state(3) AND NOT data(4).PIN AND data(3).PIN AND
|
| 1284 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1285 |
|
|
<br/> NOT data(7).PIN AND N_PZ_2236 AND regfil_0_7 AND
|
| 1286 |
|
|
<br/> Madd__addsub0000__or0006 AND NOT N_PZ_2056)
|
| 1287 |
|
|
<br/> OR (NOT state(3) AND NOT data(4).PIN AND data(3).PIN AND
|
| 1288 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1289 |
|
|
<br/> NOT data(7).PIN AND N_PZ_2236 AND Madd__addsub0000__or0006 AND N_PZ_2056 AND
|
| 1290 |
|
|
<br/> _addsub0000(15))
|
| 1291 |
|
|
<br/> OR (NOT state(3) AND NOT data(4).PIN AND data(3).PIN AND
|
| 1292 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1293 |
|
|
<br/> NOT data(7).PIN AND regfil_4_7 AND regfil_0_7 AND NOT N_PZ_2056 AND NOT N_PZ_1347)
|
| 1294 |
|
|
<br/> OR (NOT state(3) AND NOT data(4).PIN AND data(3).PIN AND
|
| 1295 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1296 |
|
|
<br/> NOT data(7).PIN AND regfil_4_7 AND N_PZ_2056 AND _addsub0000(15) AND
|
| 1297 |
|
|
<br/> NOT N_PZ_1347)
|
| 1298 |
|
|
<br/> OR (NOT state(3) AND data(3).PIN AND NOT data(2).PIN AND
|
| 1299 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1300 |
|
|
<br/> data(5).PIN AND N_PZ_2236 AND NOT Madd__AUX_11__or0012 AND N_PZ_2105 AND
|
| 1301 |
|
|
<br/> NOT N_PZ_1849)
|
| 1302 |
|
|
<br/> OR (NOT state(3) AND data(3).PIN AND NOT data(2).PIN AND
|
| 1303 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1304 |
|
|
<br/> data(5).PIN AND N_PZ_2236 AND NOT N_PZ_2105 AND sp(14) AND NOT N_PZ_1849)
|
| 1305 |
|
|
<br/> OR (NOT state(3) AND data(4).PIN AND data(3).PIN AND
|
| 1306 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1307 |
|
|
<br/> NOT data(7).PIN AND NOT data(5).PIN AND regfil_4_7 AND
|
| 1308 |
|
|
<br/> NOT Madd__addsub0001__or0006 AND N_PZ_1347 AND NOT N_PZ_2226)
|
| 1309 |
|
|
<br/> OR (NOT state(3) AND NOT data(4).PIN AND data(3).PIN AND
|
| 1310 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1311 |
|
|
<br/> NOT data(7).PIN AND N_PZ_2236 AND regfil_4_7 AND NOT regfil_0_7 AND
|
| 1312 |
|
|
<br/> NOT Madd__addsub0000__or0006 AND NOT N_PZ_2056 AND N_PZ_1347)
|
| 1313 |
|
|
<br/> OR (NOT state(3) AND NOT data(4).PIN AND data(3).PIN AND
|
| 1314 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1315 |
|
|
<br/> NOT data(7).PIN AND N_PZ_2236 AND regfil_4_7 AND
|
| 1316 |
|
|
<br/> NOT Madd__addsub0000__or0006 AND N_PZ_2056 AND NOT _addsub0000(15) AND N_PZ_1347));
|
| 1317 |
|
|
</td></tr><tr><td>
|
| 1318 |
|
|
</td></tr><tr><td>
|
| 1319 |
|
|
_mux0009(2)72 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1320 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1916 AND regfil_5_1)
|
| 1321 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1322 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_5_0 AND
|
| 1323 |
|
|
<br/> regfil_5_2)
|
| 1324 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1325 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_5_1 AND
|
| 1326 |
|
|
<br/> regfil_5_2)
|
| 1327 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1328 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_5_0 AND
|
| 1329 |
|
|
<br/> regfil_5_1 AND NOT regfil_5_2)
|
| 1330 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1331 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1332 |
|
|
<br/> data(5).PIN AND regfil_5_2 AND sp(2) AND N_PZ_1725)
|
| 1333 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1334 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1335 |
|
|
<br/> data(5).PIN AND regfil_5_2 AND NOT sp(2) AND NOT N_PZ_1725)
|
| 1336 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1337 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1338 |
|
|
<br/> data(5).PIN AND NOT regfil_5_2 AND sp(2) AND NOT N_PZ_1725)
|
| 1339 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1340 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1341 |
|
|
<br/> data(5).PIN AND NOT regfil_5_2 AND NOT sp(2) AND N_PZ_1725)
|
| 1342 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1343 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1344 |
|
|
<br/> NOT data(5).PIN AND regfil_3_2 AND regfil_5_2 AND
|
| 1345 |
|
|
<br/> Madd__addsub0001__or0000)
|
| 1346 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1347 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1348 |
|
|
<br/> NOT data(5).PIN AND regfil_3_2 AND NOT regfil_5_2 AND
|
| 1349 |
|
|
<br/> NOT Madd__addsub0001__or0000)
|
| 1350 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1351 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1352 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_3_2 AND regfil_5_2 AND
|
| 1353 |
|
|
<br/> NOT Madd__addsub0001__or0000)
|
| 1354 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1355 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1356 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_3_2 AND NOT regfil_5_2 AND
|
| 1357 |
|
|
<br/> Madd__addsub0001__or0000)
|
| 1358 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1359 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1360 |
|
|
<br/> NOT data(5).PIN AND regfil_5_2 AND regfil_1_2 AND
|
| 1361 |
|
|
<br/> Madd__addsub0000__or0000)
|
| 1362 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1363 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1364 |
|
|
<br/> NOT data(5).PIN AND regfil_5_2 AND NOT regfil_1_2 AND
|
| 1365 |
|
|
<br/> NOT Madd__addsub0000__or0000)
|
| 1366 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1367 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1368 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_5_2 AND regfil_1_2 AND
|
| 1369 |
|
|
<br/> NOT Madd__addsub0000__or0000)
|
| 1370 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1371 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1372 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_5_2 AND NOT regfil_1_2 AND
|
| 1373 |
|
|
<br/> Madd__addsub0000__or0000));
|
| 1374 |
|
|
</td></tr><tr><td>
|
| 1375 |
|
|
</td></tr><tr><td>
|
| 1376 |
|
|
_mux0009(4)72 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1377 |
|
|
<br/> NOT data(7).PIN AND NOT N_PZ_2236 AND regfil_5_3)
|
| 1378 |
|
|
<br/> OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1379 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1819 AND N_PZ_2236 AND regfil_5_4 AND NOT N_PZ_1122)
|
| 1380 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1381 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1382 |
|
|
<br/> NOT data(5).PIN AND regfil_3_4 AND N_PZ_2047)
|
| 1383 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1384 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1385 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_3_4 AND NOT N_PZ_2047)
|
| 1386 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1387 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1388 |
|
|
<br/> N_PZ_2236 AND N_PZ_2168 AND N_PZ_2111)
|
| 1389 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1390 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1391 |
|
|
<br/> N_PZ_2236 AND NOT N_PZ_2168 AND NOT N_PZ_2111)
|
| 1392 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1393 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1394 |
|
|
<br/> N_PZ_2236 AND regfil_5_4 AND regfil_1_4 AND
|
| 1395 |
|
|
<br/> NOT Madd__addsub0000__or0002)
|
| 1396 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1397 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1398 |
|
|
<br/> N_PZ_2236 AND regfil_5_4 AND NOT regfil_1_4 AND
|
| 1399 |
|
|
<br/> Madd__addsub0000__or0002)
|
| 1400 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1401 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1402 |
|
|
<br/> N_PZ_2236 AND NOT regfil_5_4 AND regfil_1_4 AND
|
| 1403 |
|
|
<br/> Madd__addsub0000__or0002)
|
| 1404 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1405 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1406 |
|
|
<br/> N_PZ_2236 AND NOT regfil_5_4 AND NOT regfil_1_4 AND
|
| 1407 |
|
|
<br/> NOT Madd__addsub0000__or0002)
|
| 1408 |
|
|
<br/> OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1409 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1819 AND N_PZ_2236 AND regfil_5_3 AND regfil_5_0 AND
|
| 1410 |
|
|
<br/> regfil_5_1 AND regfil_5_2 AND NOT N_PZ_1122));
|
| 1411 |
|
|
</td></tr><tr><td>
|
| 1412 |
|
|
</td></tr><tr><td>
|
| 1413 |
|
|
_mux0009(5)72 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1414 |
|
|
<br/> NOT data(7).PIN AND NOT N_PZ_2236 AND regfil_5_4)
|
| 1415 |
|
|
<br/> OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1416 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1819 AND N_PZ_2236 AND regfil_5_5 AND NOT N_PZ_1122)
|
| 1417 |
|
|
<br/> OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1418 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1819 AND N_PZ_2236 AND NOT regfil_5_5 AND N_PZ_1122)
|
| 1419 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1420 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1421 |
|
|
<br/> NOT data(5).PIN AND regfil_3_5 AND N_PZ_2048)
|
| 1422 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1423 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1424 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_3_5 AND NOT N_PZ_2048)
|
| 1425 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1426 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1427 |
|
|
<br/> data(5).PIN AND sp(4) AND NOT N_PZ_2168 AND N_PZ_1981)
|
| 1428 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1429 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1430 |
|
|
<br/> data(5).PIN AND NOT sp(4) AND NOT N_PZ_2168 AND NOT N_PZ_1981)
|
| 1431 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1432 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1433 |
|
|
<br/> data(5).PIN AND N_PZ_2168 AND N_PZ_1981 AND NOT N_PZ_2111)
|
| 1434 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1435 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1436 |
|
|
<br/> data(5).PIN AND N_PZ_2168 AND NOT N_PZ_1981 AND N_PZ_2111)
|
| 1437 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1438 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1439 |
|
|
<br/> NOT data(5).PIN AND regfil_5_5 AND regfil_1_5 AND NOT N_PZ_2148)
|
| 1440 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1441 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1442 |
|
|
<br/> NOT data(5).PIN AND regfil_5_5 AND NOT regfil_1_5 AND N_PZ_2148)
|
| 1443 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1444 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1445 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_5_5 AND regfil_1_5 AND N_PZ_2148)
|
| 1446 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1447 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1448 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_5_5 AND NOT regfil_1_5 AND NOT N_PZ_2148));
|
| 1449 |
|
|
</td></tr><tr><td>
|
| 1450 |
|
|
</td></tr><tr><td>
|
| 1451 |
|
|
_mux0009(6)72 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1452 |
|
|
<br/> NOT data(7).PIN AND NOT N_PZ_2236 AND regfil_5_5)
|
| 1453 |
|
|
<br/> OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1454 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1819 AND N_PZ_2236 AND regfil_5_6 AND NOT N_PZ_1143)
|
| 1455 |
|
|
<br/> OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1456 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1819 AND N_PZ_2236 AND regfil_5_5 AND NOT N_PZ_1143 AND
|
| 1457 |
|
|
<br/> N_PZ_1122)
|
| 1458 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1459 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1460 |
|
|
<br/> NOT data(5).PIN AND regfil_3_6 AND N_PZ_2049)
|
| 1461 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1462 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1463 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_3_6 AND NOT N_PZ_2049)
|
| 1464 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1465 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1466 |
|
|
<br/> N_PZ_2236 AND N_PZ_2108 AND N_PZ_2169)
|
| 1467 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1468 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1469 |
|
|
<br/> N_PZ_2236 AND NOT N_PZ_2108 AND NOT N_PZ_2169)
|
| 1470 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1471 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1472 |
|
|
<br/> N_PZ_2236 AND regfil_5_6 AND regfil_1_6 AND
|
| 1473 |
|
|
<br/> NOT Madd__addsub0000__or0004)
|
| 1474 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1475 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1476 |
|
|
<br/> N_PZ_2236 AND regfil_5_6 AND NOT regfil_1_6 AND
|
| 1477 |
|
|
<br/> Madd__addsub0000__or0004)
|
| 1478 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1479 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1480 |
|
|
<br/> N_PZ_2236 AND NOT regfil_5_6 AND regfil_1_6 AND
|
| 1481 |
|
|
<br/> Madd__addsub0000__or0004)
|
| 1482 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1483 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1484 |
|
|
<br/> N_PZ_2236 AND NOT regfil_5_6 AND NOT regfil_1_6 AND
|
| 1485 |
|
|
<br/> NOT Madd__addsub0000__or0004));
|
| 1486 |
|
|
</td></tr><tr><td>
|
| 1487 |
|
|
</td></tr><tr><td>
|
| 1488 |
|
|
_mux0009(7)72 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1489 |
|
|
<br/> NOT data(7).PIN AND NOT N_PZ_2236 AND regfil_5_6)
|
| 1490 |
|
|
<br/> OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1491 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1819 AND regfil_5_7 AND N_PZ_2236 AND NOT N_PZ_1143)
|
| 1492 |
|
|
<br/> OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1493 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_5_7 AND N_PZ_2236 AND N_PZ_1143)
|
| 1494 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1495 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1496 |
|
|
<br/> NOT data(5).PIN AND regfil_3_7 AND N_PZ_2050)
|
| 1497 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1498 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1499 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_3_7 AND NOT N_PZ_2050)
|
| 1500 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1501 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1502 |
|
|
<br/> data(5).PIN AND N_PZ_2108 AND N_PZ_2169 AND NOT N_PZ_1982)
|
| 1503 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1504 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1505 |
|
|
<br/> data(5).PIN AND NOT N_PZ_2108 AND N_PZ_2169 AND N_PZ_1982)
|
| 1506 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1507 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1508 |
|
|
<br/> data(5).PIN AND NOT N_PZ_2169 AND sp(6) AND N_PZ_1982)
|
| 1509 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1510 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1511 |
|
|
<br/> data(5).PIN AND NOT N_PZ_2169 AND NOT sp(6) AND NOT N_PZ_1982)
|
| 1512 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1513 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1514 |
|
|
<br/> NOT data(5).PIN AND regfil_5_7 AND regfil_1_7 AND NOT N_PZ_2147)
|
| 1515 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1516 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1517 |
|
|
<br/> NOT data(5).PIN AND regfil_5_7 AND NOT regfil_1_7 AND N_PZ_2147)
|
| 1518 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1519 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1520 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_5_7 AND regfil_1_7 AND N_PZ_2147)
|
| 1521 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1522 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1523 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_5_7 AND NOT regfil_1_7 AND NOT N_PZ_2147));
|
| 1524 |
|
|
</td></tr><tr><td>
|
| 1525 |
|
|
</td></tr><tr><td>
|
| 1526 |
|
|
_mux0010(8)71 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1527 |
|
|
<br/> NOT data(7).PIN AND regfil_5_7 AND NOT N_PZ_2236)
|
| 1528 |
|
|
<br/> OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1529 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_5_7 AND N_PZ_2236 AND regfil_4_0)
|
| 1530 |
|
|
<br/> OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1531 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1819 AND N_PZ_2236 AND regfil_4_0 AND NOT N_PZ_1143)
|
| 1532 |
|
|
<br/> OR (data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1533 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1819 AND regfil_5_7 AND N_PZ_2236 AND NOT regfil_4_0 AND
|
| 1534 |
|
|
<br/> N_PZ_1143)
|
| 1535 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1536 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1537 |
|
|
<br/> N_PZ_2236 AND regfil_0_0 AND NOT N_PZ_1870)
|
| 1538 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1539 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1540 |
|
|
<br/> N_PZ_2236 AND NOT regfil_0_0 AND N_PZ_1870)
|
| 1541 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1542 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1543 |
|
|
<br/> NOT data(5).PIN AND regfil_4_0 AND regfil_2_0 AND
|
| 1544 |
|
|
<br/> NOT Madd__addsub0001__or0006)
|
| 1545 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1546 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1547 |
|
|
<br/> NOT data(5).PIN AND regfil_4_0 AND NOT regfil_2_0 AND
|
| 1548 |
|
|
<br/> Madd__addsub0001__or0006)
|
| 1549 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1550 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1551 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_4_0 AND regfil_2_0 AND
|
| 1552 |
|
|
<br/> Madd__addsub0001__or0006)
|
| 1553 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1554 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1555 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_4_0 AND NOT regfil_2_0 AND
|
| 1556 |
|
|
<br/> NOT Madd__addsub0001__or0006)
|
| 1557 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1558 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1559 |
|
|
<br/> N_PZ_2236 AND regfil_4_0 AND sp(8) AND NOT Madd__AUX_11__or0006)
|
| 1560 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1561 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1562 |
|
|
<br/> N_PZ_2236 AND regfil_4_0 AND NOT sp(8) AND Madd__AUX_11__or0006)
|
| 1563 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1564 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1565 |
|
|
<br/> N_PZ_2236 AND NOT regfil_4_0 AND sp(8) AND Madd__AUX_11__or0006)
|
| 1566 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1567 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1568 |
|
|
<br/> N_PZ_2236 AND NOT regfil_4_0 AND NOT sp(8) AND NOT Madd__AUX_11__or0006));
|
| 1569 |
|
|
</td></tr><tr><td>
|
| 1570 |
|
|
</td></tr><tr><td>
|
| 1571 |
|
|
_mux0010(9)71 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1572 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1916 AND regfil_4_0)
|
| 1573 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1574 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_5_7 AND
|
| 1575 |
|
|
<br/> regfil_4_1)
|
| 1576 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1577 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_1 AND
|
| 1578 |
|
|
<br/> NOT regfil_4_0)
|
| 1579 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1580 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_1 AND
|
| 1581 |
|
|
<br/> NOT N_PZ_1143)
|
| 1582 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1583 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1584 |
|
|
<br/> NOT data(5).PIN AND regfil_2_1 AND N_PZ_2057)
|
| 1585 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1586 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1587 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_2_1 AND NOT N_PZ_2057)
|
| 1588 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1589 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1590 |
|
|
<br/> NOT N_PZ_1916 AND regfil_0_1 AND NOT Madd__AUX_8__or0008)
|
| 1591 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1592 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1593 |
|
|
<br/> NOT N_PZ_1916 AND _addsub0000(9) AND NOT Madd__AUX_8__or0008)
|
| 1594 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1595 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1596 |
|
|
<br/> NOT N_PZ_1916 AND regfil_4_1 AND Madd__AUX_11__or0008)
|
| 1597 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1598 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1599 |
|
|
<br/> NOT N_PZ_1916 AND sp(9) AND Madd__AUX_11__or0008)
|
| 1600 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1601 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1602 |
|
|
<br/> NOT N_PZ_1916 AND Madd__AUX_11__or0008 AND N_PZ_2362)
|
| 1603 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1604 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_5_7 AND
|
| 1605 |
|
|
<br/> NOT regfil_4_1 AND regfil_4_0 AND N_PZ_1143)
|
| 1606 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1607 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1608 |
|
|
<br/> NOT N_PZ_1916 AND regfil_0_0 AND NOT Madd__AUX_8__or0008 AND N_PZ_1870)
|
| 1609 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1610 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1611 |
|
|
<br/> NOT N_PZ_1916 AND regfil_4_1 AND sp(9) AND N_PZ_2362)
|
| 1612 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1613 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1614 |
|
|
<br/> NOT N_PZ_1916 AND regfil_0_1 AND regfil_0_0 AND _addsub0000(9) AND
|
| 1615 |
|
|
<br/> N_PZ_1870));
|
| 1616 |
|
|
</td></tr><tr><td>
|
| 1617 |
|
|
</td></tr><tr><td>
|
| 1618 |
|
|
_mux0010(10)71 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1619 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1916 AND regfil_4_1)
|
| 1620 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1621 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_5_7 AND
|
| 1622 |
|
|
<br/> regfil_4_2)
|
| 1623 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1624 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_2 AND
|
| 1625 |
|
|
<br/> NOT regfil_4_1)
|
| 1626 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1627 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_2 AND
|
| 1628 |
|
|
<br/> NOT regfil_4_0)
|
| 1629 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1630 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_2 AND
|
| 1631 |
|
|
<br/> NOT N_PZ_1143)
|
| 1632 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1633 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1634 |
|
|
<br/> data(5).PIN AND regfil_4_2 AND Madd__AUX_11__or0009)
|
| 1635 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1636 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1637 |
|
|
<br/> data(5).PIN AND sp(10) AND Madd__AUX_11__or0009)
|
| 1638 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1639 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1640 |
|
|
<br/> data(5).PIN AND Madd__AUX_11__or0009 AND NOT Madd__AUX_11__or0008)
|
| 1641 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1642 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1643 |
|
|
<br/> NOT data(5).PIN AND regfil_0_2 AND Madd__AUX_8__or0009)
|
| 1644 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1645 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1646 |
|
|
<br/> NOT data(5).PIN AND Madd__AUX_8__or0009 AND Madd__AUX_8__or0008)
|
| 1647 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1648 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1649 |
|
|
<br/> NOT regfil_4_2 AND N_PZ_1913 AND Madd__AUX_8__or0009)
|
| 1650 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1651 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1652 |
|
|
<br/> data(5).PIN AND regfil_4_2 AND sp(10) AND NOT Madd__AUX_11__or0008)
|
| 1653 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1654 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1655 |
|
|
<br/> NOT data(5).PIN AND regfil_2_2 AND _addsub0001(10) AND
|
| 1656 |
|
|
<br/> NOT Madd__AUX_9__or0008)
|
| 1657 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1658 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1659 |
|
|
<br/> NOT data(5).PIN AND regfil_2_2 AND NOT _addsub0001(10) AND
|
| 1660 |
|
|
<br/> Madd__AUX_9__or0008)
|
| 1661 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1662 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1663 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_2_2 AND _addsub0001(10) AND
|
| 1664 |
|
|
<br/> Madd__AUX_9__or0008)
|
| 1665 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1666 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1667 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_2_2 AND NOT _addsub0001(10) AND
|
| 1668 |
|
|
<br/> NOT Madd__AUX_9__or0008)
|
| 1669 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1670 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1671 |
|
|
<br/> NOT data(5).PIN AND regfil_4_2 AND NOT N_PZ_1913 AND Madd__AUX_8__or0009)
|
| 1672 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1673 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1674 |
|
|
<br/> NOT regfil_4_2 AND regfil_0_2 AND N_PZ_1913 AND Madd__AUX_8__or0008)
|
| 1675 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1676 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_5_7 AND
|
| 1677 |
|
|
<br/> NOT regfil_4_2 AND regfil_4_1 AND regfil_4_0 AND N_PZ_1143)
|
| 1678 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1679 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1680 |
|
|
<br/> NOT data(5).PIN AND regfil_4_2 AND regfil_0_2 AND NOT N_PZ_1913 AND
|
| 1681 |
|
|
<br/> Madd__AUX_8__or0008));
|
| 1682 |
|
|
</td></tr><tr><td>
|
| 1683 |
|
|
</td></tr><tr><td>
|
| 1684 |
|
|
_mux0010(11)71 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1685 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1916 AND regfil_4_2)
|
| 1686 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1687 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_3 AND
|
| 1688 |
|
|
<br/> NOT N_PZ_1143)
|
| 1689 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1690 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_3 AND
|
| 1691 |
|
|
<br/> NOT Madd__AUX_10_Mxor_Result(12)__xor0000)
|
| 1692 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1693 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1694 |
|
|
<br/> NOT data(5).PIN AND regfil_2_3 AND N_PZ_2052)
|
| 1695 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1696 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1697 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_2_3 AND NOT N_PZ_2052)
|
| 1698 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1699 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1700 |
|
|
<br/> NOT N_PZ_1916 AND regfil_0_3 AND _addsub0000(11) AND
|
| 1701 |
|
|
<br/> NOT Madd__AUX_8__or0009)
|
| 1702 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1703 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1704 |
|
|
<br/> NOT N_PZ_1916 AND regfil_0_3 AND NOT _addsub0000(11) AND
|
| 1705 |
|
|
<br/> Madd__AUX_8__or0009)
|
| 1706 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1707 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1708 |
|
|
<br/> NOT N_PZ_1916 AND NOT regfil_0_3 AND _addsub0000(11) AND
|
| 1709 |
|
|
<br/> Madd__AUX_8__or0009)
|
| 1710 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1711 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1712 |
|
|
<br/> NOT N_PZ_1916 AND NOT regfil_0_3 AND NOT _addsub0000(11) AND
|
| 1713 |
|
|
<br/> NOT Madd__AUX_8__or0009)
|
| 1714 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1715 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1716 |
|
|
<br/> NOT N_PZ_1916 AND regfil_4_3 AND sp(11) AND NOT Madd__AUX_11__or0009)
|
| 1717 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1718 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1719 |
|
|
<br/> NOT N_PZ_1916 AND regfil_4_3 AND NOT sp(11) AND Madd__AUX_11__or0009)
|
| 1720 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1721 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1722 |
|
|
<br/> NOT N_PZ_1916 AND NOT regfil_4_3 AND sp(11) AND Madd__AUX_11__or0009)
|
| 1723 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1724 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1725 |
|
|
<br/> NOT N_PZ_1916 AND NOT regfil_4_3 AND NOT sp(11) AND NOT Madd__AUX_11__or0009)
|
| 1726 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1727 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_5_7 AND
|
| 1728 |
|
|
<br/> regfil_4_2 AND regfil_4_1 AND regfil_4_0 AND NOT regfil_4_3 AND
|
| 1729 |
|
|
<br/> N_PZ_1143));
|
| 1730 |
|
|
</td></tr><tr><td>
|
| 1731 |
|
|
</td></tr><tr><td>
|
| 1732 |
|
|
_mux0010(12)71 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1733 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1916 AND Madd__AUX_10__or0010 AND
|
| 1734 |
|
|
<br/> Madd__AUX_10_Mxor_Result(12)__xor0000)
|
| 1735 |
|
|
<br/> OR (NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1736 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1916 AND NOT Madd__AUX_10__or0010 AND
|
| 1737 |
|
|
<br/> NOT Madd__AUX_10_Mxor_Result(12)__xor0000)
|
| 1738 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1739 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_4 AND
|
| 1740 |
|
|
<br/> NOT N_PZ_1143)
|
| 1741 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1742 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_4 AND
|
| 1743 |
|
|
<br/> NOT Madd__AUX_10_Mxor_Result(12)__xor0000)
|
| 1744 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1745 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_4_4 AND
|
| 1746 |
|
|
<br/> N_PZ_1143 AND Madd__AUX_10_Mxor_Result(12)__xor0000)
|
| 1747 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1748 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1749 |
|
|
<br/> NOT data(5).PIN AND regfil_2_4 AND Madd__AUX_9__or0011)
|
| 1750 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1751 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1752 |
|
|
<br/> NOT data(5).PIN AND _addsub0001(12) AND Madd__AUX_9__or0011)
|
| 1753 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1754 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1755 |
|
|
<br/> NOT N_PZ_1819 AND regfil_0_4 AND Madd__AUX_8__or0011)
|
| 1756 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1757 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1758 |
|
|
<br/> NOT N_PZ_1819 AND _addsub0000(12) AND Madd__AUX_8__or0011)
|
| 1759 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1760 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1761 |
|
|
<br/> NOT N_PZ_1819 AND NOT Madd__AUX_8__or0010 AND Madd__AUX_8__or0011)
|
| 1762 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1763 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1764 |
|
|
<br/> NOT N_PZ_1819 AND Madd__AUX_11__or0010 AND NOT N_PZ_1929)
|
| 1765 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1766 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1767 |
|
|
<br/> NOT N_PZ_1819 AND NOT Madd__AUX_11__or0010 AND N_PZ_1929)
|
| 1768 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1769 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1770 |
|
|
<br/> NOT data(5).PIN AND regfil_2_3 AND NOT N_PZ_2052 AND Madd__AUX_9__or0011)
|
| 1771 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1772 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1773 |
|
|
<br/> NOT data(5).PIN AND _addsub0001(11) AND N_PZ_2052 AND
|
| 1774 |
|
|
<br/> Madd__AUX_9__or0011)
|
| 1775 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1776 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1777 |
|
|
<br/> NOT N_PZ_1819 AND regfil_0_4 AND _addsub0000(12) AND
|
| 1778 |
|
|
<br/> NOT Madd__AUX_8__or0010)
|
| 1779 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1780 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1781 |
|
|
<br/> NOT data(5).PIN AND regfil_2_3 AND regfil_2_4 AND _addsub0001(12) AND
|
| 1782 |
|
|
<br/> NOT N_PZ_2052)
|
| 1783 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1784 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1785 |
|
|
<br/> NOT data(5).PIN AND regfil_2_4 AND _addsub0001(11) AND _addsub0001(12) AND
|
| 1786 |
|
|
<br/> N_PZ_2052));
|
| 1787 |
|
|
</td></tr><tr><td>
|
| 1788 |
|
|
</td></tr><tr><td>
|
| 1789 |
|
|
_mux0010(13)71 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1790 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1916 AND regfil_4_4 AND Madd__AUX_10__or0010)
|
| 1791 |
|
|
<br/> OR (NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1792 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1916 AND regfil_4_4 AND
|
| 1793 |
|
|
<br/> NOT Madd__AUX_10_Mxor_Result(12)__xor0000)
|
| 1794 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1795 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_5 AND
|
| 1796 |
|
|
<br/> NOT N_PZ_1995)
|
| 1797 |
|
|
<br/> OR (NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1798 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1916 AND NOT regfil_4_4 AND NOT Madd__AUX_10__or0010 AND
|
| 1799 |
|
|
<br/> Madd__AUX_10_Mxor_Result(12)__xor0000)
|
| 1800 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1801 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_4_5 AND
|
| 1802 |
|
|
<br/> regfil_4_4 AND N_PZ_1143 AND Madd__AUX_10_Mxor_Result(12)__xor0000)
|
| 1803 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1804 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1805 |
|
|
<br/> NOT data(5).PIN AND regfil_2_5 AND Madd__AUX_9__or0011 AND
|
| 1806 |
|
|
<br/> NOT _addsub0001(13))
|
| 1807 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1808 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1809 |
|
|
<br/> NOT data(5).PIN AND regfil_2_5 AND NOT Madd__AUX_9__or0011 AND
|
| 1810 |
|
|
<br/> _addsub0001(13))
|
| 1811 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1812 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1813 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_2_5 AND Madd__AUX_9__or0011 AND
|
| 1814 |
|
|
<br/> _addsub0001(13))
|
| 1815 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1816 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1817 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_2_5 AND NOT Madd__AUX_9__or0011 AND
|
| 1818 |
|
|
<br/> NOT _addsub0001(13))
|
| 1819 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1820 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1821 |
|
|
<br/> NOT N_PZ_1916 AND regfil_0_5 AND Madd__AUX_8__or0011 AND
|
| 1822 |
|
|
<br/> NOT _addsub0000(13))
|
| 1823 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1824 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1825 |
|
|
<br/> NOT N_PZ_1916 AND regfil_0_5 AND NOT Madd__AUX_8__or0011 AND
|
| 1826 |
|
|
<br/> _addsub0000(13))
|
| 1827 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1828 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1829 |
|
|
<br/> NOT N_PZ_1916 AND NOT regfil_0_5 AND Madd__AUX_8__or0011 AND
|
| 1830 |
|
|
<br/> _addsub0000(13))
|
| 1831 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1832 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1833 |
|
|
<br/> NOT N_PZ_1916 AND NOT regfil_0_5 AND NOT Madd__AUX_8__or0011 AND
|
| 1834 |
|
|
<br/> NOT _addsub0000(13))
|
| 1835 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1836 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1837 |
|
|
<br/> NOT N_PZ_1916 AND Madd__AUX_11__or0010 AND NOT N_PZ_1929 AND NOT N_PZ_1848)
|
| 1838 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1839 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1840 |
|
|
<br/> NOT N_PZ_1916 AND NOT Madd__AUX_11__or0010 AND NOT N_PZ_1929 AND N_PZ_1848)
|
| 1841 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1842 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1843 |
|
|
<br/> NOT N_PZ_1916 AND N_PZ_1929 AND sp(12) AND N_PZ_1848)
|
| 1844 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1845 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1846 |
|
|
<br/> NOT N_PZ_1916 AND N_PZ_1929 AND NOT sp(12) AND NOT N_PZ_1848));
|
| 1847 |
|
|
</td></tr><tr><td>
|
| 1848 |
|
|
</td></tr><tr><td>
|
| 1849 |
|
|
_mux0010(14)71 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1850 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1916 AND regfil_4_5 AND NOT N_PZ_2046)
|
| 1851 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1852 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_6 AND
|
| 1853 |
|
|
<br/> NOT N_PZ_1995)
|
| 1854 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1855 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_4_6 AND
|
| 1856 |
|
|
<br/> N_PZ_1995)
|
| 1857 |
|
|
<br/> OR (NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1858 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1916 AND regfil_4_4 AND NOT Madd__AUX_10__or0010 AND
|
| 1859 |
|
|
<br/> Madd__AUX_10_Mxor_Result(12)__xor0000 AND NOT N_PZ_2046)
|
| 1860 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1861 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1862 |
|
|
<br/> NOT data(5).PIN AND N_PZ_1905 AND N_PZ_2031)
|
| 1863 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1864 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1865 |
|
|
<br/> NOT N_PZ_1916 AND regfil_0_6 AND N_PZ_2054)
|
| 1866 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1867 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1868 |
|
|
<br/> NOT N_PZ_1916 AND NOT regfil_0_6 AND NOT N_PZ_2054)
|
| 1869 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1870 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1871 |
|
|
<br/> NOT N_PZ_1916 AND Madd__AUX_11__or0012 AND N_PZ_2105)
|
| 1872 |
|
|
<br/> OR (data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND
|
| 1873 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND data(5).PIN AND
|
| 1874 |
|
|
<br/> NOT N_PZ_1916 AND NOT Madd__AUX_11__or0012 AND NOT N_PZ_2105)
|
| 1875 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1876 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1877 |
|
|
<br/> NOT data(5).PIN AND regfil_2_5 AND NOT Madd__AUX_9__or0011 AND NOT N_PZ_1905)
|
| 1878 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1879 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1880 |
|
|
<br/> NOT data(5).PIN AND regfil_4_6 AND regfil_2_6 AND _addsub0001(13) AND
|
| 1881 |
|
|
<br/> NOT N_PZ_2031)
|
| 1882 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1883 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1884 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_4_6 AND NOT regfil_2_6 AND _addsub0001(13) AND
|
| 1885 |
|
|
<br/> NOT N_PZ_2031));
|
| 1886 |
|
|
</td></tr><tr><td>
|
| 1887 |
|
|
</td></tr><tr><td>
|
| 1888 |
|
|
_mux0010(15)71 <= ((NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1889 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1916 AND regfil_4_6 AND NOT N_PZ_2046)
|
| 1890 |
|
|
<br/> OR (NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 1891 |
|
|
<br/> NOT data(7).PIN AND N_PZ_1916 AND NOT regfil_4_6 AND N_PZ_2046)
|
| 1892 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1893 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_7 AND
|
| 1894 |
|
|
<br/> NOT regfil_4_6)
|
| 1895 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1896 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND regfil_4_7 AND
|
| 1897 |
|
|
<br/> NOT N_PZ_1995)
|
| 1898 |
|
|
<br/> OR (NOT data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 1899 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND NOT regfil_4_7 AND
|
| 1900 |
|
|
<br/> regfil_4_6 AND N_PZ_1995)
|
| 1901 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1902 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1903 |
|
|
<br/> NOT data(5).PIN AND regfil_2_7 AND N_PZ_2055)
|
| 1904 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1905 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1906 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_2_7 AND NOT N_PZ_2055)
|
| 1907 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1908 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1909 |
|
|
<br/> NOT data(5).PIN AND regfil_0_7 AND N_PZ_2056)
|
| 1910 |
|
|
<br/> OR (NOT data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1911 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1912 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_0_7 AND NOT N_PZ_2056)
|
| 1913 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1914 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1915 |
|
|
<br/> data(5).PIN AND Madd__AUX_11__or0012 AND N_PZ_2105 AND NOT N_PZ_1849)
|
| 1916 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1917 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1918 |
|
|
<br/> data(5).PIN AND NOT Madd__AUX_11__or0012 AND N_PZ_2105 AND N_PZ_1849)
|
| 1919 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1920 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1921 |
|
|
<br/> data(5).PIN AND NOT N_PZ_2105 AND sp(14) AND N_PZ_1849)
|
| 1922 |
|
|
<br/> OR (data(4).PIN AND data(3).PIN AND NOT data(2).PIN AND
|
| 1923 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 1924 |
|
|
<br/> data(5).PIN AND NOT N_PZ_2105 AND NOT sp(14) AND NOT N_PZ_1849));
|
| 1925 |
|
|
</td></tr><tr><td>
|
| 1926 |
|
|
</td></tr><tr><td>
|
| 1927 |
|
|
_mux0014(13)8 <= regfil_2_5
|
| 1928 |
|
|
<br/> XOR ((NOT data(4).PIN AND regfil_2_5)
|
| 1929 |
|
|
<br/> OR (data(2).PIN AND regfil_2_5)
|
| 1930 |
|
|
<br/> OR (NOT data(1).PIN AND regfil_2_5)
|
| 1931 |
|
|
<br/> OR (NOT data(0).PIN AND regfil_2_5)
|
| 1932 |
|
|
<br/> OR (data(6).PIN AND regfil_2_5)
|
| 1933 |
|
|
<br/> OR (data(7).PIN AND regfil_2_5)
|
| 1934 |
|
|
<br/> OR (data(5).PIN AND regfil_2_5)
|
| 1935 |
|
|
<br/> OR (data(4).PIN AND NOT data(2).PIN AND data(1).PIN AND
|
| 1936 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT data(5).PIN AND
|
| 1937 |
|
|
<br/> regfil_3_0 AND regfil_2_0 AND regfil_3_1 AND regfil_2_1 AND
|
| 1938 |
|
|
<br/> regfil_3_2 AND regfil_2_2 AND regfil_3_3 AND regfil_3_4 AND
|
| 1939 |
|
|
<br/> regfil_3_5 AND regfil_2_3 AND regfil_3_6 AND regfil_2_4 AND
|
| 1940 |
|
|
<br/> regfil_3_7));
|
| 1941 |
|
|
</td></tr><tr><td>
|
| 1942 |
|
|
</td></tr><tr><td>
|
| 1943 |
|
|
_mux003739 <= ((NOT state(3) AND state(2) AND NOT state(4) AND NOT state(1) AND
|
| 1944 |
|
|
<br/> state(0) AND NOT regd(2) AND addrhold(15))
|
| 1945 |
|
|
<br/> OR (NOT state(3) AND state(2) AND NOT state(4) AND NOT state(1) AND
|
| 1946 |
|
|
<br/> state(0) AND NOT regd(1) AND addrhold(15))
|
| 1947 |
|
|
<br/> OR (NOT state(3) AND state(2) AND NOT state(4) AND NOT state(1) AND
|
| 1948 |
|
|
<br/> state(0) AND regd(0) AND addrhold(15))
|
| 1949 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 1950 |
|
|
<br/> NOT state(0) AND data(7).PIN AND addrhold(15))
|
| 1951 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 1952 |
|
|
<br/> NOT state(0) AND NOT data(1).PIN AND NOT data(6).PIN AND addrhold(15))
|
| 1953 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 1954 |
|
|
<br/> NOT state(0) AND data(0).PIN AND NOT data(6).PIN AND addrhold(15))
|
| 1955 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 1956 |
|
|
<br/> NOT state(0) AND data(6).PIN AND _cmp_eq0004 AND addrhold(15))
|
| 1957 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 1958 |
|
|
<br/> NOT state(0) AND data(6).PIN AND NOT N_PZ_1921 AND addrhold(15))
|
| 1959 |
|
|
<br/> OR (NOT state(3) AND state(2) AND NOT state(4) AND NOT state(1) AND
|
| 1960 |
|
|
<br/> state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND addrhold2(15))
|
| 1961 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 1962 |
|
|
<br/> NOT state(0) AND NOT data(2).PIN AND NOT data(6).PIN AND data(5).PIN AND
|
| 1963 |
|
|
<br/> addrhold(15))
|
| 1964 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 1965 |
|
|
<br/> NOT state(0) AND data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND
|
| 1966 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND pc(15)));
|
| 1967 |
|
|
</td></tr><tr><td>
|
| 1968 |
|
|
</td></tr><tr><td>
|
| 1969 |
|
|
_xor0000 <= (NOT regfil_5_7 AND NOT regfil_5_3 AND NOT regfil_5_0 AND
|
| 1970 |
|
|
<br/> NOT regfil_5_1 AND NOT regfil_5_2 AND NOT regfil_5_4 AND NOT regfil_5_5 AND
|
| 1971 |
|
|
<br/> NOT regfil_5_6);
|
| 1972 |
|
|
</td></tr><tr><td>
|
| 1973 |
|
|
</td></tr><tr><td>
|
| 1974 |
|
|
_xor0068 <= (NOT regfil_1_0 AND NOT regfil_1_2 AND NOT regfil_1_1 AND
|
| 1975 |
|
|
<br/> NOT regfil_1_3 AND NOT regfil_1_6 AND NOT regfil_1_4 AND NOT regfil_1_5 AND
|
| 1976 |
|
|
<br/> NOT regfil_1_7);
|
| 1977 |
|
|
</td></tr><tr><td>
|
| 1978 |
|
|
FDCPE_addrhold20: FDCPE port map (addrhold2(0),regfil_5_0,clock,'0','0',addrhold2_CE(0));
|
| 1979 |
|
|
<br/> addrhold2_CE(0) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 1980 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 1981 |
|
|
<br/> data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND
|
| 1982 |
|
|
<br/> NOT data(7).PIN AND data(5).PIN);
|
| 1983 |
|
|
</td></tr><tr><td>
|
| 1984 |
|
|
FDCPE_addrhold21: FDCPE port map (addrhold2(1),regfil_5_1,clock,'0','0',addrhold2_CE(1));
|
| 1985 |
|
|
<br/> addrhold2_CE(1) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 1986 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 1987 |
|
|
<br/> data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND
|
| 1988 |
|
|
<br/> NOT data(7).PIN AND data(5).PIN);
|
| 1989 |
|
|
</td></tr><tr><td>
|
| 1990 |
|
|
FDCPE_addrhold22: FDCPE port map (addrhold2(2),regfil_5_2,clock,'0','0',addrhold2_CE(2));
|
| 1991 |
|
|
<br/> addrhold2_CE(2) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 1992 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 1993 |
|
|
<br/> data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND
|
| 1994 |
|
|
<br/> NOT data(7).PIN AND data(5).PIN);
|
| 1995 |
|
|
</td></tr><tr><td>
|
| 1996 |
|
|
FDCPE_addrhold23: FDCPE port map (addrhold2(3),regfil_5_3,clock,'0','0',addrhold2_CE(3));
|
| 1997 |
|
|
<br/> addrhold2_CE(3) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 1998 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 1999 |
|
|
<br/> data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND
|
| 2000 |
|
|
<br/> NOT data(7).PIN AND data(5).PIN);
|
| 2001 |
|
|
</td></tr><tr><td>
|
| 2002 |
|
|
FDCPE_addrhold24: FDCPE port map (addrhold2(4),regfil_5_4,clock,'0','0',addrhold2_CE(4));
|
| 2003 |
|
|
<br/> addrhold2_CE(4) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2004 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 2005 |
|
|
<br/> data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND
|
| 2006 |
|
|
<br/> NOT data(7).PIN AND data(5).PIN);
|
| 2007 |
|
|
</td></tr><tr><td>
|
| 2008 |
|
|
FDCPE_addrhold25: FDCPE port map (addrhold2(5),regfil_5_5,clock,'0','0',addrhold2_CE(5));
|
| 2009 |
|
|
<br/> addrhold2_CE(5) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2010 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 2011 |
|
|
<br/> data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND
|
| 2012 |
|
|
<br/> NOT data(7).PIN AND data(5).PIN);
|
| 2013 |
|
|
</td></tr><tr><td>
|
| 2014 |
|
|
FDCPE_addrhold26: FDCPE port map (addrhold2(6),regfil_5_6,clock,'0','0',addrhold2_CE(6));
|
| 2015 |
|
|
<br/> addrhold2_CE(6) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2016 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 2017 |
|
|
<br/> data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND
|
| 2018 |
|
|
<br/> NOT data(7).PIN AND data(5).PIN);
|
| 2019 |
|
|
</td></tr><tr><td>
|
| 2020 |
|
|
FDCPE_addrhold27: FDCPE port map (addrhold2(7),regfil_5_7,clock,'0','0',addrhold2_CE(7));
|
| 2021 |
|
|
<br/> addrhold2_CE(7) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2022 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 2023 |
|
|
<br/> data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND
|
| 2024 |
|
|
<br/> NOT data(7).PIN AND data(5).PIN);
|
| 2025 |
|
|
</td></tr><tr><td>
|
| 2026 |
|
|
FDCPE_addrhold28: FDCPE port map (addrhold2(8),regfil_4_0,clock,'0','0',addrhold2_CE(8));
|
| 2027 |
|
|
<br/> addrhold2_CE(8) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2028 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 2029 |
|
|
<br/> data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND
|
| 2030 |
|
|
<br/> NOT data(7).PIN AND data(5).PIN);
|
| 2031 |
|
|
</td></tr><tr><td>
|
| 2032 |
|
|
FDCPE_addrhold29: FDCPE port map (addrhold2(9),regfil_4_1,clock,'0','0',addrhold2_CE(9));
|
| 2033 |
|
|
<br/> addrhold2_CE(9) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2034 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 2035 |
|
|
<br/> data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND
|
| 2036 |
|
|
<br/> NOT data(7).PIN AND data(5).PIN);
|
| 2037 |
|
|
</td></tr><tr><td>
|
| 2038 |
|
|
FDCPE_addrhold210: FDCPE port map (addrhold2(10),regfil_4_2,clock,'0','0',addrhold2_CE(10));
|
| 2039 |
|
|
<br/> addrhold2_CE(10) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2040 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 2041 |
|
|
<br/> data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND
|
| 2042 |
|
|
<br/> NOT data(7).PIN AND data(5).PIN);
|
| 2043 |
|
|
</td></tr><tr><td>
|
| 2044 |
|
|
FDCPE_addrhold211: FDCPE port map (addrhold2(11),regfil_4_3,clock,'0','0',addrhold2_CE(11));
|
| 2045 |
|
|
<br/> addrhold2_CE(11) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2046 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 2047 |
|
|
<br/> data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND
|
| 2048 |
|
|
<br/> NOT data(7).PIN AND data(5).PIN);
|
| 2049 |
|
|
</td></tr><tr><td>
|
| 2050 |
|
|
FDCPE_addrhold212: FDCPE port map (addrhold2(12),regfil_4_4,clock,'0','0',addrhold2_CE(12));
|
| 2051 |
|
|
<br/> addrhold2_CE(12) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2052 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 2053 |
|
|
<br/> data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND
|
| 2054 |
|
|
<br/> NOT data(7).PIN AND data(5).PIN);
|
| 2055 |
|
|
</td></tr><tr><td>
|
| 2056 |
|
|
FDCPE_addrhold213: FDCPE port map (addrhold2(13),regfil_4_5,clock,'0','0',addrhold2_CE(13));
|
| 2057 |
|
|
<br/> addrhold2_CE(13) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2058 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 2059 |
|
|
<br/> data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND
|
| 2060 |
|
|
<br/> NOT data(7).PIN AND data(5).PIN);
|
| 2061 |
|
|
</td></tr><tr><td>
|
| 2062 |
|
|
FDCPE_addrhold214: FDCPE port map (addrhold2(14),regfil_4_6,clock,'0','0',addrhold2_CE(14));
|
| 2063 |
|
|
<br/> addrhold2_CE(14) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2064 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 2065 |
|
|
<br/> data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND
|
| 2066 |
|
|
<br/> NOT data(7).PIN AND data(5).PIN);
|
| 2067 |
|
|
</td></tr><tr><td>
|
| 2068 |
|
|
FDCPE_addrhold215: FDCPE port map (addrhold2(15),regfil_4_7,clock,'0','0',addrhold2_CE(15));
|
| 2069 |
|
|
<br/> addrhold2_CE(15) <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2070 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 2071 |
|
|
<br/> data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND
|
| 2072 |
|
|
<br/> NOT data(7).PIN AND data(5).PIN);
|
| 2073 |
|
|
</td></tr><tr><td>
|
| 2074 |
|
|
FTCPE_addrhold0: FTCPE port map (addrhold(0),addrhold_T(0),clock,'0','0','1');
|
| 2075 |
|
|
<br/> addrhold_T(0) <= ((N_PZ_1948)
|
| 2076 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2077 |
|
|
<br/> state(1) AND state(0) AND data(0).PIN AND NOT addrhold(0))
|
| 2078 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2079 |
|
|
<br/> state(1) AND state(0) AND NOT data(0).PIN AND addrhold(0))
|
| 2080 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2081 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2082 |
|
|
<br/> addrhold(0) AND NOT addrhold2(0))
|
| 2083 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2084 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2085 |
|
|
<br/> NOT addrhold(0) AND addrhold2(0))
|
| 2086 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2087 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 2088 |
|
|
<br/> NOT _cmp_eq0004 AND addrhold(0) AND N_PZ_1921 AND _xor0000)
|
| 2089 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2090 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 2091 |
|
|
<br/> NOT _cmp_eq0004 AND NOT addrhold(0) AND N_PZ_1921 AND NOT _xor0000)
|
| 2092 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2093 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2094 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(0) AND NOT pc(0))
|
| 2095 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2096 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2097 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(0) AND pc(0))
|
| 2098 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2099 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 2100 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2101 |
|
|
<br/> NOT data(5).PIN AND NOT addrhold(0) AND regfil_2_0)
|
| 2102 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2103 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 2104 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2105 |
|
|
<br/> NOT data(5).PIN AND NOT addrhold(0) AND regfil_2_1)
|
| 2106 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2107 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 2108 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2109 |
|
|
<br/> NOT data(5).PIN AND NOT addrhold(0) AND regfil_2_2)
|
| 2110 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2111 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 2112 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2113 |
|
|
<br/> NOT data(5).PIN AND NOT addrhold(0) AND regfil_2_5)
|
| 2114 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2115 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 2116 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2117 |
|
|
<br/> NOT data(5).PIN AND NOT addrhold(0) AND regfil_2_3)
|
| 2118 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2119 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 2120 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2121 |
|
|
<br/> NOT data(5).PIN AND NOT addrhold(0) AND regfil_2_7)
|
| 2122 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2123 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 2124 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2125 |
|
|
<br/> NOT data(5).PIN AND NOT addrhold(0) AND regfil_2_6)
|
| 2126 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2127 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 2128 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2129 |
|
|
<br/> NOT data(5).PIN AND NOT addrhold(0) AND regfil_2_4)
|
| 2130 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2131 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND
|
| 2132 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2133 |
|
|
<br/> NOT data(5).PIN AND addrhold(0) AND _xor0068)
|
| 2134 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2135 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND
|
| 2136 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2137 |
|
|
<br/> NOT data(5).PIN AND NOT addrhold(0) AND NOT _xor0068)
|
| 2138 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2139 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 2140 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2141 |
|
|
<br/> NOT data(5).PIN AND addrhold(0) AND NOT regfil_2_0 AND NOT regfil_2_1 AND
|
| 2142 |
|
|
<br/> NOT regfil_2_2 AND NOT regfil_2_5 AND NOT regfil_2_3 AND NOT regfil_2_7 AND
|
| 2143 |
|
|
<br/> NOT regfil_2_6 AND NOT regfil_2_4));
|
| 2144 |
|
|
</td></tr><tr><td>
|
| 2145 |
|
|
FTCPE_addrhold1: FTCPE port map (addrhold(1),addrhold_T(1),clock,'0','0','1');
|
| 2146 |
|
|
<br/> addrhold_T(1) <= ((addrhold(0) AND N_PZ_1948)
|
| 2147 |
|
|
<br/> OR (addrhold(1) AND N_PZ_1133)
|
| 2148 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2149 |
|
|
<br/> state(1) AND state(0) AND data(1).PIN AND NOT addrhold(1))
|
| 2150 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2151 |
|
|
<br/> state(1) AND state(0) AND NOT data(1).PIN AND addrhold(1))
|
| 2152 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2153 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2154 |
|
|
<br/> addrhold(1) AND NOT addrhold2(1))
|
| 2155 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2156 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2157 |
|
|
<br/> NOT addrhold(1) AND addrhold2(1))
|
| 2158 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2159 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2160 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(1) AND NOT pc(1))
|
| 2161 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2162 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2163 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(1) AND pc(1)));
|
| 2164 |
|
|
</td></tr><tr><td>
|
| 2165 |
|
|
FTCPE_addrhold2: FTCPE port map (addrhold(2),addrhold_T(2),clock,'0','0','1');
|
| 2166 |
|
|
<br/> addrhold_T(2) <= ((addrhold(2) AND N_PZ_1133)
|
| 2167 |
|
|
<br/> OR (addrhold(0) AND addrhold(1) AND N_PZ_1948)
|
| 2168 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2169 |
|
|
<br/> state(1) AND state(0) AND data(2).PIN AND NOT addrhold(2))
|
| 2170 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2171 |
|
|
<br/> state(1) AND state(0) AND NOT data(2).PIN AND addrhold(2))
|
| 2172 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2173 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2174 |
|
|
<br/> addrhold(2) AND NOT addrhold2(2))
|
| 2175 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2176 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2177 |
|
|
<br/> NOT addrhold(2) AND addrhold2(2))
|
| 2178 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2179 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2180 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(2) AND NOT pc(2))
|
| 2181 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2182 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2183 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(2) AND pc(2)));
|
| 2184 |
|
|
</td></tr><tr><td>
|
| 2185 |
|
|
FTCPE_addrhold3: FTCPE port map (addrhold(3),addrhold_T(3),clock,'0','0','1');
|
| 2186 |
|
|
<br/> addrhold_T(3) <= ((addrhold(3) AND N_PZ_1133)
|
| 2187 |
|
|
<br/> OR (addrhold(0) AND addrhold(1) AND addrhold(2) AND
|
| 2188 |
|
|
<br/> N_PZ_1948)
|
| 2189 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2190 |
|
|
<br/> state(1) AND state(0) AND data(3).PIN AND NOT addrhold(3))
|
| 2191 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2192 |
|
|
<br/> state(1) AND state(0) AND NOT data(3).PIN AND addrhold(3))
|
| 2193 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2194 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2195 |
|
|
<br/> addrhold(3) AND NOT addrhold2(3))
|
| 2196 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2197 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2198 |
|
|
<br/> NOT addrhold(3) AND addrhold2(3))
|
| 2199 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2200 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2201 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND pc(3) AND NOT addrhold(3))
|
| 2202 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2203 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2204 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT pc(3) AND addrhold(3)));
|
| 2205 |
|
|
</td></tr><tr><td>
|
| 2206 |
|
|
FTCPE_addrhold4: FTCPE port map (addrhold(4),addrhold_T(4),clock,'0','0','1');
|
| 2207 |
|
|
<br/> addrhold_T(4) <= ((addrhold(4) AND N_PZ_1133)
|
| 2208 |
|
|
<br/> OR (addrhold(3) AND addrhold(0) AND addrhold(1) AND
|
| 2209 |
|
|
<br/> addrhold(2) AND N_PZ_1948)
|
| 2210 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2211 |
|
|
<br/> state(1) AND state(0) AND data(4).PIN AND NOT addrhold(4))
|
| 2212 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2213 |
|
|
<br/> state(1) AND state(0) AND NOT data(4).PIN AND addrhold(4))
|
| 2214 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2215 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2216 |
|
|
<br/> addrhold(4) AND NOT addrhold2(4))
|
| 2217 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2218 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2219 |
|
|
<br/> NOT addrhold(4) AND addrhold2(4))
|
| 2220 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2221 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2222 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(4) AND NOT pc(4))
|
| 2223 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2224 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2225 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(4) AND pc(4)));
|
| 2226 |
|
|
</td></tr><tr><td>
|
| 2227 |
|
|
FTCPE_addrhold5: FTCPE port map (addrhold(5),addrhold_T(5),clock,'0','0','1');
|
| 2228 |
|
|
<br/> addrhold_T(5) <= ((addrhold(5) AND N_PZ_1133)
|
| 2229 |
|
|
<br/> OR (addrhold(3) AND addrhold(0) AND addrhold(1) AND
|
| 2230 |
|
|
<br/> addrhold(2) AND addrhold(4) AND N_PZ_1948)
|
| 2231 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2232 |
|
|
<br/> state(1) AND state(0) AND data(5).PIN AND NOT addrhold(5))
|
| 2233 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2234 |
|
|
<br/> state(1) AND state(0) AND NOT data(5).PIN AND addrhold(5))
|
| 2235 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2236 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2237 |
|
|
<br/> addrhold(5) AND NOT addrhold2(5))
|
| 2238 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2239 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2240 |
|
|
<br/> NOT addrhold(5) AND addrhold2(5))
|
| 2241 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2242 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2243 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(5) AND NOT pc(5))
|
| 2244 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2245 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2246 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(5) AND pc(5)));
|
| 2247 |
|
|
</td></tr><tr><td>
|
| 2248 |
|
|
FTCPE_addrhold6: FTCPE port map (addrhold(6),addrhold_T(6),clock,'0','0','1');
|
| 2249 |
|
|
<br/> addrhold_T(6) <= ((addrhold(6) AND N_PZ_1133)
|
| 2250 |
|
|
<br/> OR (addrhold(3) AND addrhold(0) AND addrhold(1) AND
|
| 2251 |
|
|
<br/> addrhold(2) AND addrhold(4) AND addrhold(5) AND N_PZ_1948)
|
| 2252 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2253 |
|
|
<br/> state(1) AND state(0) AND data(6).PIN AND NOT addrhold(6))
|
| 2254 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2255 |
|
|
<br/> state(1) AND state(0) AND NOT data(6).PIN AND addrhold(6))
|
| 2256 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2257 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2258 |
|
|
<br/> addrhold(6) AND NOT addrhold2(6))
|
| 2259 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2260 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2261 |
|
|
<br/> NOT addrhold(6) AND addrhold2(6))
|
| 2262 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2263 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2264 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(6) AND NOT pc(6))
|
| 2265 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2266 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2267 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(6) AND pc(6)));
|
| 2268 |
|
|
</td></tr><tr><td>
|
| 2269 |
|
|
FTCPE_addrhold7: FTCPE port map (addrhold(7),addrhold_T(7),clock,'0','0','1');
|
| 2270 |
|
|
<br/> addrhold_T(7) <= ((addrhold(7) AND N_PZ_1133)
|
| 2271 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2272 |
|
|
<br/> state(1) AND state(0) AND data(7).PIN AND NOT addrhold(7))
|
| 2273 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2274 |
|
|
<br/> state(1) AND state(0) AND NOT data(7).PIN AND addrhold(7))
|
| 2275 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 2276 |
|
|
<br/> NOT state(1) AND state(0) AND data(0).PIN AND NOT addrhold(7))
|
| 2277 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 2278 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(0).PIN AND addrhold(7))
|
| 2279 |
|
|
<br/> OR (addrhold(3) AND addrhold(0) AND addrhold(1) AND
|
| 2280 |
|
|
<br/> addrhold(2) AND addrhold(4) AND addrhold(5) AND addrhold(6) AND
|
| 2281 |
|
|
<br/> N_PZ_1948)
|
| 2282 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2283 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2284 |
|
|
<br/> addrhold(7) AND NOT addrhold2(7))
|
| 2285 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2286 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2287 |
|
|
<br/> NOT addrhold(7) AND addrhold2(7))
|
| 2288 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2289 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2290 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(7) AND NOT pc(7))
|
| 2291 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2292 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2293 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(7) AND pc(7)));
|
| 2294 |
|
|
</td></tr><tr><td>
|
| 2295 |
|
|
FTCPE_addrhold8: FTCPE port map (addrhold(8),addrhold_T(8),clock,'0','0','1');
|
| 2296 |
|
|
<br/> addrhold_T(8) <= ((addrhold(8) AND N_PZ_1133)
|
| 2297 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 2298 |
|
|
<br/> NOT state(1) AND state(0) AND data(1).PIN AND NOT addrhold(8))
|
| 2299 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 2300 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(1).PIN AND addrhold(8))
|
| 2301 |
|
|
<br/> OR (addrhold(7) AND addrhold(3) AND addrhold(0) AND
|
| 2302 |
|
|
<br/> addrhold(1) AND addrhold(2) AND addrhold(4) AND addrhold(5) AND
|
| 2303 |
|
|
<br/> addrhold(6) AND N_PZ_1948)
|
| 2304 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2305 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2306 |
|
|
<br/> addrhold(8) AND NOT addrhold2(8))
|
| 2307 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2308 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2309 |
|
|
<br/> NOT addrhold(8) AND addrhold2(8))
|
| 2310 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2311 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2312 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(8) AND NOT pc(8))
|
| 2313 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2314 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2315 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(8) AND pc(8)));
|
| 2316 |
|
|
</td></tr><tr><td>
|
| 2317 |
|
|
FTCPE_addrhold9: FTCPE port map (addrhold(9),addrhold_T(9),clock,'0','0','1');
|
| 2318 |
|
|
<br/> addrhold_T(9) <= ((addrhold(9) AND N_PZ_1133)
|
| 2319 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 2320 |
|
|
<br/> NOT state(1) AND state(0) AND data(2).PIN AND NOT addrhold(9))
|
| 2321 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 2322 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(2).PIN AND addrhold(9))
|
| 2323 |
|
|
<br/> OR (addrhold(7) AND addrhold(3) AND addrhold(0) AND
|
| 2324 |
|
|
<br/> addrhold(8) AND addrhold(1) AND addrhold(2) AND addrhold(4) AND
|
| 2325 |
|
|
<br/> addrhold(5) AND addrhold(6) AND N_PZ_1948)
|
| 2326 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2327 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2328 |
|
|
<br/> addrhold(9) AND NOT addrhold2(9))
|
| 2329 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2330 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2331 |
|
|
<br/> NOT addrhold(9) AND addrhold2(9))
|
| 2332 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2333 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2334 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(9) AND NOT pc(9))
|
| 2335 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2336 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2337 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(9) AND pc(9)));
|
| 2338 |
|
|
</td></tr><tr><td>
|
| 2339 |
|
|
FTCPE_addrhold10: FTCPE port map (addrhold(10),addrhold_T(10),clock,'0','0','1');
|
| 2340 |
|
|
<br/> addrhold_T(10) <= ((addrhold(10) AND N_PZ_1133)
|
| 2341 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 2342 |
|
|
<br/> NOT state(1) AND state(0) AND data(3).PIN AND NOT addrhold(10))
|
| 2343 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 2344 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(3).PIN AND addrhold(10))
|
| 2345 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2346 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2347 |
|
|
<br/> addrhold(10) AND NOT addrhold2(10))
|
| 2348 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2349 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2350 |
|
|
<br/> NOT addrhold(10) AND addrhold2(10))
|
| 2351 |
|
|
<br/> OR (addrhold(7) AND addrhold(3) AND addrhold(0) AND
|
| 2352 |
|
|
<br/> addrhold(9) AND addrhold(8) AND addrhold(1) AND addrhold(2) AND
|
| 2353 |
|
|
<br/> addrhold(4) AND addrhold(5) AND addrhold(6) AND N_PZ_1948)
|
| 2354 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2355 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2356 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(10) AND
|
| 2357 |
|
|
<br/> NOT pc(10))
|
| 2358 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2359 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2360 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(10) AND
|
| 2361 |
|
|
<br/> pc(10)));
|
| 2362 |
|
|
</td></tr><tr><td>
|
| 2363 |
|
|
FTCPE_addrhold11: FTCPE port map (addrhold(11),addrhold_T(11),clock,'0','0','1');
|
| 2364 |
|
|
<br/> addrhold_T(11) <= ((addrhold(11) AND N_PZ_1133)
|
| 2365 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 2366 |
|
|
<br/> NOT state(1) AND state(0) AND data(4).PIN AND NOT addrhold(11))
|
| 2367 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 2368 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(4).PIN AND addrhold(11))
|
| 2369 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2370 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2371 |
|
|
<br/> addrhold(11) AND NOT addrhold2(11))
|
| 2372 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2373 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2374 |
|
|
<br/> NOT addrhold(11) AND addrhold2(11))
|
| 2375 |
|
|
<br/> OR (addrhold(7) AND addrhold(3) AND addrhold(0) AND
|
| 2376 |
|
|
<br/> addrhold(9) AND addrhold(8) AND addrhold(1) AND addrhold(2) AND
|
| 2377 |
|
|
<br/> addrhold(10) AND addrhold(4) AND addrhold(5) AND addrhold(6) AND
|
| 2378 |
|
|
<br/> N_PZ_1948)
|
| 2379 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2380 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2381 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(11) AND
|
| 2382 |
|
|
<br/> NOT pc(11))
|
| 2383 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2384 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2385 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(11) AND
|
| 2386 |
|
|
<br/> pc(11)));
|
| 2387 |
|
|
</td></tr><tr><td>
|
| 2388 |
|
|
FTCPE_addrhold12: FTCPE port map (addrhold(12),addrhold_T(12),clock,'0','0','1');
|
| 2389 |
|
|
<br/> addrhold_T(12) <= ((N_PZ_2405)
|
| 2390 |
|
|
<br/> OR (addrhold(12) AND N_PZ_1133)
|
| 2391 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 2392 |
|
|
<br/> NOT state(1) AND state(0) AND data(5).PIN AND NOT addrhold(12))
|
| 2393 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 2394 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(5).PIN AND addrhold(12))
|
| 2395 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2396 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2397 |
|
|
<br/> addrhold(12) AND NOT addrhold2(12))
|
| 2398 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2399 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2400 |
|
|
<br/> NOT addrhold(12) AND addrhold2(12))
|
| 2401 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2402 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2403 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(12) AND
|
| 2404 |
|
|
<br/> NOT pc(12))
|
| 2405 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2406 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2407 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(12) AND
|
| 2408 |
|
|
<br/> pc(12)));
|
| 2409 |
|
|
</td></tr><tr><td>
|
| 2410 |
|
|
FTCPE_addrhold13: FTCPE port map (addrhold(13),addrhold_T(13),clock,'0','0','1');
|
| 2411 |
|
|
<br/> addrhold_T(13) <= ((addrhold(13) AND N_PZ_1133)
|
| 2412 |
|
|
<br/> OR (addrhold(12) AND N_PZ_2405)
|
| 2413 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 2414 |
|
|
<br/> NOT state(1) AND state(0) AND data(6).PIN AND NOT addrhold(13))
|
| 2415 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 2416 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(6).PIN AND addrhold(13))
|
| 2417 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2418 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2419 |
|
|
<br/> addrhold(13) AND NOT addrhold2(13))
|
| 2420 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2421 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2422 |
|
|
<br/> NOT addrhold(13) AND addrhold2(13))
|
| 2423 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2424 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2425 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(13) AND
|
| 2426 |
|
|
<br/> NOT pc(13))
|
| 2427 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2428 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2429 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(13) AND
|
| 2430 |
|
|
<br/> pc(13)));
|
| 2431 |
|
|
</td></tr><tr><td>
|
| 2432 |
|
|
FTCPE_addrhold14: FTCPE port map (addrhold(14),addrhold_T(14),clock,'0','0','1');
|
| 2433 |
|
|
<br/> addrhold_T(14) <= ((addrhold(14) AND N_PZ_1133)
|
| 2434 |
|
|
<br/> OR (addrhold(13) AND addrhold(12) AND N_PZ_2405)
|
| 2435 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 2436 |
|
|
<br/> NOT state(1) AND state(0) AND data(7).PIN AND NOT addrhold(14))
|
| 2437 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 2438 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(7).PIN AND addrhold(14))
|
| 2439 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2440 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2441 |
|
|
<br/> addrhold(14) AND NOT addrhold2(14))
|
| 2442 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2443 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 2444 |
|
|
<br/> NOT addrhold(14) AND addrhold2(14))
|
| 2445 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2446 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2447 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND addrhold(14) AND
|
| 2448 |
|
|
<br/> NOT pc(14))
|
| 2449 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2450 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2451 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND NOT addrhold(14) AND
|
| 2452 |
|
|
<br/> pc(14)));
|
| 2453 |
|
|
</td></tr><tr><td>
|
| 2454 |
|
|
FTCPE_addrhold15: FTCPE port map (addrhold(15),addrhold_T(15),clock,'0','0','1');
|
| 2455 |
|
|
<br/> addrhold_T(15) <= ((NOT reset AND NOT addrhold(15) AND _mux003739)
|
| 2456 |
|
|
<br/> OR (NOT reset AND NOT state(2) AND N_PZ_1209 AND addrhold(15) AND
|
| 2457 |
|
|
<br/> NOT _mux003739)
|
| 2458 |
|
|
<br/> OR (NOT state(3) AND state(2) AND NOT state(4) AND NOT state(1) AND
|
| 2459 |
|
|
<br/> state(0) AND NOT N_PZ_1209 AND addrhold(15) AND NOT _mux003739)
|
| 2460 |
|
|
<br/> OR (NOT state(2) AND state(1) AND N_PZ_1066 AND addrhold(7) AND
|
| 2461 |
|
|
<br/> addrhold(3) AND addrhold(0) AND addrhold(9) AND addrhold(8) AND
|
| 2462 |
|
|
<br/> addrhold(1) AND addrhold(2) AND addrhold(10) AND addrhold(4) AND
|
| 2463 |
|
|
<br/> addrhold(14) AND addrhold(13) AND addrhold(12) AND addrhold(11) AND
|
| 2464 |
|
|
<br/> addrhold(5) AND addrhold(6) AND NOT _mux003739)
|
| 2465 |
|
|
<br/> OR (NOT state(3) AND state(2) AND state(4) AND state(1) AND
|
| 2466 |
|
|
<br/> NOT N_PZ_1066 AND NOT N_PZ_1209 AND addrhold(7) AND addrhold(3) AND
|
| 2467 |
|
|
<br/> addrhold(0) AND addrhold(9) AND addrhold(8) AND addrhold(1) AND
|
| 2468 |
|
|
<br/> addrhold(2) AND addrhold(10) AND addrhold(4) AND addrhold(14) AND
|
| 2469 |
|
|
<br/> addrhold(13) AND addrhold(12) AND addrhold(11) AND addrhold(5) AND
|
| 2470 |
|
|
<br/> addrhold(6) AND NOT _mux003739));
|
| 2471 |
|
|
</td></tr><tr><td>
|
| 2472 |
|
|
FDCPE_alucin: FDCPE port map (alucin,carry,clock,'0','0',alucin_CE);
|
| 2473 |
|
|
<br/> alucin_CE <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2474 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN);
|
| 2475 |
|
|
</td></tr><tr><td>
|
| 2476 |
|
|
FDCPE_alucout: FDCPE port map (alucout,alucout_D,clock,'0','0','1');
|
| 2477 |
|
|
<br/> alucout_D <= NOT ((NOT m1/Mmux__mux0000_Result1 AND
|
| 2478 |
|
|
<br/> NOT m1/Mmux__mux0000_Result3)
|
| 2479 |
|
|
<br/> XOR ((NOT m1/Mmux__mux0000_Result1 AND alusel(1) AND NOT alusel(0) AND
|
| 2480 |
|
|
<br/> NOT alusel(2) AND m1/Msub__AUX_23__xor0019 AND NOT N_PZ_1092 AND
|
| 2481 |
|
|
<br/> NOT m1/Mmux__mux0000_Result3)
|
| 2482 |
|
|
<br/> OR (NOT m1/Mmux__mux0000_Result1 AND alusel(1) AND NOT alusel(0) AND
|
| 2483 |
|
|
<br/> NOT alusel(2) AND N_PZ_1092 AND NOT aluopra(7) AND
|
| 2484 |
|
|
<br/> NOT m1/Mmux__mux0000_Result3)
|
| 2485 |
|
|
<br/> OR (NOT m1/Mmux__mux0000_Result1 AND NOT alusel(1) AND NOT alusel(0) AND
|
| 2486 |
|
|
<br/> NOT alusel(2) AND N_PZ_1092 AND NOT m1/_addsub0000(7) AND
|
| 2487 |
|
|
<br/> NOT m1/Mmux__mux0000_Result3)
|
| 2488 |
|
|
<br/> OR (NOT m1/Mmux__mux0000_Result1 AND NOT alusel(1) AND NOT alusel(0) AND
|
| 2489 |
|
|
<br/> NOT alusel(2) AND NOT N_PZ_1092 AND aluopra(7) AND
|
| 2490 |
|
|
<br/> NOT m1/Mmux__mux0000_Result3)));
|
| 2491 |
|
|
</td></tr><tr><td>
|
| 2492 |
|
|
FDCPE_aluopra0: FDCPE port map (aluopra(0),aluopra_D(0),clock,'0','0','1');
|
| 2493 |
|
|
<br/> aluopra_D(0) <= NOT (((NOT N_PZ_1099 AND NOT aluopra(0))
|
| 2494 |
|
|
<br/> OR (NOT regfil_5_0 AND N_PZ_1129 AND N_PZ_1099)
|
| 2495 |
|
|
<br/> OR (regd(2) AND regd(1) AND regd(0) AND NOT regfil_7_0 AND
|
| 2496 |
|
|
<br/> N_PZ_1099)
|
| 2497 |
|
|
<br/> OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2498 |
|
|
<br/> NOT regfil_6_0)
|
| 2499 |
|
|
<br/> OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND NOT regfil_4_0 AND
|
| 2500 |
|
|
<br/> N_PZ_1099)
|
| 2501 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND NOT regfil_3_0 AND
|
| 2502 |
|
|
<br/> N_PZ_1099)
|
| 2503 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND NOT regfil_2_0 AND
|
| 2504 |
|
|
<br/> N_PZ_1099)
|
| 2505 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND NOT regfil_1_0 AND
|
| 2506 |
|
|
<br/> N_PZ_1099)
|
| 2507 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2508 |
|
|
<br/> NOT regfil_0_0)));
|
| 2509 |
|
|
</td></tr><tr><td>
|
| 2510 |
|
|
FDCPE_aluopra1: FDCPE port map (aluopra(1),aluopra_D(1),clock,'0','0','1');
|
| 2511 |
|
|
<br/> aluopra_D(1) <= NOT (((NOT aluopra(1) AND NOT N_PZ_1099)
|
| 2512 |
|
|
<br/> OR (NOT regfil_5_1 AND N_PZ_1129 AND N_PZ_1099)
|
| 2513 |
|
|
<br/> OR (regd(2) AND regd(1) AND regd(0) AND NOT regfil_7_1 AND
|
| 2514 |
|
|
<br/> N_PZ_1099)
|
| 2515 |
|
|
<br/> OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2516 |
|
|
<br/> NOT regfil_6_1)
|
| 2517 |
|
|
<br/> OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND NOT regfil_4_1 AND
|
| 2518 |
|
|
<br/> N_PZ_1099)
|
| 2519 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND NOT regfil_3_1 AND
|
| 2520 |
|
|
<br/> N_PZ_1099)
|
| 2521 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND NOT regfil_2_1 AND
|
| 2522 |
|
|
<br/> N_PZ_1099)
|
| 2523 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND NOT regfil_1_1 AND
|
| 2524 |
|
|
<br/> N_PZ_1099)
|
| 2525 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2526 |
|
|
<br/> NOT regfil_0_1)));
|
| 2527 |
|
|
</td></tr><tr><td>
|
| 2528 |
|
|
FDCPE_aluopra2: FDCPE port map (aluopra(2),aluopra_D(2),clock,'0','0','1');
|
| 2529 |
|
|
<br/> aluopra_D(2) <= NOT (((NOT N_PZ_1099 AND NOT aluopra(2))
|
| 2530 |
|
|
<br/> OR (N_PZ_1129 AND NOT regfil_5_2 AND N_PZ_1099)
|
| 2531 |
|
|
<br/> OR (regd(2) AND regd(1) AND regd(0) AND NOT regfil_7_2 AND
|
| 2532 |
|
|
<br/> N_PZ_1099)
|
| 2533 |
|
|
<br/> OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2534 |
|
|
<br/> NOT regfil_6_2)
|
| 2535 |
|
|
<br/> OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND NOT regfil_4_2 AND
|
| 2536 |
|
|
<br/> N_PZ_1099)
|
| 2537 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND NOT regfil_3_2 AND
|
| 2538 |
|
|
<br/> N_PZ_1099)
|
| 2539 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2540 |
|
|
<br/> NOT regfil_2_2)
|
| 2541 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND NOT regfil_1_2 AND
|
| 2542 |
|
|
<br/> N_PZ_1099)
|
| 2543 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2544 |
|
|
<br/> NOT regfil_0_2)));
|
| 2545 |
|
|
</td></tr><tr><td>
|
| 2546 |
|
|
FDCPE_aluopra3: FDCPE port map (aluopra(3),aluopra_D(3),clock,'0','0','1');
|
| 2547 |
|
|
<br/> aluopra_D(3) <= NOT (((NOT N_PZ_1099 AND NOT aluopra(3))
|
| 2548 |
|
|
<br/> OR (NOT regfil_5_3 AND N_PZ_1129 AND N_PZ_1099)
|
| 2549 |
|
|
<br/> OR (regd(2) AND regd(1) AND regd(0) AND NOT regfil_7_3 AND
|
| 2550 |
|
|
<br/> N_PZ_1099)
|
| 2551 |
|
|
<br/> OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2552 |
|
|
<br/> NOT regfil_6_3)
|
| 2553 |
|
|
<br/> OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2554 |
|
|
<br/> NOT regfil_4_3)
|
| 2555 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND N_PZ_1099 AND
|
| 2556 |
|
|
<br/> NOT regfil_3_3)
|
| 2557 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2558 |
|
|
<br/> NOT regfil_2_3)
|
| 2559 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND N_PZ_1099 AND
|
| 2560 |
|
|
<br/> NOT regfil_1_3)
|
| 2561 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2562 |
|
|
<br/> NOT regfil_0_3)));
|
| 2563 |
|
|
</td></tr><tr><td>
|
| 2564 |
|
|
FDCPE_aluopra4: FDCPE port map (aluopra(4),aluopra_D(4),clock,'0','0','1');
|
| 2565 |
|
|
<br/> aluopra_D(4) <= NOT (((NOT N_PZ_1099 AND NOT aluopra(4))
|
| 2566 |
|
|
<br/> OR (N_PZ_1129 AND N_PZ_1099 AND NOT regfil_5_4)
|
| 2567 |
|
|
<br/> OR (regd(2) AND regd(1) AND regd(0) AND N_PZ_1099 AND
|
| 2568 |
|
|
<br/> NOT regfil_7_4)
|
| 2569 |
|
|
<br/> OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2570 |
|
|
<br/> NOT regfil_6_4)
|
| 2571 |
|
|
<br/> OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2572 |
|
|
<br/> NOT regfil_4_4)
|
| 2573 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND N_PZ_1099 AND
|
| 2574 |
|
|
<br/> NOT regfil_3_4)
|
| 2575 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2576 |
|
|
<br/> NOT regfil_2_4)
|
| 2577 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND N_PZ_1099 AND
|
| 2578 |
|
|
<br/> NOT regfil_1_4)
|
| 2579 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2580 |
|
|
<br/> NOT regfil_0_4)));
|
| 2581 |
|
|
</td></tr><tr><td>
|
| 2582 |
|
|
FDCPE_aluopra5: FDCPE port map (aluopra(5),aluopra_D(5),clock,'0','0','1');
|
| 2583 |
|
|
<br/> aluopra_D(5) <= NOT (((NOT N_PZ_1099 AND NOT aluopra(5))
|
| 2584 |
|
|
<br/> OR (N_PZ_1129 AND N_PZ_1099 AND NOT regfil_5_5)
|
| 2585 |
|
|
<br/> OR (regd(2) AND regd(1) AND regd(0) AND N_PZ_1099 AND
|
| 2586 |
|
|
<br/> NOT regfil_7_5)
|
| 2587 |
|
|
<br/> OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2588 |
|
|
<br/> NOT regfil_6_5)
|
| 2589 |
|
|
<br/> OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2590 |
|
|
<br/> NOT regfil_4_5)
|
| 2591 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND N_PZ_1099 AND
|
| 2592 |
|
|
<br/> NOT regfil_3_5)
|
| 2593 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2594 |
|
|
<br/> NOT regfil_2_5)
|
| 2595 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND N_PZ_1099 AND
|
| 2596 |
|
|
<br/> NOT regfil_1_5)
|
| 2597 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2598 |
|
|
<br/> NOT regfil_0_5)));
|
| 2599 |
|
|
</td></tr><tr><td>
|
| 2600 |
|
|
FDCPE_aluopra6: FDCPE port map (aluopra(6),aluopra_D(6),clock,'0','0','1');
|
| 2601 |
|
|
<br/> aluopra_D(6) <= NOT (((NOT N_PZ_1099 AND NOT aluopra(6))
|
| 2602 |
|
|
<br/> OR (N_PZ_1129 AND N_PZ_1099 AND NOT regfil_5_6)
|
| 2603 |
|
|
<br/> OR (regd(2) AND regd(1) AND regd(0) AND N_PZ_1099 AND
|
| 2604 |
|
|
<br/> NOT regfil_7_6)
|
| 2605 |
|
|
<br/> OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2606 |
|
|
<br/> NOT regfil_6_6)
|
| 2607 |
|
|
<br/> OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2608 |
|
|
<br/> NOT regfil_4_6)
|
| 2609 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND N_PZ_1099 AND
|
| 2610 |
|
|
<br/> NOT regfil_3_6)
|
| 2611 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2612 |
|
|
<br/> NOT regfil_2_6)
|
| 2613 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND N_PZ_1099 AND
|
| 2614 |
|
|
<br/> NOT regfil_1_6)
|
| 2615 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2616 |
|
|
<br/> NOT regfil_0_6)));
|
| 2617 |
|
|
</td></tr><tr><td>
|
| 2618 |
|
|
FDCPE_aluopra7: FDCPE port map (aluopra(7),aluopra_D(7),clock,'0','0','1');
|
| 2619 |
|
|
<br/> aluopra_D(7) <= NOT (((NOT N_PZ_1099 AND NOT aluopra(7))
|
| 2620 |
|
|
<br/> OR (NOT regfil_5_7 AND N_PZ_1129 AND N_PZ_1099)
|
| 2621 |
|
|
<br/> OR (regd(2) AND regd(1) AND regd(0) AND N_PZ_1099 AND
|
| 2622 |
|
|
<br/> NOT regfil_7_7)
|
| 2623 |
|
|
<br/> OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2624 |
|
|
<br/> NOT regfil_6_7)
|
| 2625 |
|
|
<br/> OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2626 |
|
|
<br/> NOT regfil_4_7)
|
| 2627 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND N_PZ_1099 AND
|
| 2628 |
|
|
<br/> NOT regfil_3_7)
|
| 2629 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2630 |
|
|
<br/> NOT regfil_2_7)
|
| 2631 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND N_PZ_1099 AND
|
| 2632 |
|
|
<br/> NOT regfil_1_7)
|
| 2633 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1099 AND
|
| 2634 |
|
|
<br/> NOT regfil_0_7)));
|
| 2635 |
|
|
</td></tr><tr><td>
|
| 2636 |
|
|
FTCPE_aluoprb0: FTCPE port map (aluoprb(0),aluoprb_T(0),clock,'0','0','1');
|
| 2637 |
|
|
<br/> aluoprb_T(0) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2638 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND
|
| 2639 |
|
|
<br/> aluoprb(0) AND _COND_18(0))
|
| 2640 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2641 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND
|
| 2642 |
|
|
<br/> NOT aluoprb(0) AND NOT _COND_18(0))
|
| 2643 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2644 |
|
|
<br/> NOT state(1) AND NOT state(0) AND data(0).PIN AND NOT regd(2) AND NOT regd(1) AND
|
| 2645 |
|
|
<br/> NOT regd(0) AND NOT aluoprb(0))
|
| 2646 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2647 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT data(0).PIN AND NOT regd(2) AND NOT regd(1) AND
|
| 2648 |
|
|
<br/> NOT regd(0) AND aluoprb(0))
|
| 2649 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2650 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND
|
| 2651 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND NOT aluoprb(0)));
|
| 2652 |
|
|
</td></tr><tr><td>
|
| 2653 |
|
|
FTCPE_aluoprb1: FTCPE port map (aluoprb(1),aluoprb_T(1),clock,'0','0','1');
|
| 2654 |
|
|
<br/> aluoprb_T(1) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2655 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND
|
| 2656 |
|
|
<br/> aluoprb(1) AND _COND_18(1))
|
| 2657 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2658 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND
|
| 2659 |
|
|
<br/> NOT aluoprb(1) AND NOT _COND_18(1))
|
| 2660 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2661 |
|
|
<br/> NOT state(1) AND NOT state(0) AND data(0).PIN AND NOT regd(2) AND NOT regd(1) AND
|
| 2662 |
|
|
<br/> regd(0) AND NOT aluoprb(1))
|
| 2663 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2664 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT data(0).PIN AND NOT regd(2) AND NOT regd(1) AND
|
| 2665 |
|
|
<br/> regd(0) AND aluoprb(1))
|
| 2666 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2667 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND
|
| 2668 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND aluoprb(1)));
|
| 2669 |
|
|
</td></tr><tr><td>
|
| 2670 |
|
|
FTCPE_aluoprb2: FTCPE port map (aluoprb(2),aluoprb_T(2),clock,'0','0','1');
|
| 2671 |
|
|
<br/> aluoprb_T(2) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2672 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND
|
| 2673 |
|
|
<br/> aluoprb(2) AND _COND_18(2))
|
| 2674 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2675 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND
|
| 2676 |
|
|
<br/> NOT aluoprb(2) AND NOT _COND_18(2))
|
| 2677 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2678 |
|
|
<br/> NOT state(1) AND NOT state(0) AND data(0).PIN AND NOT regd(2) AND regd(1) AND
|
| 2679 |
|
|
<br/> NOT regd(0) AND NOT aluoprb(2))
|
| 2680 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2681 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT data(0).PIN AND NOT regd(2) AND regd(1) AND
|
| 2682 |
|
|
<br/> NOT regd(0) AND aluoprb(2))
|
| 2683 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2684 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND
|
| 2685 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND aluoprb(2)));
|
| 2686 |
|
|
</td></tr><tr><td>
|
| 2687 |
|
|
FTCPE_aluoprb3: FTCPE port map (aluoprb(3),aluoprb_T(3),clock,'0','0','1');
|
| 2688 |
|
|
<br/> aluoprb_T(3) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2689 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND
|
| 2690 |
|
|
<br/> aluoprb(3) AND _COND_18(3))
|
| 2691 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2692 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND
|
| 2693 |
|
|
<br/> NOT aluoprb(3) AND NOT _COND_18(3))
|
| 2694 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2695 |
|
|
<br/> NOT state(1) AND NOT state(0) AND data(0).PIN AND NOT regd(2) AND regd(1) AND
|
| 2696 |
|
|
<br/> regd(0) AND NOT aluoprb(3))
|
| 2697 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2698 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT data(0).PIN AND NOT regd(2) AND regd(1) AND
|
| 2699 |
|
|
<br/> regd(0) AND aluoprb(3))
|
| 2700 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2701 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND
|
| 2702 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND aluoprb(3)));
|
| 2703 |
|
|
</td></tr><tr><td>
|
| 2704 |
|
|
FTCPE_aluoprb4: FTCPE port map (aluoprb(4),aluoprb_T(4),clock,'0','0','1');
|
| 2705 |
|
|
<br/> aluoprb_T(4) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2706 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND
|
| 2707 |
|
|
<br/> aluoprb(4) AND _COND_18(4))
|
| 2708 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2709 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND
|
| 2710 |
|
|
<br/> NOT aluoprb(4) AND NOT _COND_18(4))
|
| 2711 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2712 |
|
|
<br/> NOT state(1) AND NOT state(0) AND data(0).PIN AND regd(2) AND NOT regd(1) AND
|
| 2713 |
|
|
<br/> NOT regd(0) AND NOT aluoprb(4))
|
| 2714 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2715 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT data(0).PIN AND regd(2) AND NOT regd(1) AND
|
| 2716 |
|
|
<br/> NOT regd(0) AND aluoprb(4))
|
| 2717 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2718 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND
|
| 2719 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND aluoprb(4)));
|
| 2720 |
|
|
</td></tr><tr><td>
|
| 2721 |
|
|
FTCPE_aluoprb5: FTCPE port map (aluoprb(5),aluoprb_T(5),clock,'0','0','1');
|
| 2722 |
|
|
<br/> aluoprb_T(5) <= ((NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2723 |
|
|
<br/> NOT state(1) AND NOT state(0) AND data(0).PIN AND N_PZ_1129 AND NOT aluoprb(5))
|
| 2724 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2725 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT data(0).PIN AND N_PZ_1129 AND aluoprb(5))
|
| 2726 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2727 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND
|
| 2728 |
|
|
<br/> aluoprb(5) AND _COND_18(5))
|
| 2729 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2730 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND
|
| 2731 |
|
|
<br/> NOT aluoprb(5) AND NOT _COND_18(5))
|
| 2732 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2733 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND
|
| 2734 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND aluoprb(5)));
|
| 2735 |
|
|
</td></tr><tr><td>
|
| 2736 |
|
|
FTCPE_aluoprb6: FTCPE port map (aluoprb(6),aluoprb_T(6),clock,'0','0','1');
|
| 2737 |
|
|
<br/> aluoprb_T(6) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2738 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND
|
| 2739 |
|
|
<br/> aluoprb(6) AND _COND_18(6))
|
| 2740 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2741 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND
|
| 2742 |
|
|
<br/> NOT aluoprb(6) AND NOT _COND_18(6))
|
| 2743 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2744 |
|
|
<br/> NOT state(1) AND NOT state(0) AND data(0).PIN AND regd(2) AND regd(1) AND
|
| 2745 |
|
|
<br/> NOT regd(0) AND NOT aluoprb(6))
|
| 2746 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2747 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT data(0).PIN AND regd(2) AND regd(1) AND
|
| 2748 |
|
|
<br/> NOT regd(0) AND aluoprb(6))
|
| 2749 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2750 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND
|
| 2751 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND aluoprb(6)));
|
| 2752 |
|
|
</td></tr><tr><td>
|
| 2753 |
|
|
FTCPE_aluoprb7: FTCPE port map (aluoprb(7),aluoprb_T(7),clock,'0','0','1');
|
| 2754 |
|
|
<br/> aluoprb_T(7) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2755 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND
|
| 2756 |
|
|
<br/> aluoprb(7) AND _COND_18(7))
|
| 2757 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2758 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND
|
| 2759 |
|
|
<br/> NOT aluoprb(7) AND NOT _COND_18(7))
|
| 2760 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2761 |
|
|
<br/> NOT state(1) AND NOT state(0) AND data(0).PIN AND NOT aluoprb(7) AND regd(2) AND
|
| 2762 |
|
|
<br/> regd(1) AND regd(0))
|
| 2763 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 2764 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT data(0).PIN AND aluoprb(7) AND regd(2) AND
|
| 2765 |
|
|
<br/> regd(1) AND regd(0))
|
| 2766 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2767 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND
|
| 2768 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND aluoprb(7)));
|
| 2769 |
|
|
</td></tr><tr><td>
|
| 2770 |
|
|
FDCPE_alupar: FDCPE port map (alupar,alupar_D,clock,'0','0','1');
|
| 2771 |
|
|
<br/> alupar_D <= N_PZ_1261
|
| 2772 |
|
|
<br/> XOR ((m1/Mmux__old_resi_28_I3_Result28 AND NOT N_PZ_1997)
|
| 2773 |
|
|
<br/> OR (NOT N_PZ_1527 AND NOT N_PZ_1997)
|
| 2774 |
|
|
<br/> OR (NOT m1/Mmux__old_resi_28_I3_Result28 AND N_PZ_1527 AND
|
| 2775 |
|
|
<br/> N_PZ_1997));
|
| 2776 |
|
|
</td></tr><tr><td>
|
| 2777 |
|
|
FDCPE_alures0: FDCPE port map (alures(0),alures_D(0),clock,'0','0','1');
|
| 2778 |
|
|
<br/> alures_D(0) <= NOT (((NOT alusel(2) AND NOT m1/Mmux__old_resi_28_I7_Result30)
|
| 2779 |
|
|
<br/> OR (NOT m1/Mmux__old_resi_28_I7_Result30 AND NOT N_PZ_1076 AND
|
| 2780 |
|
|
<br/> NOT aluoprb(0))
|
| 2781 |
|
|
<br/> OR (alusel(1) AND alusel(0) AND
|
| 2782 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I7_Result30 AND NOT aluopra(0))
|
| 2783 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND
|
| 2784 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I7_Result30 AND NOT N_PZ_1076)
|
| 2785 |
|
|
<br/> OR (NOT alusel(1) AND NOT alusel(0) AND
|
| 2786 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I7_Result30 AND N_PZ_1076)));
|
| 2787 |
|
|
</td></tr><tr><td>
|
| 2788 |
|
|
FDCPE_alures1: FDCPE port map (alures(1),alures_D(1),clock,'0','0','1');
|
| 2789 |
|
|
<br/> alures_D(1) <= NOT (((NOT alusel(2) AND NOT m1/Mmux__old_resi_28_I6_Result28)
|
| 2790 |
|
|
<br/> OR (NOT m1/Mmux__old_resi_28_I6_Result28 AND NOT N_PZ_1043 AND
|
| 2791 |
|
|
<br/> NOT aluoprb(1))
|
| 2792 |
|
|
<br/> OR (alusel(1) AND alusel(0) AND
|
| 2793 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I6_Result28 AND NOT aluopra(1))
|
| 2794 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND
|
| 2795 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I6_Result28 AND NOT N_PZ_1043)
|
| 2796 |
|
|
<br/> OR (NOT alusel(1) AND NOT alusel(0) AND
|
| 2797 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I6_Result28 AND N_PZ_1043)));
|
| 2798 |
|
|
</td></tr><tr><td>
|
| 2799 |
|
|
FDCPE_alures2: FDCPE port map (alures(2),N_PZ_1213,clock,'0','0','1');
|
| 2800 |
|
|
</td></tr><tr><td>
|
| 2801 |
|
|
FDCPE_alures3: FDCPE port map (alures(3),N_PZ_1260,clock,'0','0','1');
|
| 2802 |
|
|
</td></tr><tr><td>
|
| 2803 |
|
|
FDCPE_alures4: FDCPE port map (alures(4),alures_D(4),clock,'0','0','1');
|
| 2804 |
|
|
<br/> alures_D(4) <= NOT ((NOT m1/Mmux__old_resi_28_I3_Result28 AND N_PZ_1527));
|
| 2805 |
|
|
</td></tr><tr><td>
|
| 2806 |
|
|
FDCPE_alures5: FDCPE port map (alures(5),N_PZ_1141,clock,'0','0','1');
|
| 2807 |
|
|
</td></tr><tr><td>
|
| 2808 |
|
|
FDCPE_alures6: FDCPE port map (alures(6),N_PZ_1261,clock,'0','0','1');
|
| 2809 |
|
|
</td></tr><tr><td>
|
| 2810 |
|
|
FDCPE_alures7: FDCPE port map (alures(7),N_PZ_1214,clock,'0','0','1');
|
| 2811 |
|
|
</td></tr><tr><td>
|
| 2812 |
|
|
FTCPE_alusel0: FTCPE port map (alusel(0),alusel_T(0),clock,'0','0','1');
|
| 2813 |
|
|
<br/> alusel_T(0) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2814 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(6).PIN AND
|
| 2815 |
|
|
<br/> data(7).PIN AND NOT alusel(0))
|
| 2816 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2817 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(6).PIN AND
|
| 2818 |
|
|
<br/> data(7).PIN AND alusel(0))
|
| 2819 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2820 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND
|
| 2821 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND alusel(0)));
|
| 2822 |
|
|
</td></tr><tr><td>
|
| 2823 |
|
|
FTCPE_alusel1: FTCPE port map (alusel(1),alusel_T(1),clock,'0','0','1');
|
| 2824 |
|
|
<br/> alusel_T(1) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2825 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(6).PIN AND
|
| 2826 |
|
|
<br/> data(7).PIN AND NOT alusel(1))
|
| 2827 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2828 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(6).PIN AND
|
| 2829 |
|
|
<br/> data(7).PIN AND alusel(1))
|
| 2830 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2831 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND
|
| 2832 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND alusel(1)));
|
| 2833 |
|
|
</td></tr><tr><td>
|
| 2834 |
|
|
FTCPE_alusel2: FTCPE port map (alusel(2),alusel_T(2),clock,'0','0','1');
|
| 2835 |
|
|
<br/> alusel_T(2) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2836 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND
|
| 2837 |
|
|
<br/> data(5).PIN AND NOT alusel(2))
|
| 2838 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2839 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND
|
| 2840 |
|
|
<br/> NOT data(5).PIN AND alusel(2))
|
| 2841 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2842 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND
|
| 2843 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND alusel(2)));
|
| 2844 |
|
|
</td></tr><tr><td>
|
| 2845 |
|
|
FDCPE_aluzout: FDCPE port map (aluzout,aluzout_D,clock,'0','0','1');
|
| 2846 |
|
|
<br/> aluzout_D <= ((NOT alusel(2) AND NOT m1/Mmux__old_resi_28_I7_Result30 AND
|
| 2847 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I6_Result28 AND NOT N_PZ_1213 AND NOT N_PZ_1260 AND NOT N_PZ_1141 AND
|
| 2848 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I3_Result28 AND NOT N_PZ_1214 AND NOT N_PZ_1261)
|
| 2849 |
|
|
<br/> OR (NOT m1/Mmux__old_resi_28_I7_Result30 AND
|
| 2850 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I6_Result28 AND NOT N_PZ_1213 AND NOT N_PZ_1260 AND NOT N_PZ_1141 AND
|
| 2851 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I3_Result28 AND NOT N_PZ_1214 AND NOT N_PZ_1261 AND N_PZ_1527 AND N_PZ_1954));
|
| 2852 |
|
|
</td></tr><tr><td>
|
| 2853 |
|
|
FTCPE_auxcar: FTCPE port map (auxcar,auxcar_T,clock,'0','0','1');
|
| 2854 |
|
|
<br/> auxcar_T <= ((auxcar AND N_PZ_1894)
|
| 2855 |
|
|
<br/> OR (NOT reset AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 2856 |
|
|
<br/> NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND data(1).PIN AND
|
| 2857 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND auxcar AND
|
| 2858 |
|
|
<br/> N_PZ_1986)
|
| 2859 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2860 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2861 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2862 |
|
|
<br/> N_PZ_1819 AND NOT auxcar AND NOT N_PZ_1986));
|
| 2863 |
|
|
</td></tr><tr><td>
|
| 2864 |
|
|
FTCPE_carry: FTCPE port map (carry,carry_T,clock,'0','0','1');
|
| 2865 |
|
|
<br/> carry_T <= ((NOT reset AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 2866 |
|
|
<br/> NOT state(0) AND NOT carry AND _mux000762)
|
| 2867 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2868 |
|
|
<br/> state(1) AND NOT state(0) AND NOT carry AND alucout)
|
| 2869 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2870 |
|
|
<br/> state(1) AND NOT state(0) AND carry AND NOT alucout AND NOT _mux000762)
|
| 2871 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2872 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 2873 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND
|
| 2874 |
|
|
<br/> NOT _mux000762)
|
| 2875 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2876 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2877 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND
|
| 2878 |
|
|
<br/> NOT _mux000762)
|
| 2879 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2880 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 2881 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND NOT N_PZ_1819 AND
|
| 2882 |
|
|
<br/> NOT _mux000762));
|
| 2883 |
|
|
</td></tr><tr><td>
|
| 2884 |
|
|
FDCPE_carryhold: FDCPE port map (carryhold,regfil_7_0,clock,'0','0',carryhold_CE);
|
| 2885 |
|
|
<br/> carryhold_CE <= (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2886 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 2887 |
|
|
<br/> data(2).PIN AND data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 2888 |
|
|
<br/> NOT data(7).PIN AND NOT data(5).PIN);
|
| 2889 |
|
|
</td></tr><tr><td>
|
| 2890 |
|
|
FTCPE_dataeno: FTCPE port map (dataeno,dataeno_T,clock,'0','0','1');
|
| 2891 |
|
|
<br/> dataeno_T <= ((reset AND dataeno)
|
| 2892 |
|
|
<br/> OR (NOT reset AND state(3) AND state(4) AND state(1) AND
|
| 2893 |
|
|
<br/> NOT state(0) AND NOT dataeno)
|
| 2894 |
|
|
<br/> OR (state(3) AND state(2) AND state(4) AND NOT state(1) AND
|
| 2895 |
|
|
<br/> state(0) AND dataeno)
|
| 2896 |
|
|
<br/> OR (state(3) AND NOT state(2) AND NOT state(4) AND NOT state(1) AND
|
| 2897 |
|
|
<br/> state(0) AND dataeno)
|
| 2898 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 2899 |
|
|
<br/> state(1) AND NOT state(0) AND NOT dataeno));
|
| 2900 |
|
|
</td></tr><tr><td>
|
| 2901 |
|
|
FTCPE_holding0: FTCPE port map (holding(0),holding_T(0),clock,'0','0','1');
|
| 2902 |
|
|
<br/> holding_T(0) <= ((holding(0) AND NOT regfil_4_0 AND N_PZ_2114)
|
| 2903 |
|
|
<br/> OR (NOT holding(0) AND regfil_4_0 AND N_PZ_2114)
|
| 2904 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2905 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2906 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2907 |
|
|
<br/> N_PZ_1819 AND holding(0) AND NOT regfil_7_0 AND auxcar)
|
| 2908 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2909 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2910 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2911 |
|
|
<br/> N_PZ_1819 AND holding(0) AND NOT regfil_7_0 AND NOT N_PZ_1986)
|
| 2912 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2913 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2914 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2915 |
|
|
<br/> N_PZ_1819 AND NOT holding(0) AND regfil_7_0 AND auxcar)
|
| 2916 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2917 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2918 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2919 |
|
|
<br/> N_PZ_1819 AND NOT holding(0) AND regfil_7_0 AND NOT N_PZ_1986));
|
| 2920 |
|
|
</td></tr><tr><td>
|
| 2921 |
|
|
FTCPE_holding1: FTCPE port map (holding(1),holding_T(1),clock,'0','0','1');
|
| 2922 |
|
|
<br/> holding_T(1) <= ((holding(1) AND NOT regfil_4_1 AND N_PZ_2114)
|
| 2923 |
|
|
<br/> OR (NOT holding(1) AND regfil_4_1 AND N_PZ_2114)
|
| 2924 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2925 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2926 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2927 |
|
|
<br/> N_PZ_1819 AND regfil_7_1 AND holding(1) AND regfil_7_3)
|
| 2928 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2929 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2930 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2931 |
|
|
<br/> N_PZ_1819 AND regfil_7_1 AND holding(1) AND auxcar)
|
| 2932 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2933 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2934 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2935 |
|
|
<br/> N_PZ_1819 AND NOT regfil_7_1 AND NOT holding(1) AND auxcar)
|
| 2936 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2937 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2938 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2939 |
|
|
<br/> N_PZ_1819 AND NOT regfil_7_1 AND NOT holding(1) AND regfil_7_3 AND
|
| 2940 |
|
|
<br/> regfil_7_2));
|
| 2941 |
|
|
</td></tr><tr><td>
|
| 2942 |
|
|
FTCPE_holding2: FTCPE port map (holding(2),holding_T(2),clock,'0','0','1');
|
| 2943 |
|
|
<br/> holding_T(2) <= ((holding(2) AND NOT regfil_4_2 AND N_PZ_2114)
|
| 2944 |
|
|
<br/> OR (NOT holding(2) AND regfil_4_2 AND N_PZ_2114)
|
| 2945 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2946 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2947 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2948 |
|
|
<br/> N_PZ_1819 AND regfil_7_3 AND holding(2) AND N_PZ_1890)
|
| 2949 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2950 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2951 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2952 |
|
|
<br/> N_PZ_1819 AND holding(2) AND auxcar AND N_PZ_1890)
|
| 2953 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2954 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2955 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2956 |
|
|
<br/> N_PZ_1819 AND NOT holding(2) AND auxcar AND NOT N_PZ_1890)
|
| 2957 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2958 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2959 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2960 |
|
|
<br/> N_PZ_1819 AND regfil_7_3 AND regfil_7_2 AND NOT holding(2) AND
|
| 2961 |
|
|
<br/> NOT N_PZ_1890));
|
| 2962 |
|
|
</td></tr><tr><td>
|
| 2963 |
|
|
FTCPE_holding3: FTCPE port map (holding(3),holding_T(3),clock,'0','0','1');
|
| 2964 |
|
|
<br/> holding_T(3) <= ((N_PZ_2114 AND holding(3) AND NOT regfil_4_3)
|
| 2965 |
|
|
<br/> OR (N_PZ_2114 AND NOT holding(3) AND regfil_4_3)
|
| 2966 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2967 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2968 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2969 |
|
|
<br/> N_PZ_1819 AND holding(3) AND NOT N_PZ_1986)
|
| 2970 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2971 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2972 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2973 |
|
|
<br/> N_PZ_1819 AND regfil_7_1 AND NOT regfil_7_3 AND NOT holding(3) AND auxcar)
|
| 2974 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2975 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2976 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2977 |
|
|
<br/> N_PZ_1819 AND NOT regfil_7_3 AND regfil_7_2 AND NOT holding(3) AND auxcar)
|
| 2978 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2979 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2980 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2981 |
|
|
<br/> N_PZ_1819 AND NOT regfil_7_1 AND regfil_7_3 AND NOT regfil_7_2 AND
|
| 2982 |
|
|
<br/> NOT holding(3) AND auxcar)
|
| 2983 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2984 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2985 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 2986 |
|
|
<br/> N_PZ_1819 AND NOT regfil_7_1 AND NOT regfil_7_3 AND NOT regfil_7_2 AND
|
| 2987 |
|
|
<br/> holding(3) AND auxcar));
|
| 2988 |
|
|
</td></tr><tr><td>
|
| 2989 |
|
|
FTCPE_holding4: FTCPE port map (holding(4),holding_T(4),clock,'0','0','1');
|
| 2990 |
|
|
<br/> holding_T(4) <= ((N_PZ_2114 AND holding(4) AND NOT regfil_4_4)
|
| 2991 |
|
|
<br/> OR (N_PZ_2114 AND NOT holding(4) AND regfil_4_4)
|
| 2992 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2993 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2994 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND
|
| 2995 |
|
|
<br/> N_PZ_1819 AND holding(4) AND NOT regfil_7_4)
|
| 2996 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 2997 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 2998 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND
|
| 2999 |
|
|
<br/> N_PZ_1819 AND NOT holding(4) AND regfil_7_4)
|
| 3000 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3001 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 3002 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3003 |
|
|
<br/> N_PZ_1819 AND holding(4) AND NOT regfil_7_4 AND regfil_7_7 AND
|
| 3004 |
|
|
<br/> NOT N_PZ_1887)
|
| 3005 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3006 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 3007 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3008 |
|
|
<br/> N_PZ_1819 AND NOT holding(4) AND regfil_7_4 AND regfil_7_7 AND
|
| 3009 |
|
|
<br/> NOT N_PZ_1887));
|
| 3010 |
|
|
</td></tr><tr><td>
|
| 3011 |
|
|
FTCPE_holding5: FTCPE port map (holding(5),holding_T(5),clock,'0','0','1');
|
| 3012 |
|
|
<br/> holding_T(5) <= ((N_PZ_2114 AND regfil_4_5 AND NOT holding(5))
|
| 3013 |
|
|
<br/> OR (N_PZ_2114 AND NOT regfil_4_5 AND holding(5))
|
| 3014 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3015 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 3016 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND
|
| 3017 |
|
|
<br/> N_PZ_1819 AND regfil_7_5 AND holding(5))
|
| 3018 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3019 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 3020 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND
|
| 3021 |
|
|
<br/> N_PZ_1819 AND NOT regfil_7_5 AND NOT holding(5))
|
| 3022 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3023 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 3024 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3025 |
|
|
<br/> N_PZ_1819 AND regfil_7_5 AND regfil_7_7 AND holding(5))
|
| 3026 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3027 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 3028 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3029 |
|
|
<br/> N_PZ_1819 AND NOT regfil_7_5 AND regfil_7_6 AND regfil_7_7 AND
|
| 3030 |
|
|
<br/> NOT holding(5)));
|
| 3031 |
|
|
</td></tr><tr><td>
|
| 3032 |
|
|
FTCPE_holding6: FTCPE port map (holding(6),holding_T(6),clock,'0','0','1');
|
| 3033 |
|
|
<br/> holding_T(6) <= ((N_PZ_2114 AND regfil_4_6 AND NOT holding(6))
|
| 3034 |
|
|
<br/> OR (N_PZ_2114 AND NOT regfil_4_6 AND holding(6))
|
| 3035 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3036 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 3037 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND
|
| 3038 |
|
|
<br/> N_PZ_1819 AND N_PZ_1887 AND NOT holding(6))
|
| 3039 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3040 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 3041 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND
|
| 3042 |
|
|
<br/> N_PZ_1819 AND regfil_7_5 AND regfil_7_6 AND NOT holding(6))
|
| 3043 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3044 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 3045 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND
|
| 3046 |
|
|
<br/> N_PZ_1819 AND regfil_7_5 AND NOT regfil_7_6 AND holding(6))
|
| 3047 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3048 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 3049 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND
|
| 3050 |
|
|
<br/> N_PZ_1819 AND NOT regfil_7_5 AND regfil_7_6 AND holding(6))
|
| 3051 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3052 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 3053 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3054 |
|
|
<br/> N_PZ_1819 AND regfil_7_5 AND regfil_7_6 AND regfil_7_7 AND
|
| 3055 |
|
|
<br/> NOT holding(6))
|
| 3056 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3057 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 3058 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3059 |
|
|
<br/> N_PZ_1819 AND regfil_7_5 AND NOT regfil_7_6 AND regfil_7_7 AND
|
| 3060 |
|
|
<br/> holding(6))
|
| 3061 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3062 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 3063 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3064 |
|
|
<br/> N_PZ_1819 AND NOT regfil_7_5 AND regfil_7_6 AND regfil_7_7 AND
|
| 3065 |
|
|
<br/> holding(6)));
|
| 3066 |
|
|
</td></tr><tr><td>
|
| 3067 |
|
|
FTCPE_holding7: FTCPE port map (holding(7),holding_T(7),clock,'0','0','1');
|
| 3068 |
|
|
<br/> holding_T(7) <= ((N_PZ_2114 AND holding(7) AND NOT regfil_4_7)
|
| 3069 |
|
|
<br/> OR (N_PZ_2114 AND NOT holding(7) AND regfil_4_7)
|
| 3070 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3071 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 3072 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3073 |
|
|
<br/> N_PZ_1819 AND regfil_7_7 AND holding(7) AND NOT N_PZ_1887)
|
| 3074 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3075 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 3076 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND
|
| 3077 |
|
|
<br/> N_PZ_1819 AND regfil_7_7 AND NOT holding(7) AND N_PZ_1887)
|
| 3078 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3079 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 3080 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND
|
| 3081 |
|
|
<br/> N_PZ_1819 AND NOT regfil_7_7 AND holding(7) AND N_PZ_1887)
|
| 3082 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3083 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 3084 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND carry AND
|
| 3085 |
|
|
<br/> N_PZ_1819 AND NOT regfil_7_7 AND NOT holding(7) AND NOT N_PZ_1887));
|
| 3086 |
|
|
</td></tr><tr><td>
|
| 3087 |
|
|
</td></tr><tr><td>
|
| 3088 |
|
|
m1/Madd__addsub0000__or0000 <= ((aluoprb(1) AND aluopra(1))
|
| 3089 |
|
|
<br/> OR (NOT N_PZ_1076 AND N_PZ_1043 AND aluopra(0)));
|
| 3090 |
|
|
</td></tr><tr><td>
|
| 3091 |
|
|
</td></tr><tr><td>
|
| 3092 |
|
|
m1/Mmux__mux0000_Result1 <= ((NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluoprb(7) AND
|
| 3093 |
|
|
<br/> NOT m1/_addsub0000(7))
|
| 3094 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluopra(7) AND
|
| 3095 |
|
|
<br/> NOT m1/_addsub0000(7))
|
| 3096 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluoprb(7) AND
|
| 3097 |
|
|
<br/> NOT N_PZ_1076 AND aluopra(7))
|
| 3098 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluoprb(7) AND
|
| 3099 |
|
|
<br/> NOT N_PZ_1043 AND aluopra(7))
|
| 3100 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluoprb(7) AND
|
| 3101 |
|
|
<br/> NOT m1/_addsub0000(2) AND aluopra(7))
|
| 3102 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluoprb(7) AND
|
| 3103 |
|
|
<br/> NOT m1/_addsub0000(3) AND aluopra(7))
|
| 3104 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluoprb(7) AND
|
| 3105 |
|
|
<br/> NOT m1/_addsub0000(4) AND aluopra(7))
|
| 3106 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluoprb(7) AND
|
| 3107 |
|
|
<br/> aluopra(7) AND NOT m1/_addsub0000(6))
|
| 3108 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluoprb(7) AND
|
| 3109 |
|
|
<br/> aluopra(7) AND NOT m1/_addsub0000(5))
|
| 3110 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND aluoprb(7) AND
|
| 3111 |
|
|
<br/> aluopra(7) AND NOT alucin)
|
| 3112 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND NOT aluoprb(7) AND
|
| 3113 |
|
|
<br/> N_PZ_1076 AND N_PZ_1043 AND m1/_addsub0000(2) AND
|
| 3114 |
|
|
<br/> m1/_addsub0000(3) AND m1/_addsub0000(4) AND aluopra(7) AND
|
| 3115 |
|
|
<br/> m1/_addsub0000(6) AND m1/_addsub0000(5) AND alucin)
|
| 3116 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND NOT alusel(2) AND N_PZ_1076 AND
|
| 3117 |
|
|
<br/> N_PZ_1043 AND m1/_addsub0000(2) AND m1/_addsub0000(3) AND
|
| 3118 |
|
|
<br/> m1/_addsub0000(4) AND NOT aluopra(7) AND m1/_addsub0000(6) AND
|
| 3119 |
|
|
<br/> m1/_addsub0000(5) AND alucin AND m1/_addsub0000(7)));
|
| 3120 |
|
|
</td></tr><tr><td>
|
| 3121 |
|
|
</td></tr><tr><td>
|
| 3122 |
|
|
m1/Mmux__mux0000_Result3 <= ((alusel(1) AND alusel(0) AND NOT alusel(2) AND
|
| 3123 |
|
|
<br/> m1/Msub__AUX_23__xor0019 AND NOT N_PZ_1092)
|
| 3124 |
|
|
<br/> OR (alusel(1) AND alusel(0) AND NOT alusel(2) AND
|
| 3125 |
|
|
<br/> m1/Msub__AUX_23__xor0019 AND NOT aluopra(7))
|
| 3126 |
|
|
<br/> OR (alusel(1) AND alusel(0) AND NOT alusel(2) AND N_PZ_1092 AND
|
| 3127 |
|
|
<br/> NOT aluopra(7) AND m1/Msub__AUX_23__xor0016)
|
| 3128 |
|
|
<br/> OR (alusel(1) AND alusel(0) AND NOT alusel(2) AND N_PZ_1092 AND
|
| 3129 |
|
|
<br/> NOT aluopra(7) AND m1/Msub__AUX_23__xor0013)
|
| 3130 |
|
|
<br/> OR (alusel(1) AND alusel(0) AND NOT alusel(2) AND N_PZ_1092 AND
|
| 3131 |
|
|
<br/> NOT aluopra(7) AND m1/Msub__AUX_23__xor0010)
|
| 3132 |
|
|
<br/> OR (alusel(1) AND alusel(0) AND NOT alusel(2) AND N_PZ_1092 AND
|
| 3133 |
|
|
<br/> NOT aluopra(7) AND NOT N_PZ_1999)
|
| 3134 |
|
|
<br/> OR (alusel(1) AND NOT alusel(2) AND NOT N_PZ_1092 AND
|
| 3135 |
|
|
<br/> NOT m1/Msub__AUX_23__xor0016 AND NOT m1/Msub__AUX_23__xor0013 AND
|
| 3136 |
|
|
<br/> NOT m1/Msub__AUX_23__xor0010 AND N_PZ_1999)
|
| 3137 |
|
|
<br/> OR (alusel(1) AND NOT alusel(2) AND NOT aluoprb(7) AND
|
| 3138 |
|
|
<br/> NOT m1/Msub__AUX_23__xor0019 AND NOT m1/Msub__AUX_23__xor0016 AND
|
| 3139 |
|
|
<br/> NOT m1/Msub__AUX_23__xor0013 AND NOT m1/Msub__AUX_23__xor0010 AND N_PZ_1999));
|
| 3140 |
|
|
</td></tr><tr><td>
|
| 3141 |
|
|
</td></tr><tr><td>
|
| 3142 |
|
|
m1/Mmux__old_resi_28_I3_Result28 <= (NOT alusel(1) AND m1/_addsub0000(4))
|
| 3143 |
|
|
<br/> XOR ((alusel(1) AND NOT alusel(2) AND m1/Msub__AUX_23__xor0010 AND
|
| 3144 |
|
|
<br/> NOT N_PZ_1999)
|
| 3145 |
|
|
<br/> OR (alusel(1) AND NOT alusel(2) AND NOT m1/Msub__AUX_23__xor0010 AND
|
| 3146 |
|
|
<br/> N_PZ_1999)
|
| 3147 |
|
|
<br/> OR (NOT alusel(1) AND alusel(2) AND
|
| 3148 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I7_Result30 AND m1/_addsub0000(4))
|
| 3149 |
|
|
<br/> OR (NOT alusel(1) AND NOT alusel(2) AND
|
| 3150 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I7_Result30 AND N_PZ_1076 AND N_PZ_1043 AND m1/_addsub0000(2) AND
|
| 3151 |
|
|
<br/> m1/_addsub0000(3)));
|
| 3152 |
|
|
</td></tr><tr><td>
|
| 3153 |
|
|
</td></tr><tr><td>
|
| 3154 |
|
|
m1/Mmux__old_resi_28_I6_Result28 <= (NOT alusel(2) AND N_PZ_1043)
|
| 3155 |
|
|
<br/> XOR ((alusel(1) AND NOT alusel(2) AND
|
| 3156 |
|
|
<br/> m1/Mmux__old_resi_28_I7_Result30 AND NOT N_PZ_1076)
|
| 3157 |
|
|
<br/> OR (alusel(1) AND NOT alusel(2) AND N_PZ_1076 AND NOT aluopra(0))
|
| 3158 |
|
|
<br/> OR (alusel(1) AND m1/Mmux__old_resi_28_I7_Result30 AND
|
| 3159 |
|
|
<br/> NOT N_PZ_1076 AND NOT N_PZ_1043)
|
| 3160 |
|
|
<br/> OR (NOT alusel(1) AND NOT alusel(2) AND
|
| 3161 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I7_Result30 AND N_PZ_1076)
|
| 3162 |
|
|
<br/> OR (NOT alusel(1) AND NOT alusel(2) AND NOT N_PZ_1076 AND aluopra(0))
|
| 3163 |
|
|
<br/> OR (NOT alusel(1) AND alusel(2) AND
|
| 3164 |
|
|
<br/> m1/Mmux__old_resi_28_I7_Result30 AND N_PZ_1076 AND N_PZ_1043));
|
| 3165 |
|
|
</td></tr><tr><td>
|
| 3166 |
|
|
</td></tr><tr><td>
|
| 3167 |
|
|
m1/Mmux__old_resi_28_I7_Result30 <= (NOT alusel(2) AND N_PZ_1076)
|
| 3168 |
|
|
<br/> XOR (alusel(0) AND NOT alusel(2) AND alucin);
|
| 3169 |
|
|
</td></tr><tr><td>
|
| 3170 |
|
|
</td></tr><tr><td>
|
| 3171 |
|
|
m1/Msub__AUX_23__xor0007 <= ((aluoprb(2) AND NOT N_PZ_1082 AND NOT aluopra(2))
|
| 3172 |
|
|
<br/> OR (NOT aluoprb(2) AND N_PZ_1082 AND aluopra(2))
|
| 3173 |
|
|
<br/> OR (N_PZ_1082 AND NOT m1/Msub__sub0000__or0001 AND N_PZ_1041)
|
| 3174 |
|
|
<br/> OR (NOT N_PZ_1082 AND m1/Msub__sub0000__or0001 AND N_PZ_1041));
|
| 3175 |
|
|
</td></tr><tr><td>
|
| 3176 |
|
|
</td></tr><tr><td>
|
| 3177 |
|
|
m1/Msub__AUX_23__xor0010 <= ((aluoprb(3) AND NOT N_PZ_1054 AND NOT aluopra(3))
|
| 3178 |
|
|
<br/> OR (NOT aluoprb(3) AND N_PZ_1054 AND aluopra(3))
|
| 3179 |
|
|
<br/> OR (N_PZ_1054 AND NOT N_PZ_1082 AND NOT m1/Msub__AUX_23__xor0007)
|
| 3180 |
|
|
<br/> OR (NOT N_PZ_1054 AND NOT N_PZ_1082 AND m1/Msub__AUX_23__xor0007));
|
| 3181 |
|
|
</td></tr><tr><td>
|
| 3182 |
|
|
</td></tr><tr><td>
|
| 3183 |
|
|
m1/Msub__AUX_23__xor0013 <= N_PZ_1038
|
| 3184 |
|
|
<br/> XOR ((NOT aluopra(4) AND N_PZ_1054)
|
| 3185 |
|
|
<br/> OR (NOT N_PZ_1054 AND m1/Msub__AUX_23__xor0010));
|
| 3186 |
|
|
</td></tr><tr><td>
|
| 3187 |
|
|
</td></tr><tr><td>
|
| 3188 |
|
|
m1/Msub__AUX_23__xor0016 <= ((aluoprb(5) AND NOT aluopra(5) AND NOT N_PZ_1059)
|
| 3189 |
|
|
<br/> OR (NOT aluoprb(5) AND aluopra(5) AND N_PZ_1059)
|
| 3190 |
|
|
<br/> OR (N_PZ_1059 AND NOT m1/Msub__AUX_23__xor0013 AND NOT N_PZ_1038)
|
| 3191 |
|
|
<br/> OR (NOT N_PZ_1059 AND m1/Msub__AUX_23__xor0013 AND NOT N_PZ_1038));
|
| 3192 |
|
|
</td></tr><tr><td>
|
| 3193 |
|
|
</td></tr><tr><td>
|
| 3194 |
|
|
m1/Msub__AUX_23__xor0019 <= N_PZ_1092
|
| 3195 |
|
|
<br/> XOR ((m1/Msub__AUX_23__xor0016 AND NOT N_PZ_1059)
|
| 3196 |
|
|
<br/> OR (N_PZ_1059 AND NOT aluopra(6)));
|
| 3197 |
|
|
</td></tr><tr><td>
|
| 3198 |
|
|
</td></tr><tr><td>
|
| 3199 |
|
|
m1/Msub__sub0000__or0001 <= ((aluoprb(1) AND NOT aluopra(1))
|
| 3200 |
|
|
<br/> OR (aluoprb(0) AND NOT N_PZ_1043 AND NOT aluopra(0)));
|
| 3201 |
|
|
</td></tr><tr><td>
|
| 3202 |
|
|
</td></tr><tr><td>
|
| 3203 |
|
|
m1/Mxor__xor0001_Mxor__xor0000__xor0001 <= ((m1/Mmux__old_resi_28_I7_Result30 AND
|
| 3204 |
|
|
<br/> m1/Mmux__old_resi_28_I6_Result28)
|
| 3205 |
|
|
<br/> OR (NOT alusel(2) AND NOT m1/Mmux__old_resi_28_I7_Result30 AND
|
| 3206 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I6_Result28)
|
| 3207 |
|
|
<br/> OR (NOT m1/Mmux__old_resi_28_I7_Result30 AND
|
| 3208 |
|
|
<br/> NOT m1/Mmux__old_resi_28_I6_Result28 AND N_PZ_1954)
|
| 3209 |
|
|
<br/> OR (alusel(1) AND alusel(2) AND
|
| 3210 |
|
|
<br/> m1/Mmux__old_resi_28_I7_Result30 AND aluopra(1))
|
| 3211 |
|
|
<br/> OR (alusel(1) AND alusel(2) AND
|
| 3212 |
|
|
<br/> m1/Mmux__old_resi_28_I6_Result28 AND aluopra(0))
|
| 3213 |
|
|
<br/> OR (alusel(1) AND alusel(2) AND aluopra(1) AND aluopra(0))
|
| 3214 |
|
|
<br/> OR (alusel(1) AND NOT alusel(0) AND alusel(2) AND
|
| 3215 |
|
|
<br/> m1/Mmux__old_resi_28_I7_Result30 AND N_PZ_1043)
|
| 3216 |
|
|
<br/> OR (alusel(1) AND NOT alusel(0) AND alusel(2) AND N_PZ_1076 AND
|
| 3217 |
|
|
<br/> m1/Mmux__old_resi_28_I6_Result28)
|
| 3218 |
|
|
<br/> OR (alusel(1) AND NOT alusel(0) AND alusel(2) AND N_PZ_1076 AND
|
| 3219 |
|
|
<br/> aluopra(1))
|
| 3220 |
|
|
<br/> OR (alusel(1) AND NOT alusel(0) AND alusel(2) AND N_PZ_1043 AND
|
| 3221 |
|
|
<br/> aluopra(0))
|
| 3222 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND alusel(2) AND
|
| 3223 |
|
|
<br/> m1/Mmux__old_resi_28_I7_Result30 AND N_PZ_1043)
|
| 3224 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND alusel(2) AND N_PZ_1076 AND
|
| 3225 |
|
|
<br/> m1/Mmux__old_resi_28_I6_Result28)
|
| 3226 |
|
|
<br/> OR (NOT alusel(1) AND alusel(0) AND alusel(2) AND N_PZ_1076 AND
|
| 3227 |
|
|
<br/> N_PZ_1043)
|
| 3228 |
|
|
<br/> OR (NOT alusel(0) AND alusel(2) AND
|
| 3229 |
|
|
<br/> m1/Mmux__old_resi_28_I7_Result30 AND NOT N_PZ_1043 AND aluopra(1))
|
| 3230 |
|
|
<br/> OR (NOT alusel(0) AND alusel(2) AND NOT N_PZ_1076 AND
|
| 3231 |
|
|
<br/> m1/Mmux__old_resi_28_I6_Result28 AND aluopra(0))
|
| 3232 |
|
|
<br/> OR (NOT alusel(0) AND alusel(2) AND aluoprb(0) AND aluoprb(1) AND
|
| 3233 |
|
|
<br/> NOT m1/Msub__sub0000__or0001)
|
| 3234 |
|
|
<br/> OR (NOT alusel(0) AND NOT m1/Mmux__old_resi_28_I7_Result30 AND
|
| 3235 |
|
|
<br/> N_PZ_1076 AND NOT m1/Mmux__old_resi_28_I6_Result28 AND N_PZ_1043));
|
| 3236 |
|
|
</td></tr><tr><td>
|
| 3237 |
|
|
</td></tr><tr><td>
|
| 3238 |
|
|
m1/_addsub0000(2) <= ((m1/Madd__addsub0000__or0000 AND N_PZ_1041)
|
| 3239 |
|
|
<br/> OR (NOT m1/Madd__addsub0000__or0000 AND NOT N_PZ_1041));
|
| 3240 |
|
|
</td></tr><tr><td>
|
| 3241 |
|
|
</td></tr><tr><td>
|
| 3242 |
|
|
m1/_addsub0000(3) <= ((m1/Madd__addsub0000__or0000 AND NOT N_PZ_1082 AND
|
| 3243 |
|
|
<br/> NOT N_PZ_1041)
|
| 3244 |
|
|
<br/> OR (NOT m1/Madd__addsub0000__or0000 AND N_PZ_1082 AND
|
| 3245 |
|
|
<br/> NOT N_PZ_1041)
|
| 3246 |
|
|
<br/> OR (aluoprb(2) AND NOT N_PZ_1082 AND aluopra(2))
|
| 3247 |
|
|
<br/> OR (NOT aluoprb(2) AND N_PZ_1082 AND NOT aluopra(2)));
|
| 3248 |
|
|
</td></tr><tr><td>
|
| 3249 |
|
|
</td></tr><tr><td>
|
| 3250 |
|
|
m1/_addsub0000(4) <= ((m1/_addsub0000(3) AND N_PZ_1054 AND N_PZ_1082)
|
| 3251 |
|
|
<br/> OR (NOT m1/_addsub0000(3) AND NOT N_PZ_1054 AND N_PZ_1082)
|
| 3252 |
|
|
<br/> OR (aluoprb(3) AND NOT N_PZ_1054 AND aluopra(3))
|
| 3253 |
|
|
<br/> OR (NOT aluoprb(3) AND N_PZ_1054 AND NOT aluopra(3)));
|
| 3254 |
|
|
</td></tr><tr><td>
|
| 3255 |
|
|
</td></tr><tr><td>
|
| 3256 |
|
|
m1/_addsub0000(5) <= ((m1/_addsub0000(4) AND N_PZ_1038 AND N_PZ_1054)
|
| 3257 |
|
|
<br/> OR (NOT m1/_addsub0000(4) AND NOT N_PZ_1038 AND N_PZ_1054)
|
| 3258 |
|
|
<br/> OR (N_PZ_1038 AND NOT N_PZ_1054 AND NOT aluoprb(4))
|
| 3259 |
|
|
<br/> OR (NOT N_PZ_1038 AND aluopra(4) AND NOT N_PZ_1054));
|
| 3260 |
|
|
</td></tr><tr><td>
|
| 3261 |
|
|
</td></tr><tr><td>
|
| 3262 |
|
|
m1/_addsub0000(6) <= ((aluoprb(5) AND aluopra(5) AND NOT N_PZ_1059)
|
| 3263 |
|
|
<br/> OR (NOT aluoprb(5) AND NOT aluopra(5) AND N_PZ_1059)
|
| 3264 |
|
|
<br/> OR (N_PZ_1059 AND N_PZ_1038 AND m1/_addsub0000(5))
|
| 3265 |
|
|
<br/> OR (NOT N_PZ_1059 AND N_PZ_1038 AND NOT m1/_addsub0000(5)));
|
| 3266 |
|
|
</td></tr><tr><td>
|
| 3267 |
|
|
</td></tr><tr><td>
|
| 3268 |
|
|
m1/_addsub0000(7) <= ((N_PZ_1092 AND N_PZ_1059 AND m1/_addsub0000(6))
|
| 3269 |
|
|
<br/> OR (N_PZ_1092 AND NOT N_PZ_1059 AND NOT aluoprb(6))
|
| 3270 |
|
|
<br/> OR (NOT N_PZ_1092 AND N_PZ_1059 AND NOT m1/_addsub0000(6))
|
| 3271 |
|
|
<br/> OR (NOT N_PZ_1092 AND NOT N_PZ_1059 AND aluopra(6)));
|
| 3272 |
|
|
</td></tr><tr><td>
|
| 3273 |
|
|
FDCPE_parity: FDCPE port map (parity,parity_D,clock,'0','0','1');
|
| 3274 |
|
|
<br/> parity_D <= ((N_PZ_1894 AND alupar)
|
| 3275 |
|
|
<br/> OR (NOT N_PZ_1894 AND parity));
|
| 3276 |
|
|
</td></tr><tr><td>
|
| 3277 |
|
|
FDCPE_pc0: FDCPE port map (pc(0),pc_D(0),clock,'0','0','1');
|
| 3278 |
|
|
<br/> pc_D(0) <= ((NOT N_PZ_1209 AND pc(0))
|
| 3279 |
|
|
<br/> OR (N_PZ_1145 AND NOT pc(0))
|
| 3280 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3281 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 3282 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND
|
| 3283 |
|
|
<br/> N_PZ_1819 AND regfil_5_0));
|
| 3284 |
|
|
</td></tr><tr><td>
|
| 3285 |
|
|
FDCPE_pc1: FDCPE port map (pc(1),pc_D(1),clock,'0','0','1');
|
| 3286 |
|
|
<br/> pc_D(1) <= ((NOT N_PZ_1209 AND pc(1))
|
| 3287 |
|
|
<br/> OR (N_PZ_1145 AND pc(0) AND NOT pc(1))
|
| 3288 |
|
|
<br/> OR (NOT reset AND NOT N_PZ_1891 AND NOT pc(0) AND pc(1))
|
| 3289 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3290 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 3291 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND
|
| 3292 |
|
|
<br/> N_PZ_1819 AND regfil_5_1));
|
| 3293 |
|
|
</td></tr><tr><td>
|
| 3294 |
|
|
FTCPE_pc2: FTCPE port map (pc(2),pc_T(2),clock,'0','0','1');
|
| 3295 |
|
|
<br/> pc_T(2) <= ((reset AND pc(2))
|
| 3296 |
|
|
<br/> OR (NOT N_PZ_1117 AND pc(0) AND pc(1))
|
| 3297 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3298 |
|
|
<br/> NOT state(0) AND data(1).PIN AND N_PZ_2033)
|
| 3299 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3300 |
|
|
<br/> NOT state(0) AND NOT N_PZ_1916 AND N_PZ_2033)
|
| 3301 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3302 |
|
|
<br/> NOT state(0) AND NOT regfil_5_2 AND N_PZ_2033)
|
| 3303 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3304 |
|
|
<br/> state(1) AND NOT state(0) AND N_PZ_2236 AND pc(0) AND pc(1) AND NOT pc(2))
|
| 3305 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3306 |
|
|
<br/> NOT state(0) AND data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 3307 |
|
|
<br/> data(6).PIN AND data(7).PIN AND pc(2))
|
| 3308 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3309 |
|
|
<br/> NOT state(0) AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 3310 |
|
|
<br/> data(7).PIN AND N_PZ_1916 AND NOT regfil_5_2 AND pc(2))
|
| 3311 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3312 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 3313 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND
|
| 3314 |
|
|
<br/> N_PZ_1819 AND regfil_5_2 AND NOT pc(2)));
|
| 3315 |
|
|
</td></tr><tr><td>
|
| 3316 |
|
|
FDCPE_pc3: FDCPE port map (pc(3),pc_D(3),clock,'0','0','1');
|
| 3317 |
|
|
<br/> pc_D(3) <= ((NOT N_PZ_1209 AND pc(3))
|
| 3318 |
|
|
<br/> OR (N_PZ_1145 AND pc(3) AND NOT N_PZ_2033)
|
| 3319 |
|
|
<br/> OR (N_PZ_1145 AND NOT pc(3) AND N_PZ_2033)
|
| 3320 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3321 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 3322 |
|
|
<br/> data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN)
|
| 3323 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3324 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 3325 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND
|
| 3326 |
|
|
<br/> N_PZ_1819 AND regfil_5_3));
|
| 3327 |
|
|
</td></tr><tr><td>
|
| 3328 |
|
|
FTCPE_pc4: FTCPE port map (pc(4),pc_T(4),clock,'0','0','1');
|
| 3329 |
|
|
<br/> pc_T(4) <= ((reset AND pc(4))
|
| 3330 |
|
|
<br/> OR (NOT N_PZ_1117 AND pc(3) AND N_PZ_2033)
|
| 3331 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3332 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(2).PIN AND data(1).PIN AND pc(3) AND
|
| 3333 |
|
|
<br/> N_PZ_2033)
|
| 3334 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3335 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(1).PIN AND NOT N_PZ_1916 AND pc(3) AND
|
| 3336 |
|
|
<br/> N_PZ_2033)
|
| 3337 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3338 |
|
|
<br/> NOT state(0) AND N_PZ_1916 AND pc(3) AND NOT regfil_5_4 AND pc(4) AND
|
| 3339 |
|
|
<br/> N_PZ_2033)
|
| 3340 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3341 |
|
|
<br/> NOT state(0) AND NOT data(4).PIN AND data(2).PIN AND data(1).PIN AND
|
| 3342 |
|
|
<br/> data(0).PIN AND data(6).PIN AND data(7).PIN AND pc(4))
|
| 3343 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3344 |
|
|
<br/> NOT state(0) AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 3345 |
|
|
<br/> data(7).PIN AND N_PZ_1916 AND NOT regfil_5_4 AND pc(4))
|
| 3346 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3347 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(2).PIN AND
|
| 3348 |
|
|
<br/> data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND NOT pc(4))
|
| 3349 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3350 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(1).PIN AND data(0).PIN AND
|
| 3351 |
|
|
<br/> data(6).PIN AND data(7).PIN AND N_PZ_1916 AND regfil_5_4 AND NOT pc(4)));
|
| 3352 |
|
|
</td></tr><tr><td>
|
| 3353 |
|
|
FDCPE_pc5: FDCPE port map (pc(5),pc_D(5),clock,'0','0','1');
|
| 3354 |
|
|
<br/> pc_D(5) <= ((NOT N_PZ_1209 AND pc(5))
|
| 3355 |
|
|
<br/> OR (N_PZ_1145 AND NOT pc(4) AND pc(5))
|
| 3356 |
|
|
<br/> OR (N_PZ_1145 AND NOT pc(3) AND pc(4) AND pc(5))
|
| 3357 |
|
|
<br/> OR (N_PZ_1145 AND pc(3) AND pc(4) AND N_PZ_2033 AND NOT pc(5))
|
| 3358 |
|
|
<br/> OR (N_PZ_1145 AND pc(3) AND pc(4) AND NOT N_PZ_2033 AND pc(5))
|
| 3359 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3360 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 3361 |
|
|
<br/> data(0).PIN AND data(6).PIN AND data(7).PIN AND data(5).PIN)
|
| 3362 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3363 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 3364 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND
|
| 3365 |
|
|
<br/> N_PZ_1819 AND regfil_5_5));
|
| 3366 |
|
|
</td></tr><tr><td>
|
| 3367 |
|
|
FTCPE_pc6: FTCPE port map (pc(6),pc_T(6),clock,'0','0','1');
|
| 3368 |
|
|
<br/> pc_T(6) <= ((reset AND pc(6))
|
| 3369 |
|
|
<br/> OR (NOT N_PZ_1117 AND pc(3) AND pc(4) AND N_PZ_2033 AND pc(5))
|
| 3370 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3371 |
|
|
<br/> NOT state(0) AND data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 3372 |
|
|
<br/> data(6).PIN AND data(7).PIN AND pc(6))
|
| 3373 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3374 |
|
|
<br/> NOT state(0) AND NOT N_PZ_1916 AND pc(3) AND pc(6) AND pc(4) AND N_PZ_2033 AND
|
| 3375 |
|
|
<br/> pc(5))
|
| 3376 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3377 |
|
|
<br/> NOT state(0) AND pc(3) AND NOT regfil_5_6 AND pc(6) AND pc(4) AND N_PZ_2033 AND
|
| 3378 |
|
|
<br/> pc(5))
|
| 3379 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3380 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(2).PIN AND data(1).PIN AND pc(3) AND
|
| 3381 |
|
|
<br/> pc(4) AND N_PZ_2033 AND pc(5))
|
| 3382 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3383 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(1).PIN AND NOT N_PZ_1916 AND pc(3) AND
|
| 3384 |
|
|
<br/> pc(4) AND N_PZ_2033 AND pc(5))
|
| 3385 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3386 |
|
|
<br/> NOT state(0) AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 3387 |
|
|
<br/> data(7).PIN AND N_PZ_1916 AND NOT regfil_5_6 AND pc(6))
|
| 3388 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3389 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 3390 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND
|
| 3391 |
|
|
<br/> N_PZ_1819 AND regfil_5_6 AND NOT pc(6)));
|
| 3392 |
|
|
</td></tr><tr><td>
|
| 3393 |
|
|
FDCPE_pc7: FDCPE port map (pc(7),pc_D(7),clock,'0','0','1');
|
| 3394 |
|
|
<br/> pc_D(7) <= ((NOT N_PZ_1209 AND pc(7))
|
| 3395 |
|
|
<br/> OR (pc(7) AND N_PZ_1145 AND NOT N_PZ_2021)
|
| 3396 |
|
|
<br/> OR (N_PZ_1145 AND NOT N_PZ_2021 AND pc(3) AND pc(6) AND pc(4) AND
|
| 3397 |
|
|
<br/> N_PZ_2033 AND pc(5))
|
| 3398 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3399 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 3400 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND
|
| 3401 |
|
|
<br/> N_PZ_1819 AND regfil_5_7));
|
| 3402 |
|
|
</td></tr><tr><td>
|
| 3403 |
|
|
FTCPE_pc8: FTCPE port map (pc(8),pc_T(8),clock,'0','0','1');
|
| 3404 |
|
|
<br/> pc_T(8) <= ((reset AND pc(8))
|
| 3405 |
|
|
<br/> OR (NOT N_PZ_1117 AND N_PZ_2021)
|
| 3406 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3407 |
|
|
<br/> NOT state(0) AND data(1).PIN AND N_PZ_2021 AND pc(8))
|
| 3408 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3409 |
|
|
<br/> NOT state(0) AND NOT N_PZ_1916 AND N_PZ_2021 AND pc(8))
|
| 3410 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3411 |
|
|
<br/> NOT state(0) AND N_PZ_2021 AND NOT regfil_4_0 AND pc(8))
|
| 3412 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3413 |
|
|
<br/> state(1) AND NOT state(0) AND N_PZ_2236 AND N_PZ_2021 AND NOT pc(8))
|
| 3414 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3415 |
|
|
<br/> NOT state(0) AND data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 3416 |
|
|
<br/> data(6).PIN AND data(7).PIN AND pc(8))
|
| 3417 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3418 |
|
|
<br/> NOT state(0) AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 3419 |
|
|
<br/> data(7).PIN AND N_PZ_1916 AND NOT regfil_4_0 AND pc(8))
|
| 3420 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3421 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 3422 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND
|
| 3423 |
|
|
<br/> N_PZ_1819 AND regfil_4_0 AND NOT pc(8)));
|
| 3424 |
|
|
</td></tr><tr><td>
|
| 3425 |
|
|
FDCPE_pc9: FDCPE port map (pc(9),pc_D(9),clock,'0','0','1');
|
| 3426 |
|
|
<br/> pc_D(9) <= ((NOT N_PZ_1209 AND pc(9))
|
| 3427 |
|
|
<br/> OR (N_PZ_1145 AND NOT pc(8) AND pc(9))
|
| 3428 |
|
|
<br/> OR (N_PZ_1145 AND N_PZ_2021 AND pc(8) AND NOT pc(9))
|
| 3429 |
|
|
<br/> OR (N_PZ_1145 AND NOT N_PZ_2021 AND pc(8) AND pc(9))
|
| 3430 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3431 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 3432 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND
|
| 3433 |
|
|
<br/> N_PZ_1819 AND regfil_4_1));
|
| 3434 |
|
|
</td></tr><tr><td>
|
| 3435 |
|
|
FTCPE_pc10: FTCPE port map (pc(10),pc_T(10),clock,'0','0','1');
|
| 3436 |
|
|
<br/> pc_T(10) <= ((reset AND pc(10))
|
| 3437 |
|
|
<br/> OR (NOT N_PZ_1117 AND N_PZ_2021 AND pc(8) AND pc(9))
|
| 3438 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3439 |
|
|
<br/> NOT state(0) AND NOT N_PZ_1916 AND N_PZ_2021 AND pc(10) AND pc(8) AND pc(9))
|
| 3440 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3441 |
|
|
<br/> NOT state(0) AND N_PZ_2021 AND NOT regfil_4_2 AND pc(10) AND pc(8) AND
|
| 3442 |
|
|
<br/> pc(9))
|
| 3443 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3444 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(2).PIN AND data(1).PIN AND
|
| 3445 |
|
|
<br/> N_PZ_2021 AND pc(8) AND pc(9))
|
| 3446 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3447 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(1).PIN AND NOT N_PZ_1916 AND N_PZ_2021 AND
|
| 3448 |
|
|
<br/> pc(8) AND pc(9))
|
| 3449 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3450 |
|
|
<br/> NOT state(0) AND data(2).PIN AND data(1).PIN AND data(0).PIN AND
|
| 3451 |
|
|
<br/> data(6).PIN AND data(7).PIN AND pc(10))
|
| 3452 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 3453 |
|
|
<br/> NOT state(0) AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 3454 |
|
|
<br/> data(7).PIN AND N_PZ_1916 AND NOT regfil_4_2 AND pc(10))
|
| 3455 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3456 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 3457 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND
|
| 3458 |
|
|
<br/> N_PZ_1819 AND regfil_4_2 AND NOT pc(10)));
|
| 3459 |
|
|
</td></tr><tr><td>
|
| 3460 |
|
|
FDCPE_pc11: FDCPE port map (pc(11),pc_D(11),clock,'0','0','1');
|
| 3461 |
|
|
<br/> pc_D(11) <= ((NOT N_PZ_1209 AND pc(11))
|
| 3462 |
|
|
<br/> OR (NOT reset AND pc(11) AND NOT N_PZ_1223 AND NOT N_PZ_1891)
|
| 3463 |
|
|
<br/> OR (NOT reset AND N_PZ_1209 AND N_PZ_2021 AND pc(10) AND pc(8) AND
|
| 3464 |
|
|
<br/> pc(9) AND NOT N_PZ_1223 AND NOT N_PZ_1891)
|
| 3465 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND NOT data(1).PIN AND data(0).PIN AND
|
| 3466 |
|
|
<br/> data(6).PIN AND data(7).PIN AND N_PZ_1209 AND N_PZ_1916 AND
|
| 3467 |
|
|
<br/> regfil_4_3));
|
| 3468 |
|
|
</td></tr><tr><td>
|
| 3469 |
|
|
FDCPE_pc12: FDCPE port map (pc(12),pc_D(12),clock,'0','0','1');
|
| 3470 |
|
|
<br/> pc_D(12) <= ((NOT N_PZ_1209 AND pc(12))
|
| 3471 |
|
|
<br/> OR (NOT reset AND NOT N_PZ_1223 AND NOT N_PZ_1891 AND pc(12))
|
| 3472 |
|
|
<br/> OR (NOT reset AND N_PZ_1209 AND N_PZ_1223 AND NOT N_PZ_1891 AND
|
| 3473 |
|
|
<br/> NOT pc(12))
|
| 3474 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 3475 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND
|
| 3476 |
|
|
<br/> N_PZ_1209 AND N_PZ_1819 AND regfil_4_4));
|
| 3477 |
|
|
</td></tr><tr><td>
|
| 3478 |
|
|
FDCPE_pc13: FDCPE port map (pc(13),pc_D(13),clock,'0','0','1');
|
| 3479 |
|
|
<br/> pc_D(13) <= ((pc(13) AND NOT N_PZ_2067)
|
| 3480 |
|
|
<br/> OR (N_PZ_1145 AND N_PZ_1223 AND pc(12) AND NOT pc(13))
|
| 3481 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3482 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 3483 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND
|
| 3484 |
|
|
<br/> N_PZ_1819 AND regfil_4_5));
|
| 3485 |
|
|
</td></tr><tr><td>
|
| 3486 |
|
|
FDCPE_pc14: FDCPE port map (pc(14),pc_D(14),clock,'0','0','1');
|
| 3487 |
|
|
<br/> pc_D(14) <= ((NOT N_PZ_2067 AND pc(14))
|
| 3488 |
|
|
<br/> OR (N_PZ_1145 AND NOT pc(13) AND pc(14))
|
| 3489 |
|
|
<br/> OR (N_PZ_1145 AND N_PZ_1223 AND pc(12) AND pc(13) AND
|
| 3490 |
|
|
<br/> NOT pc(14))
|
| 3491 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3492 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 3493 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND
|
| 3494 |
|
|
<br/> N_PZ_1819 AND regfil_4_6));
|
| 3495 |
|
|
</td></tr><tr><td>
|
| 3496 |
|
|
FDCPE_pc15: FDCPE port map (pc(15),pc_D(15),clock,'0','0','1');
|
| 3497 |
|
|
<br/> pc_D(15) <= ((NOT N_PZ_2067 AND pc(15))
|
| 3498 |
|
|
<br/> OR (N_PZ_1145 AND NOT pc(13) AND pc(15))
|
| 3499 |
|
|
<br/> OR (N_PZ_1145 AND NOT pc(14) AND pc(15))
|
| 3500 |
|
|
<br/> OR (N_PZ_1145 AND N_PZ_1223 AND pc(12) AND pc(13) AND
|
| 3501 |
|
|
<br/> pc(14) AND NOT pc(15))
|
| 3502 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3503 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 3504 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND data(7).PIN AND
|
| 3505 |
|
|
<br/> N_PZ_1819 AND regfil_4_7));
|
| 3506 |
|
|
</td></tr><tr><td>
|
| 3507 |
|
|
FTCPE_regd0: FTCPE port map (regd(0),regd_T(0),clock,'0','0','1');
|
| 3508 |
|
|
<br/> regd_T(0) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3509 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND NOT regd(0))
|
| 3510 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3511 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(6).PIN AND
|
| 3512 |
|
|
<br/> NOT data(7).PIN AND NOT regd(0))
|
| 3513 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3514 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 3515 |
|
|
<br/> NOT data(1).PIN AND NOT data(7).PIN AND NOT regd(0))
|
| 3516 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3517 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 3518 |
|
|
<br/> NOT data(1).PIN AND NOT data(7).PIN AND regd(0))
|
| 3519 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3520 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(6).PIN AND
|
| 3521 |
|
|
<br/> NOT data(7).PIN AND NOT _cmp_eq0004 AND regd(0))
|
| 3522 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3523 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(1).PIN AND
|
| 3524 |
|
|
<br/> NOT data(0).PIN AND NOT data(7).PIN AND NOT regd(0) AND NOT N_PZ_1916)
|
| 3525 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3526 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 3527 |
|
|
<br/> NOT data(0).PIN AND NOT data(7).PIN AND NOT _cmp_eq0004 AND regd(0)));
|
| 3528 |
|
|
</td></tr><tr><td>
|
| 3529 |
|
|
FTCPE_regd1: FTCPE port map (regd(1),regd_T(1),clock,'0','0','1');
|
| 3530 |
|
|
<br/> regd_T(1) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3531 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND NOT regd(1))
|
| 3532 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3533 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(2).PIN AND
|
| 3534 |
|
|
<br/> NOT data(1).PIN AND NOT data(6).PIN AND NOT regd(1))
|
| 3535 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3536 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(2).PIN AND
|
| 3537 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT regd(1))
|
| 3538 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3539 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(6).PIN AND
|
| 3540 |
|
|
<br/> NOT data(7).PIN AND NOT _cmp_eq0004 AND NOT regd(1))
|
| 3541 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3542 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND data(6).PIN AND
|
| 3543 |
|
|
<br/> NOT data(7).PIN AND NOT _cmp_eq0004 AND regd(1))
|
| 3544 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3545 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND data(2).PIN AND
|
| 3546 |
|
|
<br/> NOT data(1).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND regd(1))
|
| 3547 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3548 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND data(2).PIN AND
|
| 3549 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND regd(1))
|
| 3550 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3551 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 3552 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT N_PZ_1819 AND NOT regd(1)));
|
| 3553 |
|
|
</td></tr><tr><td>
|
| 3554 |
|
|
FTCPE_regd2: FTCPE port map (regd(2),regd_T(2),clock,'0','0','1');
|
| 3555 |
|
|
<br/> regd_T(2) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3556 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND NOT regd(2))
|
| 3557 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3558 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND
|
| 3559 |
|
|
<br/> NOT data(6).PIN AND data(5).PIN AND NOT regd(2))
|
| 3560 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3561 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND NOT data(0).PIN AND
|
| 3562 |
|
|
<br/> NOT data(6).PIN AND data(5).PIN AND NOT regd(2))
|
| 3563 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3564 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 3565 |
|
|
<br/> data(5).PIN AND NOT regd(2) AND NOT _cmp_eq0004)
|
| 3566 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3567 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 3568 |
|
|
<br/> NOT data(5).PIN AND regd(2) AND NOT _cmp_eq0004)
|
| 3569 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3570 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND
|
| 3571 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND NOT data(5).PIN AND regd(2))
|
| 3572 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3573 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND NOT data(0).PIN AND
|
| 3574 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN AND NOT data(5).PIN AND regd(2))
|
| 3575 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3576 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 3577 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT regd(2) AND NOT N_PZ_1819));
|
| 3578 |
|
|
</td></tr><tr><td>
|
| 3579 |
|
|
FTCPE_regfil_0_0: FTCPE port map (regfil_0_0,regfil_0_0_T,clock,'0','0','1');
|
| 3580 |
|
|
<br/> regfil_0_0_T <= ((NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1268 AND
|
| 3581 |
|
|
<br/> regfil_0_0)
|
| 3582 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND NOT N_PZ_1268 AND
|
| 3583 |
|
|
<br/> N_PZ_1996 AND NOT regfil_0_0)
|
| 3584 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3585 |
|
|
<br/> state(1) AND NOT state(0) AND addrhold(7) AND NOT regfil_0_0)
|
| 3586 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3587 |
|
|
<br/> state(1) AND NOT state(0) AND NOT addrhold(7) AND regfil_0_0)
|
| 3588 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3589 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND
|
| 3590 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3591 |
|
|
<br/> NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1 AND
|
| 3592 |
|
|
<br/> regfil_1_3 AND regfil_1_6 AND regfil_1_4 AND regfil_1_5 AND
|
| 3593 |
|
|
<br/> regfil_1_7));
|
| 3594 |
|
|
</td></tr><tr><td>
|
| 3595 |
|
|
FTCPE_regfil_0_1: FTCPE port map (regfil_0_1,regfil_0_1_T,clock,'0','0','1');
|
| 3596 |
|
|
<br/> regfil_0_1_T <= ((NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1262 AND
|
| 3597 |
|
|
<br/> NOT regfil_0_1)
|
| 3598 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1946 AND
|
| 3599 |
|
|
<br/> regfil_0_1)
|
| 3600 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3601 |
|
|
<br/> state(1) AND NOT state(0) AND addrhold(8) AND NOT regfil_0_1)
|
| 3602 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3603 |
|
|
<br/> state(1) AND NOT state(0) AND NOT addrhold(8) AND regfil_0_1)
|
| 3604 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3605 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND
|
| 3606 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3607 |
|
|
<br/> NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1 AND
|
| 3608 |
|
|
<br/> regfil_1_3 AND regfil_1_6 AND regfil_1_4 AND regfil_1_5 AND
|
| 3609 |
|
|
<br/> regfil_1_7 AND regfil_0_0));
|
| 3610 |
|
|
</td></tr><tr><td>
|
| 3611 |
|
|
FTCPE_regfil_0_2: FTCPE port map (regfil_0_2,regfil_0_2_T,clock,'0','0','1');
|
| 3612 |
|
|
<br/> regfil_0_2_T <= ((NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1944 AND
|
| 3613 |
|
|
<br/> NOT regfil_0_2)
|
| 3614 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND regfil_0_2 AND
|
| 3615 |
|
|
<br/> N_PZ_1945)
|
| 3616 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3617 |
|
|
<br/> state(1) AND NOT state(0) AND addrhold(9) AND NOT regfil_0_2)
|
| 3618 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3619 |
|
|
<br/> state(1) AND NOT state(0) AND NOT addrhold(9) AND regfil_0_2)
|
| 3620 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3621 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND
|
| 3622 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3623 |
|
|
<br/> NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1 AND
|
| 3624 |
|
|
<br/> regfil_0_1 AND regfil_1_3 AND regfil_1_6 AND regfil_1_4 AND
|
| 3625 |
|
|
<br/> regfil_1_5 AND regfil_1_7 AND regfil_0_0));
|
| 3626 |
|
|
</td></tr><tr><td>
|
| 3627 |
|
|
FTCPE_regfil_0_3: FTCPE port map (regfil_0_3,regfil_0_3_T,clock,'0','0','1');
|
| 3628 |
|
|
<br/> regfil_0_3_T <= ((NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1943 AND
|
| 3629 |
|
|
<br/> NOT regfil_0_3)
|
| 3630 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND regfil_0_3 AND
|
| 3631 |
|
|
<br/> N_PZ_2180)
|
| 3632 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3633 |
|
|
<br/> state(1) AND NOT state(0) AND addrhold(10) AND NOT regfil_0_3)
|
| 3634 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3635 |
|
|
<br/> state(1) AND NOT state(0) AND NOT addrhold(10) AND regfil_0_3)
|
| 3636 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3637 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND
|
| 3638 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3639 |
|
|
<br/> NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1 AND
|
| 3640 |
|
|
<br/> regfil_0_1 AND regfil_1_3 AND regfil_1_6 AND regfil_1_4 AND
|
| 3641 |
|
|
<br/> regfil_1_5 AND regfil_1_7 AND regfil_0_2 AND regfil_0_0));
|
| 3642 |
|
|
</td></tr><tr><td>
|
| 3643 |
|
|
FTCPE_regfil_0_4: FTCPE port map (regfil_0_4,regfil_0_4_T,clock,'0','0','1');
|
| 3644 |
|
|
<br/> regfil_0_4_T <= ((NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_2181 AND
|
| 3645 |
|
|
<br/> regfil_0_4)
|
| 3646 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1996 AND
|
| 3647 |
|
|
<br/> NOT N_PZ_2181 AND NOT regfil_0_4)
|
| 3648 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3649 |
|
|
<br/> state(1) AND NOT state(0) AND addrhold(11) AND NOT regfil_0_4)
|
| 3650 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3651 |
|
|
<br/> state(1) AND NOT state(0) AND NOT addrhold(11) AND regfil_0_4)
|
| 3652 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3653 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND
|
| 3654 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3655 |
|
|
<br/> NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1 AND
|
| 3656 |
|
|
<br/> regfil_0_1 AND regfil_1_3 AND regfil_1_6 AND regfil_1_4 AND
|
| 3657 |
|
|
<br/> regfil_0_3 AND regfil_1_5 AND regfil_1_7 AND regfil_0_2 AND
|
| 3658 |
|
|
<br/> regfil_0_0));
|
| 3659 |
|
|
</td></tr><tr><td>
|
| 3660 |
|
|
FTCPE_regfil_0_5: FTCPE port map (regfil_0_5,regfil_0_5_T,clock,'0','0','1');
|
| 3661 |
|
|
<br/> regfil_0_5_T <= ((N_PZ_1799)
|
| 3662 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1265 AND
|
| 3663 |
|
|
<br/> NOT regfil_0_5)
|
| 3664 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_2000 AND
|
| 3665 |
|
|
<br/> regfil_0_5)
|
| 3666 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3667 |
|
|
<br/> state(1) AND NOT state(0) AND addrhold(12) AND NOT regfil_0_5)
|
| 3668 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3669 |
|
|
<br/> state(1) AND NOT state(0) AND NOT addrhold(12) AND regfil_0_5));
|
| 3670 |
|
|
</td></tr><tr><td>
|
| 3671 |
|
|
FTCPE_regfil_0_6: FTCPE port map (regfil_0_6,regfil_0_6_T,clock,'0','0','1');
|
| 3672 |
|
|
<br/> regfil_0_6_T <= ((regfil_0_5 AND N_PZ_1799)
|
| 3673 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND regfil_0_6 AND
|
| 3674 |
|
|
<br/> N_PZ_2106)
|
| 3675 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND NOT regfil_0_6 AND
|
| 3676 |
|
|
<br/> N_PZ_1888)
|
| 3677 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3678 |
|
|
<br/> state(1) AND NOT state(0) AND addrhold(13) AND NOT regfil_0_6)
|
| 3679 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3680 |
|
|
<br/> state(1) AND NOT state(0) AND NOT addrhold(13) AND regfil_0_6)
|
| 3681 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 3682 |
|
|
<br/> NOT state(1) AND state(0) AND data(6).PIN AND NOT regd(2) AND NOT regd(1) AND
|
| 3683 |
|
|
<br/> NOT regd(0) AND NOT regfil_0_6));
|
| 3684 |
|
|
</td></tr><tr><td>
|
| 3685 |
|
|
FTCPE_regfil_0_7: FTCPE port map (regfil_0_7,regfil_0_7_T,clock,'0','0','1');
|
| 3686 |
|
|
<br/> regfil_0_7_T <= ((regfil_0_5 AND N_PZ_1799 AND regfil_0_6)
|
| 3687 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1266 AND
|
| 3688 |
|
|
<br/> NOT regfil_0_7)
|
| 3689 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_2001 AND
|
| 3690 |
|
|
<br/> regfil_0_7)
|
| 3691 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3692 |
|
|
<br/> state(1) AND NOT state(0) AND addrhold(14) AND NOT regfil_0_7)
|
| 3693 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3694 |
|
|
<br/> state(1) AND NOT state(0) AND NOT addrhold(14) AND regfil_0_7));
|
| 3695 |
|
|
</td></tr><tr><td>
|
| 3696 |
|
|
FTCPE_regfil_1_0: FTCPE port map (regfil_1_0,regfil_1_0_T,clock,'0','0','1');
|
| 3697 |
|
|
<br/> regfil_1_0_T <= ((NOT regd(2) AND NOT regd(1) AND regd(0) AND regfil_1_0 AND
|
| 3698 |
|
|
<br/> N_PZ_1268)
|
| 3699 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND NOT regfil_1_0 AND
|
| 3700 |
|
|
<br/> NOT N_PZ_1268 AND N_PZ_1996)
|
| 3701 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3702 |
|
|
<br/> state(1) AND NOT state(0) AND addrhold(0) AND NOT regfil_1_0)
|
| 3703 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3704 |
|
|
<br/> state(1) AND NOT state(0) AND NOT addrhold(0) AND regfil_1_0)
|
| 3705 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3706 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND
|
| 3707 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3708 |
|
|
<br/> NOT data(5).PIN));
|
| 3709 |
|
|
</td></tr><tr><td>
|
| 3710 |
|
|
FTCPE_regfil_1_1: FTCPE port map (regfil_1_1,regfil_1_1_T,clock,'0','0','1');
|
| 3711 |
|
|
<br/> regfil_1_1_T <= ((NOT regd(2) AND NOT regd(1) AND regd(0) AND regfil_1_1 AND
|
| 3712 |
|
|
<br/> N_PZ_1946)
|
| 3713 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND NOT regfil_1_1 AND
|
| 3714 |
|
|
<br/> N_PZ_1262)
|
| 3715 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3716 |
|
|
<br/> state(1) AND NOT state(0) AND addrhold(1) AND NOT regfil_1_1)
|
| 3717 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3718 |
|
|
<br/> state(1) AND NOT state(0) AND NOT addrhold(1) AND regfil_1_1)
|
| 3719 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3720 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND
|
| 3721 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3722 |
|
|
<br/> NOT data(5).PIN AND regfil_1_0));
|
| 3723 |
|
|
</td></tr><tr><td>
|
| 3724 |
|
|
FTCPE_regfil_1_2: FTCPE port map (regfil_1_2,regfil_1_2_T,clock,'0','0','1');
|
| 3725 |
|
|
<br/> regfil_1_2_T <= ((NOT regd(2) AND NOT regd(1) AND regd(0) AND regfil_1_2 AND
|
| 3726 |
|
|
<br/> N_PZ_1945)
|
| 3727 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND NOT regfil_1_2 AND
|
| 3728 |
|
|
<br/> N_PZ_1944)
|
| 3729 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3730 |
|
|
<br/> state(1) AND NOT state(0) AND addrhold(2) AND NOT regfil_1_2)
|
| 3731 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3732 |
|
|
<br/> state(1) AND NOT state(0) AND NOT addrhold(2) AND regfil_1_2)
|
| 3733 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3734 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND
|
| 3735 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3736 |
|
|
<br/> NOT data(5).PIN AND regfil_1_0 AND regfil_1_1));
|
| 3737 |
|
|
</td></tr><tr><td>
|
| 3738 |
|
|
FTCPE_regfil_1_3: FTCPE port map (regfil_1_3,regfil_1_3_T,clock,'0','0','1');
|
| 3739 |
|
|
<br/> regfil_1_3_T <= ((NOT regd(2) AND NOT regd(1) AND regd(0) AND regfil_1_3 AND
|
| 3740 |
|
|
<br/> N_PZ_2180)
|
| 3741 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND NOT regfil_1_3 AND
|
| 3742 |
|
|
<br/> N_PZ_1943)
|
| 3743 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3744 |
|
|
<br/> state(1) AND NOT state(0) AND addrhold(3) AND NOT regfil_1_3)
|
| 3745 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3746 |
|
|
<br/> state(1) AND NOT state(0) AND NOT addrhold(3) AND regfil_1_3)
|
| 3747 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3748 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND
|
| 3749 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3750 |
|
|
<br/> NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1));
|
| 3751 |
|
|
</td></tr><tr><td>
|
| 3752 |
|
|
FTCPE_regfil_1_4: FTCPE port map (regfil_1_4,regfil_1_4_T,clock,'0','0','1');
|
| 3753 |
|
|
<br/> regfil_1_4_T <= ((NOT regd(2) AND NOT regd(1) AND regd(0) AND regfil_1_4 AND
|
| 3754 |
|
|
<br/> N_PZ_2181)
|
| 3755 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND N_PZ_1996 AND
|
| 3756 |
|
|
<br/> NOT regfil_1_4 AND NOT N_PZ_2181)
|
| 3757 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3758 |
|
|
<br/> state(1) AND NOT state(0) AND addrhold(4) AND NOT regfil_1_4)
|
| 3759 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3760 |
|
|
<br/> state(1) AND NOT state(0) AND NOT addrhold(4) AND regfil_1_4)
|
| 3761 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3762 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND
|
| 3763 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3764 |
|
|
<br/> NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1 AND
|
| 3765 |
|
|
<br/> regfil_1_3));
|
| 3766 |
|
|
</td></tr><tr><td>
|
| 3767 |
|
|
FTCPE_regfil_1_5: FTCPE port map (regfil_1_5,regfil_1_5_T,clock,'0','0','1');
|
| 3768 |
|
|
<br/> regfil_1_5_T <= ((NOT regd(2) AND NOT regd(1) AND regd(0) AND N_PZ_1265 AND
|
| 3769 |
|
|
<br/> NOT regfil_1_5)
|
| 3770 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND regfil_1_5 AND
|
| 3771 |
|
|
<br/> N_PZ_2000)
|
| 3772 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3773 |
|
|
<br/> state(1) AND NOT state(0) AND addrhold(5) AND NOT regfil_1_5)
|
| 3774 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3775 |
|
|
<br/> state(1) AND NOT state(0) AND NOT addrhold(5) AND regfil_1_5)
|
| 3776 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3777 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND
|
| 3778 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3779 |
|
|
<br/> NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1 AND
|
| 3780 |
|
|
<br/> regfil_1_3 AND regfil_1_4));
|
| 3781 |
|
|
</td></tr><tr><td>
|
| 3782 |
|
|
FTCPE_regfil_1_6: FTCPE port map (regfil_1_6,regfil_1_6_T,clock,'0','0','1');
|
| 3783 |
|
|
<br/> regfil_1_6_T <= ((NOT state(3) AND state(1) AND NOT N_PZ_1066 AND NOT state(0) AND
|
| 3784 |
|
|
<br/> NOT N_PZ_1209 AND addrhold(6) AND NOT regfil_1_6)
|
| 3785 |
|
|
<br/> OR (NOT state(3) AND state(1) AND NOT N_PZ_1066 AND NOT state(0) AND
|
| 3786 |
|
|
<br/> NOT N_PZ_1209 AND NOT addrhold(6) AND regfil_1_6)
|
| 3787 |
|
|
<br/> OR (state(3) AND state(2) AND NOT state(4) AND state(0) AND
|
| 3788 |
|
|
<br/> NOT N_PZ_1209 AND NOT regd(2) AND NOT regd(1) AND regd(0) AND regfil_1_6 AND
|
| 3789 |
|
|
<br/> NOT alures(6))
|
| 3790 |
|
|
<br/> OR (state(3) AND state(2) AND NOT state(4) AND state(0) AND
|
| 3791 |
|
|
<br/> NOT N_PZ_1209 AND NOT regd(2) AND NOT regd(1) AND regd(0) AND NOT regfil_1_6 AND
|
| 3792 |
|
|
<br/> alures(6))
|
| 3793 |
|
|
<br/> OR (NOT state(3) AND state(2) AND NOT state(4) AND NOT state(1) AND
|
| 3794 |
|
|
<br/> state(0) AND data(6).PIN AND NOT N_PZ_1209 AND NOT regd(2) AND NOT regd(1) AND
|
| 3795 |
|
|
<br/> regd(0) AND NOT regfil_1_6)
|
| 3796 |
|
|
<br/> OR (NOT state(3) AND state(2) AND NOT state(4) AND NOT state(1) AND
|
| 3797 |
|
|
<br/> state(0) AND NOT data(6).PIN AND NOT N_PZ_1209 AND NOT regd(2) AND NOT regd(1) AND
|
| 3798 |
|
|
<br/> regd(0) AND regfil_1_6)
|
| 3799 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 3800 |
|
|
<br/> N_PZ_1209 AND NOT regd(2) AND NOT _cmp_eq0004 AND NOT regd(1) AND regd(0) AND
|
| 3801 |
|
|
<br/> NOT N_PZ_1373 AND regfil_1_6 AND _COND_18(6))
|
| 3802 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 3803 |
|
|
<br/> N_PZ_1209 AND NOT regd(2) AND NOT _cmp_eq0004 AND NOT regd(1) AND regd(0) AND
|
| 3804 |
|
|
<br/> NOT N_PZ_1373 AND NOT regfil_1_6 AND NOT _COND_18(6))
|
| 3805 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND
|
| 3806 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3807 |
|
|
<br/> NOT data(5).PIN AND N_PZ_1209 AND regfil_1_0 AND regfil_1_2 AND
|
| 3808 |
|
|
<br/> regfil_1_1 AND regfil_1_3 AND regfil_1_4 AND regfil_1_5));
|
| 3809 |
|
|
</td></tr><tr><td>
|
| 3810 |
|
|
FTCPE_regfil_1_7: FTCPE port map (regfil_1_7,regfil_1_7_T,clock,'0','0','1');
|
| 3811 |
|
|
<br/> regfil_1_7_T <= ((NOT regd(2) AND NOT regd(1) AND regd(0) AND regfil_1_7 AND
|
| 3812 |
|
|
<br/> N_PZ_2001)
|
| 3813 |
|
|
<br/> OR (NOT regd(2) AND NOT regd(1) AND regd(0) AND NOT regfil_1_7 AND
|
| 3814 |
|
|
<br/> N_PZ_1266)
|
| 3815 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3816 |
|
|
<br/> state(1) AND NOT state(0) AND addrhold(7) AND NOT regfil_1_7)
|
| 3817 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3818 |
|
|
<br/> state(1) AND NOT state(0) AND NOT addrhold(7) AND regfil_1_7)
|
| 3819 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3820 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(2).PIN AND
|
| 3821 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 3822 |
|
|
<br/> NOT data(5).PIN AND regfil_1_0 AND regfil_1_2 AND regfil_1_1 AND
|
| 3823 |
|
|
<br/> regfil_1_3 AND regfil_1_6 AND regfil_1_4 AND regfil_1_5));
|
| 3824 |
|
|
</td></tr><tr><td>
|
| 3825 |
|
|
FTCPE_regfil_2_0: FTCPE port map (regfil_2_0,regfil_2_0_T,clock,'0','0','1');
|
| 3826 |
|
|
<br/> regfil_2_0_T <= ((holding(0) AND NOT regfil_2_0 AND N_PZ_2114)
|
| 3827 |
|
|
<br/> OR (NOT holding(0) AND regfil_2_0 AND N_PZ_2114)
|
| 3828 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1268 AND
|
| 3829 |
|
|
<br/> regfil_2_0)
|
| 3830 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND NOT N_PZ_1268 AND
|
| 3831 |
|
|
<br/> N_PZ_1996 AND NOT regfil_2_0)
|
| 3832 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3833 |
|
|
<br/> state(1) AND state(0) AND addrhold(7) AND NOT regfil_2_0)
|
| 3834 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3835 |
|
|
<br/> state(1) AND state(0) AND NOT addrhold(7) AND regfil_2_0)
|
| 3836 |
|
|
<br/> OR (regfil_3_0 AND regfil_3_1 AND regfil_3_2 AND
|
| 3837 |
|
|
<br/> regfil_3_3 AND regfil_3_4 AND regfil_3_5 AND N_PZ_1941 AND
|
| 3838 |
|
|
<br/> regfil_3_6 AND regfil_3_7));
|
| 3839 |
|
|
</td></tr><tr><td>
|
| 3840 |
|
|
FTCPE_regfil_2_1: FTCPE port map (regfil_2_1,regfil_2_1_T,clock,'0','0','1');
|
| 3841 |
|
|
<br/> regfil_2_1_T <= ((holding(1) AND N_PZ_2114 AND NOT regfil_2_1)
|
| 3842 |
|
|
<br/> OR (NOT holding(1) AND regfil_2_1 AND NOT N_PZ_2155)
|
| 3843 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND regfil_2_1 AND
|
| 3844 |
|
|
<br/> N_PZ_1946)
|
| 3845 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND NOT regfil_2_1 AND
|
| 3846 |
|
|
<br/> N_PZ_1262)
|
| 3847 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3848 |
|
|
<br/> state(1) AND state(0) AND addrhold(8) AND NOT regfil_2_1)
|
| 3849 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3850 |
|
|
<br/> state(1) AND state(0) AND NOT addrhold(8) AND regfil_2_1)
|
| 3851 |
|
|
<br/> OR (regfil_3_0 AND regfil_2_0 AND regfil_3_1 AND
|
| 3852 |
|
|
<br/> regfil_3_2 AND regfil_3_3 AND regfil_3_4 AND regfil_3_5 AND
|
| 3853 |
|
|
<br/> N_PZ_1941 AND regfil_3_6 AND regfil_3_7)
|
| 3854 |
|
|
<br/> OR (regfil_3_0 AND NOT holding(1) AND regfil_2_0 AND
|
| 3855 |
|
|
<br/> N_PZ_2114 AND regfil_3_1 AND regfil_2_1 AND regfil_3_2 AND
|
| 3856 |
|
|
<br/> regfil_3_3 AND regfil_3_4 AND regfil_3_5 AND regfil_3_6 AND
|
| 3857 |
|
|
<br/> regfil_3_7));
|
| 3858 |
|
|
</td></tr><tr><td>
|
| 3859 |
|
|
FTCPE_regfil_2_2: FTCPE port map (regfil_2_2,regfil_2_2_T,clock,'0','0','1');
|
| 3860 |
|
|
<br/> regfil_2_2_T <= ((holding(2) AND N_PZ_2114 AND NOT regfil_2_2)
|
| 3861 |
|
|
<br/> OR (NOT holding(2) AND regfil_2_2 AND NOT N_PZ_2155)
|
| 3862 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1944 AND
|
| 3863 |
|
|
<br/> NOT regfil_2_2)
|
| 3864 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND regfil_2_2 AND
|
| 3865 |
|
|
<br/> N_PZ_1945)
|
| 3866 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3867 |
|
|
<br/> state(1) AND state(0) AND addrhold(9) AND NOT regfil_2_2)
|
| 3868 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3869 |
|
|
<br/> state(1) AND state(0) AND NOT addrhold(9) AND regfil_2_2)
|
| 3870 |
|
|
<br/> OR (regfil_3_0 AND regfil_2_0 AND regfil_3_1 AND
|
| 3871 |
|
|
<br/> regfil_2_1 AND regfil_3_2 AND regfil_3_3 AND regfil_3_4 AND
|
| 3872 |
|
|
<br/> regfil_3_5 AND N_PZ_1941 AND regfil_3_6 AND regfil_3_7)
|
| 3873 |
|
|
<br/> OR (regfil_3_0 AND NOT holding(2) AND regfil_2_0 AND
|
| 3874 |
|
|
<br/> N_PZ_2114 AND regfil_3_1 AND regfil_2_1 AND regfil_3_2 AND
|
| 3875 |
|
|
<br/> regfil_2_2 AND regfil_3_3 AND regfil_3_4 AND regfil_3_5 AND
|
| 3876 |
|
|
<br/> regfil_3_6 AND regfil_3_7));
|
| 3877 |
|
|
</td></tr><tr><td>
|
| 3878 |
|
|
FTCPE_regfil_2_3: FTCPE port map (regfil_2_3,regfil_2_3_T,clock,'0','0','1');
|
| 3879 |
|
|
<br/> regfil_2_3_T <= ((N_PZ_2114 AND holding(3) AND NOT regfil_2_3)
|
| 3880 |
|
|
<br/> OR (NOT holding(3) AND regfil_2_3 AND NOT N_PZ_2155)
|
| 3881 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1943 AND
|
| 3882 |
|
|
<br/> NOT regfil_2_3)
|
| 3883 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND regfil_2_3 AND
|
| 3884 |
|
|
<br/> N_PZ_2180)
|
| 3885 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3886 |
|
|
<br/> state(1) AND state(0) AND addrhold(10) AND NOT regfil_2_3)
|
| 3887 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3888 |
|
|
<br/> state(1) AND state(0) AND NOT addrhold(10) AND regfil_2_3)
|
| 3889 |
|
|
<br/> OR (regfil_3_0 AND regfil_2_0 AND regfil_3_1 AND
|
| 3890 |
|
|
<br/> regfil_2_1 AND regfil_3_2 AND regfil_2_2 AND regfil_3_3 AND
|
| 3891 |
|
|
<br/> regfil_3_4 AND regfil_3_5 AND N_PZ_1941 AND regfil_3_6 AND
|
| 3892 |
|
|
<br/> regfil_3_7)
|
| 3893 |
|
|
<br/> OR (regfil_3_0 AND regfil_2_0 AND N_PZ_2114 AND
|
| 3894 |
|
|
<br/> regfil_3_1 AND regfil_2_1 AND regfil_3_2 AND regfil_2_2 AND
|
| 3895 |
|
|
<br/> regfil_3_3 AND NOT holding(3) AND regfil_3_4 AND regfil_3_5 AND
|
| 3896 |
|
|
<br/> regfil_2_3 AND regfil_3_6 AND regfil_3_7));
|
| 3897 |
|
|
</td></tr><tr><td>
|
| 3898 |
|
|
FTCPE_regfil_2_4: FTCPE port map (regfil_2_4,regfil_2_4_T,clock,'0','0','1');
|
| 3899 |
|
|
<br/> regfil_2_4_T <= ((N_PZ_2114 AND holding(4) AND NOT regfil_2_4)
|
| 3900 |
|
|
<br/> OR (NOT holding(4) AND regfil_2_4 AND NOT N_PZ_2155)
|
| 3901 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_2181 AND
|
| 3902 |
|
|
<br/> regfil_2_4)
|
| 3903 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1996 AND
|
| 3904 |
|
|
<br/> NOT N_PZ_2181 AND NOT regfil_2_4)
|
| 3905 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3906 |
|
|
<br/> state(1) AND state(0) AND addrhold(11) AND NOT regfil_2_4)
|
| 3907 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3908 |
|
|
<br/> state(1) AND state(0) AND NOT addrhold(11) AND regfil_2_4)
|
| 3909 |
|
|
<br/> OR (regfil_3_0 AND regfil_2_0 AND regfil_3_1 AND
|
| 3910 |
|
|
<br/> regfil_2_1 AND regfil_3_2 AND regfil_2_2 AND regfil_3_3 AND
|
| 3911 |
|
|
<br/> regfil_3_4 AND regfil_3_5 AND N_PZ_1941 AND regfil_2_3 AND
|
| 3912 |
|
|
<br/> regfil_3_6 AND regfil_3_7)
|
| 3913 |
|
|
<br/> OR (regfil_3_0 AND regfil_2_0 AND N_PZ_2114 AND
|
| 3914 |
|
|
<br/> regfil_3_1 AND regfil_2_1 AND regfil_3_2 AND regfil_2_2 AND
|
| 3915 |
|
|
<br/> regfil_3_3 AND regfil_3_4 AND NOT holding(4) AND regfil_3_5 AND
|
| 3916 |
|
|
<br/> regfil_2_3 AND regfil_3_6 AND regfil_2_4 AND regfil_3_7));
|
| 3917 |
|
|
</td></tr><tr><td>
|
| 3918 |
|
|
FTCPE_regfil_2_5: FTCPE port map (regfil_2_5,regfil_2_5_T,clock,'0','0','1');
|
| 3919 |
|
|
<br/> regfil_2_5_T <= ((N_PZ_2114 AND holding(5) AND NOT regfil_2_5)
|
| 3920 |
|
|
<br/> OR (N_PZ_1941 AND regfil_2_5 AND NOT _mux0014(13)8)
|
| 3921 |
|
|
<br/> OR (N_PZ_2114 AND NOT holding(5) AND regfil_2_5 AND
|
| 3922 |
|
|
<br/> NOT _mux0014(13)8)
|
| 3923 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1265 AND
|
| 3924 |
|
|
<br/> NOT regfil_2_5)
|
| 3925 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3926 |
|
|
<br/> state(1) AND state(0) AND addrhold(12) AND NOT regfil_2_5)
|
| 3927 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3928 |
|
|
<br/> state(1) AND state(0) AND NOT addrhold(12) AND regfil_2_5)
|
| 3929 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3930 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_2_5 AND _mux0014(13)8)
|
| 3931 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 3932 |
|
|
<br/> NOT state(1) AND state(0) AND NOT regd(2) AND regd(1) AND NOT regd(0) AND
|
| 3933 |
|
|
<br/> NOT alures(5) AND regfil_2_5)
|
| 3934 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 3935 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(5).PIN AND NOT regd(2) AND regd(1) AND
|
| 3936 |
|
|
<br/> NOT regd(0) AND regfil_2_5)
|
| 3937 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3938 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND NOT regd(2) AND
|
| 3939 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND NOT regd(0) AND NOT N_PZ_1373 AND _COND_18(5) AND
|
| 3940 |
|
|
<br/> regfil_2_5 AND NOT _mux0014(13)8));
|
| 3941 |
|
|
</td></tr><tr><td>
|
| 3942 |
|
|
FTCPE_regfil_2_6: FTCPE port map (regfil_2_6,regfil_2_6_T,clock,'0','0','1');
|
| 3943 |
|
|
<br/> regfil_2_6_T <= ((N_PZ_2114 AND NOT regfil_2_6 AND holding(6))
|
| 3944 |
|
|
<br/> OR (N_PZ_1941 AND regfil_2_5 AND NOT _mux0014(13)8)
|
| 3945 |
|
|
<br/> OR (NOT _mux0014(13)8 AND regfil_2_6 AND NOT N_PZ_2155 AND
|
| 3946 |
|
|
<br/> NOT holding(6))
|
| 3947 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND NOT regfil_2_6 AND
|
| 3948 |
|
|
<br/> N_PZ_1888)
|
| 3949 |
|
|
<br/> OR (N_PZ_2114 AND regfil_2_5 AND NOT _mux0014(13)8 AND
|
| 3950 |
|
|
<br/> regfil_2_6 AND NOT holding(6))
|
| 3951 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3952 |
|
|
<br/> state(1) AND state(0) AND addrhold(13) AND NOT regfil_2_6)
|
| 3953 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3954 |
|
|
<br/> state(1) AND state(0) AND NOT addrhold(13) AND regfil_2_6)
|
| 3955 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 3956 |
|
|
<br/> NOT state(1) AND state(0) AND NOT regd(2) AND regd(1) AND NOT regd(0) AND
|
| 3957 |
|
|
<br/> regfil_2_6 AND NOT alures(6))
|
| 3958 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 3959 |
|
|
<br/> NOT state(1) AND state(0) AND data(6).PIN AND NOT regd(2) AND regd(1) AND
|
| 3960 |
|
|
<br/> NOT regd(0) AND NOT regfil_2_6)
|
| 3961 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 3962 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(6).PIN AND NOT regd(2) AND regd(1) AND
|
| 3963 |
|
|
<br/> NOT regd(0) AND regfil_2_6)
|
| 3964 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3965 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND NOT regd(2) AND
|
| 3966 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND NOT regd(0) AND NOT N_PZ_1373 AND NOT _mux0014(13)8 AND
|
| 3967 |
|
|
<br/> regfil_2_6 AND _COND_18(6)));
|
| 3968 |
|
|
</td></tr><tr><td>
|
| 3969 |
|
|
FTCPE_regfil_2_7: FTCPE port map (regfil_2_7,regfil_2_7_T,clock,'0','0','1');
|
| 3970 |
|
|
<br/> regfil_2_7_T <= ((N_PZ_2114 AND holding(7) AND NOT regfil_2_7)
|
| 3971 |
|
|
<br/> OR (NOT holding(7) AND NOT _mux0014(13)8 AND regfil_2_7 AND
|
| 3972 |
|
|
<br/> NOT N_PZ_2155)
|
| 3973 |
|
|
<br/> OR (N_PZ_1941 AND regfil_2_5 AND NOT _mux0014(13)8 AND
|
| 3974 |
|
|
<br/> regfil_2_6)
|
| 3975 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1266 AND
|
| 3976 |
|
|
<br/> NOT regfil_2_7)
|
| 3977 |
|
|
<br/> OR (N_PZ_2114 AND NOT holding(7) AND regfil_2_5 AND
|
| 3978 |
|
|
<br/> NOT _mux0014(13)8 AND regfil_2_7 AND regfil_2_6)
|
| 3979 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3980 |
|
|
<br/> state(1) AND state(0) AND addrhold(14) AND NOT regfil_2_7)
|
| 3981 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 3982 |
|
|
<br/> state(1) AND state(0) AND NOT addrhold(14) AND regfil_2_7)
|
| 3983 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 3984 |
|
|
<br/> NOT state(1) AND state(0) AND NOT regd(2) AND regd(1) AND NOT regd(0) AND
|
| 3985 |
|
|
<br/> NOT alures(7) AND regfil_2_7)
|
| 3986 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 3987 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(7).PIN AND NOT regd(2) AND regd(1) AND
|
| 3988 |
|
|
<br/> NOT regd(0) AND regfil_2_7)
|
| 3989 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 3990 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND NOT regd(2) AND
|
| 3991 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND NOT regd(0) AND _COND_18(7) AND NOT N_PZ_1373 AND
|
| 3992 |
|
|
<br/> NOT _mux0014(13)8 AND regfil_2_7));
|
| 3993 |
|
|
</td></tr><tr><td>
|
| 3994 |
|
|
FTCPE_regfil_3_0: FTCPE port map (regfil_3_0,regfil_3_0_T,clock,'0','0','1');
|
| 3995 |
|
|
<br/> regfil_3_0_T <= ((N_PZ_1941)
|
| 3996 |
|
|
<br/> OR (regfil_3_0 AND NOT holding(0) AND N_PZ_2114)
|
| 3997 |
|
|
<br/> OR (NOT regfil_3_0 AND holding(0) AND N_PZ_2114)
|
| 3998 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND regfil_3_0 AND
|
| 3999 |
|
|
<br/> N_PZ_1268)
|
| 4000 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND NOT regfil_3_0 AND
|
| 4001 |
|
|
<br/> NOT N_PZ_1268 AND N_PZ_1996)
|
| 4002 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 4003 |
|
|
<br/> state(1) AND state(0) AND addrhold(0) AND NOT regfil_3_0)
|
| 4004 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 4005 |
|
|
<br/> state(1) AND state(0) AND NOT addrhold(0) AND regfil_3_0));
|
| 4006 |
|
|
</td></tr><tr><td>
|
| 4007 |
|
|
FTCPE_regfil_3_1: FTCPE port map (regfil_3_1,regfil_3_1_T,clock,'0','0','1');
|
| 4008 |
|
|
<br/> regfil_3_1_T <= ((regfil_3_0 AND N_PZ_1941)
|
| 4009 |
|
|
<br/> OR (holding(1) AND N_PZ_2114 AND NOT regfil_3_1)
|
| 4010 |
|
|
<br/> OR (NOT holding(1) AND N_PZ_2114 AND regfil_3_1)
|
| 4011 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND regfil_3_1 AND
|
| 4012 |
|
|
<br/> N_PZ_1946)
|
| 4013 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND NOT regfil_3_1 AND
|
| 4014 |
|
|
<br/> N_PZ_1262)
|
| 4015 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 4016 |
|
|
<br/> state(1) AND state(0) AND regfil_3_1 AND NOT addrhold(1))
|
| 4017 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 4018 |
|
|
<br/> state(1) AND state(0) AND NOT regfil_3_1 AND addrhold(1)));
|
| 4019 |
|
|
</td></tr><tr><td>
|
| 4020 |
|
|
FTCPE_regfil_3_2: FTCPE port map (regfil_3_2,regfil_3_2_T,clock,'0','0','1');
|
| 4021 |
|
|
<br/> regfil_3_2_T <= ((regfil_3_0 AND regfil_3_1 AND N_PZ_1941)
|
| 4022 |
|
|
<br/> OR (holding(2) AND N_PZ_2114 AND NOT regfil_3_2)
|
| 4023 |
|
|
<br/> OR (NOT holding(2) AND N_PZ_2114 AND regfil_3_2)
|
| 4024 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND regfil_3_2 AND
|
| 4025 |
|
|
<br/> N_PZ_1945)
|
| 4026 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND NOT regfil_3_2 AND
|
| 4027 |
|
|
<br/> N_PZ_1944)
|
| 4028 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 4029 |
|
|
<br/> state(1) AND state(0) AND regfil_3_2 AND NOT addrhold(2))
|
| 4030 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 4031 |
|
|
<br/> state(1) AND state(0) AND NOT regfil_3_2 AND addrhold(2)));
|
| 4032 |
|
|
</td></tr><tr><td>
|
| 4033 |
|
|
FTCPE_regfil_3_3: FTCPE port map (regfil_3_3,regfil_3_3_T,clock,'0','0','1');
|
| 4034 |
|
|
<br/> regfil_3_3_T <= ((N_PZ_2114 AND regfil_3_3 AND NOT holding(3))
|
| 4035 |
|
|
<br/> OR (N_PZ_2114 AND NOT regfil_3_3 AND holding(3))
|
| 4036 |
|
|
<br/> OR (regfil_3_0 AND regfil_3_1 AND regfil_3_2 AND
|
| 4037 |
|
|
<br/> N_PZ_1941)
|
| 4038 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND N_PZ_1943 AND
|
| 4039 |
|
|
<br/> NOT regfil_3_3)
|
| 4040 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND regfil_3_3 AND
|
| 4041 |
|
|
<br/> N_PZ_2180)
|
| 4042 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 4043 |
|
|
<br/> state(1) AND state(0) AND addrhold(3) AND NOT regfil_3_3)
|
| 4044 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 4045 |
|
|
<br/> state(1) AND state(0) AND NOT addrhold(3) AND regfil_3_3));
|
| 4046 |
|
|
</td></tr><tr><td>
|
| 4047 |
|
|
FTCPE_regfil_3_4: FTCPE port map (regfil_3_4,regfil_3_4_T,clock,'0','0','1');
|
| 4048 |
|
|
<br/> regfil_3_4_T <= ((N_PZ_2114 AND regfil_3_4 AND NOT holding(4))
|
| 4049 |
|
|
<br/> OR (N_PZ_2114 AND NOT regfil_3_4 AND holding(4))
|
| 4050 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND regfil_3_4 AND
|
| 4051 |
|
|
<br/> N_PZ_2181)
|
| 4052 |
|
|
<br/> OR (regfil_3_0 AND regfil_3_1 AND regfil_3_2 AND
|
| 4053 |
|
|
<br/> regfil_3_3 AND N_PZ_1941)
|
| 4054 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND N_PZ_1996 AND
|
| 4055 |
|
|
<br/> NOT regfil_3_4 AND NOT N_PZ_2181)
|
| 4056 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 4057 |
|
|
<br/> state(1) AND state(0) AND addrhold(4) AND NOT regfil_3_4)
|
| 4058 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 4059 |
|
|
<br/> state(1) AND state(0) AND NOT addrhold(4) AND regfil_3_4));
|
| 4060 |
|
|
</td></tr><tr><td>
|
| 4061 |
|
|
FTCPE_regfil_3_5: FTCPE port map (regfil_3_5,regfil_3_5_T,clock,'0','0','1');
|
| 4062 |
|
|
<br/> regfil_3_5_T <= ((N_PZ_2114 AND regfil_3_5 AND NOT holding(5))
|
| 4063 |
|
|
<br/> OR (N_PZ_2114 AND NOT regfil_3_5 AND holding(5))
|
| 4064 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND regfil_3_5 AND
|
| 4065 |
|
|
<br/> N_PZ_2000)
|
| 4066 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND NOT regfil_3_5 AND
|
| 4067 |
|
|
<br/> N_PZ_1265)
|
| 4068 |
|
|
<br/> OR (regfil_3_0 AND regfil_3_1 AND regfil_3_2 AND
|
| 4069 |
|
|
<br/> regfil_3_3 AND regfil_3_4 AND N_PZ_1941)
|
| 4070 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 4071 |
|
|
<br/> state(1) AND state(0) AND addrhold(5) AND NOT regfil_3_5)
|
| 4072 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 4073 |
|
|
<br/> state(1) AND state(0) AND NOT addrhold(5) AND regfil_3_5));
|
| 4074 |
|
|
</td></tr><tr><td>
|
| 4075 |
|
|
FTCPE_regfil_3_6: FTCPE port map (regfil_3_6,regfil_3_6_T,clock,'0','0','1');
|
| 4076 |
|
|
<br/> regfil_3_6_T <= ((N_PZ_2114 AND regfil_3_6 AND NOT holding(6))
|
| 4077 |
|
|
<br/> OR (N_PZ_2114 AND NOT regfil_3_6 AND holding(6))
|
| 4078 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND regfil_3_6 AND
|
| 4079 |
|
|
<br/> N_PZ_2106)
|
| 4080 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND NOT regfil_3_6 AND
|
| 4081 |
|
|
<br/> N_PZ_1888)
|
| 4082 |
|
|
<br/> OR (regfil_3_0 AND regfil_3_1 AND regfil_3_2 AND
|
| 4083 |
|
|
<br/> regfil_3_3 AND regfil_3_4 AND regfil_3_5 AND N_PZ_1941)
|
| 4084 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 4085 |
|
|
<br/> state(1) AND state(0) AND regfil_3_6 AND NOT addrhold(6))
|
| 4086 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 4087 |
|
|
<br/> state(1) AND state(0) AND NOT regfil_3_6 AND addrhold(6))
|
| 4088 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 4089 |
|
|
<br/> NOT state(1) AND state(0) AND data(6).PIN AND NOT regd(2) AND regd(1) AND
|
| 4090 |
|
|
<br/> regd(0) AND NOT regfil_3_6));
|
| 4091 |
|
|
</td></tr><tr><td>
|
| 4092 |
|
|
FTCPE_regfil_3_7: FTCPE port map (regfil_3_7,regfil_3_7_T,clock,'0','0','1');
|
| 4093 |
|
|
<br/> regfil_3_7_T <= ((N_PZ_2114 AND holding(7) AND NOT regfil_3_7)
|
| 4094 |
|
|
<br/> OR (N_PZ_2114 AND NOT holding(7) AND regfil_3_7)
|
| 4095 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND N_PZ_1266 AND
|
| 4096 |
|
|
<br/> NOT regfil_3_7)
|
| 4097 |
|
|
<br/> OR (NOT regd(2) AND regd(1) AND regd(0) AND regfil_3_7 AND
|
| 4098 |
|
|
<br/> N_PZ_2001)
|
| 4099 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 4100 |
|
|
<br/> state(1) AND state(0) AND addrhold(7) AND NOT regfil_3_7)
|
| 4101 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 4102 |
|
|
<br/> state(1) AND state(0) AND NOT addrhold(7) AND regfil_3_7)
|
| 4103 |
|
|
<br/> OR (regfil_3_0 AND regfil_3_1 AND regfil_3_2 AND
|
| 4104 |
|
|
<br/> regfil_3_3 AND regfil_3_4 AND regfil_3_5 AND N_PZ_1941 AND
|
| 4105 |
|
|
<br/> regfil_3_6));
|
| 4106 |
|
|
</td></tr><tr><td>
|
| 4107 |
|
|
FTCPE_regfil_4_0: FTCPE port map (regfil_4_0,regfil_4_0_T,clock,'0','0','1');
|
| 4108 |
|
|
<br/> regfil_4_0_T <= ((data(0).PIN AND NOT regfil_4_0 AND N_PZ_1061)
|
| 4109 |
|
|
<br/> OR (NOT data(0).PIN AND regfil_4_0 AND N_PZ_1061)
|
| 4110 |
|
|
<br/> OR (regfil_4_0 AND N_PZ_1100 AND NOT _mux0010(8)71)
|
| 4111 |
|
|
<br/> OR (NOT regfil_4_0 AND regfil_2_0 AND N_PZ_2114)
|
| 4112 |
|
|
<br/> OR (regfil_4_0 AND NOT regfil_2_0 AND N_PZ_2114 AND
|
| 4113 |
|
|
<br/> NOT _mux0010(8)71)
|
| 4114 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4115 |
|
|
<br/> NOT state(1) AND NOT state(0) AND addrhold(7) AND NOT regfil_4_0)
|
| 4116 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4117 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT addrhold(7) AND regfil_4_0)
|
| 4118 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4119 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_4_0 AND _mux0010(8)71)
|
| 4120 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4121 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND
|
| 4122 |
|
|
<br/> regfil_4_0 AND NOT alures(0))
|
| 4123 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4124 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND
|
| 4125 |
|
|
<br/> NOT regfil_4_0 AND alures(0))
|
| 4126 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4127 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4128 |
|
|
<br/> NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT regfil_4_0 AND NOT _COND_18(0) AND
|
| 4129 |
|
|
<br/> NOT N_PZ_1373)
|
| 4130 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4131 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4132 |
|
|
<br/> NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND regfil_4_0 AND _COND_18(0) AND
|
| 4133 |
|
|
<br/> NOT N_PZ_1373 AND NOT _mux0010(8)71));
|
| 4134 |
|
|
</td></tr><tr><td>
|
| 4135 |
|
|
FTCPE_regfil_4_1: FTCPE port map (regfil_4_1,regfil_4_1_T,clock,'0','0','1');
|
| 4136 |
|
|
<br/> regfil_4_1_T <= ((data(1).PIN AND NOT regfil_4_1 AND N_PZ_1061)
|
| 4137 |
|
|
<br/> OR (NOT data(1).PIN AND regfil_4_1 AND N_PZ_1061)
|
| 4138 |
|
|
<br/> OR (regfil_4_1 AND N_PZ_1100 AND NOT _mux0010(9)71)
|
| 4139 |
|
|
<br/> OR (NOT regfil_4_1 AND N_PZ_2114 AND regfil_2_1)
|
| 4140 |
|
|
<br/> OR (regfil_4_1 AND N_PZ_2114 AND NOT regfil_2_1 AND
|
| 4141 |
|
|
<br/> NOT _mux0010(9)71)
|
| 4142 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4143 |
|
|
<br/> NOT state(1) AND NOT state(0) AND regfil_4_1 AND NOT addrhold(8))
|
| 4144 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4145 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT regfil_4_1 AND addrhold(8))
|
| 4146 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4147 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_4_1 AND _mux0010(9)71)
|
| 4148 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4149 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND
|
| 4150 |
|
|
<br/> regfil_4_1 AND NOT alures(1))
|
| 4151 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4152 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND
|
| 4153 |
|
|
<br/> NOT regfil_4_1 AND alures(1))
|
| 4154 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4155 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4156 |
|
|
<br/> NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT regfil_4_1 AND NOT N_PZ_1373 AND
|
| 4157 |
|
|
<br/> NOT _COND_18(1))
|
| 4158 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4159 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4160 |
|
|
<br/> NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND regfil_4_1 AND NOT N_PZ_1373 AND
|
| 4161 |
|
|
<br/> _COND_18(1) AND NOT _mux0010(9)71));
|
| 4162 |
|
|
</td></tr><tr><td>
|
| 4163 |
|
|
FTCPE_regfil_4_2: FTCPE port map (regfil_4_2,regfil_4_2_T,clock,'0','0','1');
|
| 4164 |
|
|
<br/> regfil_4_2_T <= ((data(2).PIN AND NOT regfil_4_2 AND N_PZ_1061)
|
| 4165 |
|
|
<br/> OR (NOT data(2).PIN AND regfil_4_2 AND N_PZ_1061)
|
| 4166 |
|
|
<br/> OR (regfil_4_2 AND N_PZ_1100 AND NOT _mux0010(10)71)
|
| 4167 |
|
|
<br/> OR (NOT regfil_4_2 AND N_PZ_2114 AND regfil_2_2)
|
| 4168 |
|
|
<br/> OR (regfil_4_2 AND N_PZ_2114 AND NOT regfil_2_2 AND
|
| 4169 |
|
|
<br/> NOT _mux0010(10)71)
|
| 4170 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4171 |
|
|
<br/> NOT state(1) AND NOT state(0) AND regfil_4_2 AND NOT addrhold(9))
|
| 4172 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4173 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT regfil_4_2 AND addrhold(9))
|
| 4174 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4175 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_4_2 AND _mux0010(10)71)
|
| 4176 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4177 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND
|
| 4178 |
|
|
<br/> regfil_4_2 AND NOT alures(2))
|
| 4179 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4180 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND
|
| 4181 |
|
|
<br/> NOT regfil_4_2 AND alures(2))
|
| 4182 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4183 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4184 |
|
|
<br/> NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT regfil_4_2 AND NOT N_PZ_1373 AND
|
| 4185 |
|
|
<br/> NOT _COND_18(2))
|
| 4186 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4187 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4188 |
|
|
<br/> NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND regfil_4_2 AND NOT N_PZ_1373 AND
|
| 4189 |
|
|
<br/> _COND_18(2) AND NOT _mux0010(10)71));
|
| 4190 |
|
|
</td></tr><tr><td>
|
| 4191 |
|
|
FTCPE_regfil_4_3: FTCPE port map (regfil_4_3,regfil_4_3_T,clock,'0','0','1');
|
| 4192 |
|
|
<br/> regfil_4_3_T <= ((data(3).PIN AND NOT regfil_4_3 AND N_PZ_1061)
|
| 4193 |
|
|
<br/> OR (NOT data(3).PIN AND regfil_4_3 AND N_PZ_1061)
|
| 4194 |
|
|
<br/> OR (N_PZ_2114 AND NOT regfil_4_3 AND regfil_2_3)
|
| 4195 |
|
|
<br/> OR (regfil_4_3 AND N_PZ_1100 AND NOT _mux0010(11)71)
|
| 4196 |
|
|
<br/> OR (N_PZ_2114 AND regfil_4_3 AND NOT regfil_2_3 AND
|
| 4197 |
|
|
<br/> NOT _mux0010(11)71)
|
| 4198 |
|
|
<br/> OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND N_PZ_1157 AND
|
| 4199 |
|
|
<br/> NOT regfil_4_3)
|
| 4200 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4201 |
|
|
<br/> NOT state(1) AND NOT state(0) AND regfil_4_3 AND NOT addrhold(10))
|
| 4202 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4203 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT regfil_4_3 AND addrhold(10))
|
| 4204 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4205 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_4_3 AND _mux0010(11)71)
|
| 4206 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4207 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND
|
| 4208 |
|
|
<br/> NOT alures(3) AND regfil_4_3)
|
| 4209 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4210 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4211 |
|
|
<br/> NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT N_PZ_1373 AND regfil_4_3 AND
|
| 4212 |
|
|
<br/> _COND_18(3) AND NOT _mux0010(11)71));
|
| 4213 |
|
|
</td></tr><tr><td>
|
| 4214 |
|
|
FTCPE_regfil_4_4: FTCPE port map (regfil_4_4,regfil_4_4_T,clock,'0','0','1');
|
| 4215 |
|
|
<br/> regfil_4_4_T <= ((data(4).PIN AND NOT regfil_4_4 AND N_PZ_1061)
|
| 4216 |
|
|
<br/> OR (NOT data(4).PIN AND regfil_4_4 AND N_PZ_1061)
|
| 4217 |
|
|
<br/> OR (N_PZ_2114 AND NOT regfil_4_4 AND regfil_2_4)
|
| 4218 |
|
|
<br/> OR (regfil_4_4 AND N_PZ_1100 AND NOT _mux0010(12)71)
|
| 4219 |
|
|
<br/> OR (N_PZ_2114 AND regfil_4_4 AND NOT regfil_2_4 AND
|
| 4220 |
|
|
<br/> NOT _mux0010(12)71)
|
| 4221 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4222 |
|
|
<br/> NOT state(1) AND NOT state(0) AND regfil_4_4 AND NOT addrhold(11))
|
| 4223 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4224 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT regfil_4_4 AND addrhold(11))
|
| 4225 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4226 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_4_4 AND _mux0010(12)71)
|
| 4227 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4228 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND
|
| 4229 |
|
|
<br/> regfil_4_4 AND NOT alures(4))
|
| 4230 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4231 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND
|
| 4232 |
|
|
<br/> NOT regfil_4_4 AND alures(4))
|
| 4233 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4234 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4235 |
|
|
<br/> NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT N_PZ_1373 AND NOT regfil_4_4 AND
|
| 4236 |
|
|
<br/> NOT _COND_18(4))
|
| 4237 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4238 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4239 |
|
|
<br/> NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT N_PZ_1373 AND regfil_4_4 AND
|
| 4240 |
|
|
<br/> _COND_18(4) AND NOT _mux0010(12)71));
|
| 4241 |
|
|
</td></tr><tr><td>
|
| 4242 |
|
|
FTCPE_regfil_4_5: FTCPE port map (regfil_4_5,regfil_4_5_T,clock,'0','0','1');
|
| 4243 |
|
|
<br/> regfil_4_5_T <= ((data(5).PIN AND NOT regfil_4_5 AND N_PZ_1061)
|
| 4244 |
|
|
<br/> OR (NOT data(5).PIN AND regfil_4_5 AND N_PZ_1061)
|
| 4245 |
|
|
<br/> OR (N_PZ_2114 AND NOT regfil_4_5 AND regfil_2_5)
|
| 4246 |
|
|
<br/> OR (regfil_4_5 AND N_PZ_1100 AND NOT _mux0010(13)71)
|
| 4247 |
|
|
<br/> OR (N_PZ_2114 AND regfil_4_5 AND NOT regfil_2_5 AND
|
| 4248 |
|
|
<br/> NOT _mux0010(13)71)
|
| 4249 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4250 |
|
|
<br/> NOT state(1) AND NOT state(0) AND regfil_4_5 AND NOT addrhold(12))
|
| 4251 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4252 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT regfil_4_5 AND addrhold(12))
|
| 4253 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4254 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_4_5 AND _mux0010(13)71)
|
| 4255 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4256 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND
|
| 4257 |
|
|
<br/> regfil_4_5 AND NOT alures(5))
|
| 4258 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4259 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND
|
| 4260 |
|
|
<br/> NOT regfil_4_5 AND alures(5))
|
| 4261 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4262 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4263 |
|
|
<br/> NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT N_PZ_1373 AND NOT regfil_4_5 AND
|
| 4264 |
|
|
<br/> NOT _COND_18(5))
|
| 4265 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4266 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4267 |
|
|
<br/> NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT N_PZ_1373 AND regfil_4_5 AND
|
| 4268 |
|
|
<br/> _COND_18(5) AND NOT _mux0010(13)71));
|
| 4269 |
|
|
</td></tr><tr><td>
|
| 4270 |
|
|
FTCPE_regfil_4_6: FTCPE port map (regfil_4_6,regfil_4_6_T,clock,'0','0','1');
|
| 4271 |
|
|
<br/> regfil_4_6_T <= ((data(6).PIN AND NOT regfil_4_6 AND N_PZ_1061)
|
| 4272 |
|
|
<br/> OR (NOT data(6).PIN AND regfil_4_6 AND N_PZ_1061)
|
| 4273 |
|
|
<br/> OR (N_PZ_2114 AND NOT regfil_4_6 AND regfil_2_6)
|
| 4274 |
|
|
<br/> OR (regfil_4_6 AND N_PZ_1100 AND NOT _mux0010(14)71)
|
| 4275 |
|
|
<br/> OR (N_PZ_2114 AND regfil_4_6 AND NOT regfil_2_6 AND
|
| 4276 |
|
|
<br/> NOT _mux0010(14)71)
|
| 4277 |
|
|
<br/> OR (regd(2) AND NOT regd(1) AND NOT regd(0) AND NOT regfil_4_6 AND
|
| 4278 |
|
|
<br/> N_PZ_1888)
|
| 4279 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4280 |
|
|
<br/> NOT state(1) AND NOT state(0) AND regfil_4_6 AND NOT addrhold(13))
|
| 4281 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4282 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT regfil_4_6 AND addrhold(13))
|
| 4283 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4284 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_4_6 AND _mux0010(14)71)
|
| 4285 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4286 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND
|
| 4287 |
|
|
<br/> regfil_4_6 AND NOT alures(6))
|
| 4288 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4289 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4290 |
|
|
<br/> NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT N_PZ_1373 AND regfil_4_6 AND
|
| 4291 |
|
|
<br/> _COND_18(6) AND NOT _mux0010(14)71));
|
| 4292 |
|
|
</td></tr><tr><td>
|
| 4293 |
|
|
FTCPE_regfil_4_7: FTCPE port map (regfil_4_7,regfil_4_7_T,clock,'0','0','1');
|
| 4294 |
|
|
<br/> regfil_4_7_T <= ((data(7).PIN AND NOT regfil_4_7 AND N_PZ_1061)
|
| 4295 |
|
|
<br/> OR (NOT data(7).PIN AND regfil_4_7 AND N_PZ_1061)
|
| 4296 |
|
|
<br/> OR (N_PZ_2114 AND NOT regfil_4_7 AND regfil_2_7)
|
| 4297 |
|
|
<br/> OR (regfil_4_7 AND N_PZ_1100 AND NOT _mux0010(15)71)
|
| 4298 |
|
|
<br/> OR (N_PZ_2114 AND regfil_4_7 AND NOT regfil_2_7 AND
|
| 4299 |
|
|
<br/> NOT _mux0010(15)71)
|
| 4300 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4301 |
|
|
<br/> NOT state(1) AND NOT state(0) AND regfil_4_7 AND NOT addrhold(14))
|
| 4302 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4303 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT regfil_4_7 AND addrhold(14))
|
| 4304 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4305 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_4_7 AND _mux0010(15)71)
|
| 4306 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4307 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND
|
| 4308 |
|
|
<br/> regfil_4_7 AND NOT alures(7))
|
| 4309 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4310 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND NOT regd(1) AND NOT regd(0) AND
|
| 4311 |
|
|
<br/> NOT regfil_4_7 AND alures(7))
|
| 4312 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4313 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4314 |
|
|
<br/> NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND NOT _COND_18(7) AND NOT N_PZ_1373 AND
|
| 4315 |
|
|
<br/> NOT regfil_4_7)
|
| 4316 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4317 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4318 |
|
|
<br/> NOT _cmp_eq0004 AND NOT regd(1) AND NOT regd(0) AND _COND_18(7) AND NOT N_PZ_1373 AND
|
| 4319 |
|
|
<br/> regfil_4_7 AND NOT _mux0010(15)71));
|
| 4320 |
|
|
</td></tr><tr><td>
|
| 4321 |
|
|
FTCPE_regfil_5_0: FTCPE port map (regfil_5_0,regfil_5_0_T,clock,'0','0','1');
|
| 4322 |
|
|
<br/> regfil_5_0_T <= ((N_PZ_1528)
|
| 4323 |
|
|
<br/> OR (regfil_3_0 AND N_PZ_1533)
|
| 4324 |
|
|
<br/> OR (regfil_1_0 AND N_PZ_1432)
|
| 4325 |
|
|
<br/> OR (sp(0) AND N_PZ_1536)
|
| 4326 |
|
|
<br/> OR (data(0).PIN AND NOT regfil_5_0 AND N_PZ_1062)
|
| 4327 |
|
|
<br/> OR (NOT data(0).PIN AND regfil_5_0 AND N_PZ_1062)
|
| 4328 |
|
|
<br/> OR (regfil_5_0 AND NOT regfil_3_0 AND N_PZ_2114)
|
| 4329 |
|
|
<br/> OR (regfil_5_0 AND _COND_18(0) AND N_PZ_2196)
|
| 4330 |
|
|
<br/> OR (NOT regfil_5_0 AND regfil_3_0 AND N_PZ_2114)
|
| 4331 |
|
|
<br/> OR (NOT regfil_5_0 AND NOT _COND_18(0) AND N_PZ_2196)
|
| 4332 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4333 |
|
|
<br/> NOT state(1) AND NOT state(0) AND addrhold(0) AND NOT regfil_5_0)
|
| 4334 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4335 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT addrhold(0) AND regfil_5_0)
|
| 4336 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4337 |
|
|
<br/> NOT state(1) AND state(0) AND regfil_5_0 AND NOT alures(0) AND N_PZ_1129)
|
| 4338 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4339 |
|
|
<br/> NOT state(1) AND state(0) AND NOT regfil_5_0 AND alures(0) AND N_PZ_1129)
|
| 4340 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4341 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 4342 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND
|
| 4343 |
|
|
<br/> regfil_5_0));
|
| 4344 |
|
|
</td></tr><tr><td>
|
| 4345 |
|
|
FTCPE_regfil_5_1: FTCPE port map (regfil_5_1,regfil_5_1_T,clock,'0','0','1');
|
| 4346 |
|
|
<br/> regfil_5_1_T <= ((regfil_5_0 AND N_PZ_1528)
|
| 4347 |
|
|
<br/> OR (data(1).PIN AND NOT regfil_5_1 AND N_PZ_1062)
|
| 4348 |
|
|
<br/> OR (NOT data(1).PIN AND regfil_5_1 AND N_PZ_1062)
|
| 4349 |
|
|
<br/> OR (regfil_5_0 AND NOT regfil_5_1 AND N_PZ_1580)
|
| 4350 |
|
|
<br/> OR (NOT regfil_5_0 AND regfil_3_1 AND N_PZ_1533)
|
| 4351 |
|
|
<br/> OR (NOT regfil_5_0 AND regfil_5_1 AND N_PZ_1580)
|
| 4352 |
|
|
<br/> OR (NOT regfil_5_0 AND sp(1) AND N_PZ_1536)
|
| 4353 |
|
|
<br/> OR (NOT regfil_5_0 AND regfil_1_1 AND N_PZ_1432)
|
| 4354 |
|
|
<br/> OR (NOT regfil_3_0 AND regfil_3_1 AND N_PZ_1533)
|
| 4355 |
|
|
<br/> OR (NOT regfil_1_0 AND regfil_1_1 AND N_PZ_1432)
|
| 4356 |
|
|
<br/> OR (N_PZ_2114 AND regfil_3_1 AND NOT regfil_5_1)
|
| 4357 |
|
|
<br/> OR (N_PZ_2114 AND NOT regfil_3_1 AND regfil_5_1)
|
| 4358 |
|
|
<br/> OR (regfil_5_1 AND _COND_18(1) AND N_PZ_2196)
|
| 4359 |
|
|
<br/> OR (NOT regfil_5_1 AND N_PZ_1129 AND N_PZ_1262)
|
| 4360 |
|
|
<br/> OR (NOT sp(0) AND sp(1) AND N_PZ_1536)
|
| 4361 |
|
|
<br/> OR (regfil_5_0 AND regfil_3_0 AND NOT regfil_3_1 AND
|
| 4362 |
|
|
<br/> N_PZ_1533)
|
| 4363 |
|
|
<br/> OR (regfil_5_0 AND regfil_1_0 AND NOT regfil_1_1 AND
|
| 4364 |
|
|
<br/> N_PZ_1432)
|
| 4365 |
|
|
<br/> OR (regfil_5_0 AND sp(0) AND NOT sp(1) AND N_PZ_1536)
|
| 4366 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4367 |
|
|
<br/> NOT state(1) AND NOT state(0) AND addrhold(1) AND NOT regfil_5_1)
|
| 4368 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4369 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT addrhold(1) AND regfil_5_1)
|
| 4370 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4371 |
|
|
<br/> NOT state(1) AND state(0) AND regfil_5_1 AND N_PZ_1129 AND NOT alures(1)));
|
| 4372 |
|
|
</td></tr><tr><td>
|
| 4373 |
|
|
FTCPE_regfil_5_2: FTCPE port map (regfil_5_2,regfil_5_2_T,clock,'0','0','1');
|
| 4374 |
|
|
<br/> regfil_5_2_T <= ((data(2).PIN AND N_PZ_1062 AND NOT regfil_5_2)
|
| 4375 |
|
|
<br/> OR (NOT data(2).PIN AND N_PZ_1062 AND regfil_5_2)
|
| 4376 |
|
|
<br/> OR (N_PZ_2114 AND regfil_3_2 AND NOT regfil_5_2)
|
| 4377 |
|
|
<br/> OR (regfil_5_2 AND NOT _mux0009(2)72 AND N_PZ_1100)
|
| 4378 |
|
|
<br/> OR (N_PZ_2114 AND NOT regfil_3_2 AND regfil_5_2 AND
|
| 4379 |
|
|
<br/> NOT _mux0009(2)72)
|
| 4380 |
|
|
<br/> OR (regfil_5_2 AND NOT _mux0009(2)72 AND _COND_18(2) AND
|
| 4381 |
|
|
<br/> N_PZ_2196)
|
| 4382 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4383 |
|
|
<br/> NOT state(1) AND NOT state(0) AND addrhold(2) AND NOT regfil_5_2)
|
| 4384 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4385 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT addrhold(2) AND regfil_5_2)
|
| 4386 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4387 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_5_2 AND _mux0009(2)72)
|
| 4388 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4389 |
|
|
<br/> NOT state(1) AND state(0) AND N_PZ_1129 AND regfil_5_2 AND NOT alures(2))
|
| 4390 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4391 |
|
|
<br/> NOT state(1) AND state(0) AND N_PZ_1129 AND NOT regfil_5_2 AND alures(2))
|
| 4392 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4393 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 4394 |
|
|
<br/> NOT _cmp_eq0004 AND NOT N_PZ_1373 AND N_PZ_1129 AND NOT regfil_5_2 AND
|
| 4395 |
|
|
<br/> NOT _COND_18(2)));
|
| 4396 |
|
|
</td></tr><tr><td>
|
| 4397 |
|
|
FTCPE_regfil_5_3: FTCPE port map (regfil_5_3,regfil_5_3_T,clock,'0','0','1');
|
| 4398 |
|
|
<br/> regfil_5_3_T <= ((data(3).PIN AND NOT regfil_5_3 AND N_PZ_1062)
|
| 4399 |
|
|
<br/> OR (NOT data(3).PIN AND regfil_5_3 AND N_PZ_1062)
|
| 4400 |
|
|
<br/> OR (regfil_5_3 AND N_PZ_2114 AND NOT regfil_3_3)
|
| 4401 |
|
|
<br/> OR (regfil_5_3 AND NOT regfil_5_2 AND N_PZ_1580)
|
| 4402 |
|
|
<br/> OR (regfil_5_3 AND _COND_18(3) AND N_PZ_2196)
|
| 4403 |
|
|
<br/> OR (NOT regfil_5_3 AND N_PZ_2114 AND regfil_3_3)
|
| 4404 |
|
|
<br/> OR (NOT regfil_5_3 AND N_PZ_1129 AND N_PZ_1157)
|
| 4405 |
|
|
<br/> OR (NOT regfil_5_3 AND regfil_5_2 AND N_PZ_1580)
|
| 4406 |
|
|
<br/> OR (regfil_1_3 AND N_PZ_2004 AND N_PZ_1432)
|
| 4407 |
|
|
<br/> OR (regfil_3_3 AND NOT N_PZ_2358 AND N_PZ_1533)
|
| 4408 |
|
|
<br/> OR (NOT regfil_3_3 AND N_PZ_2358 AND N_PZ_1533)
|
| 4409 |
|
|
<br/> OR (sp(3) AND NOT Madd__AUX_11__or0001 AND N_PZ_1536)
|
| 4410 |
|
|
<br/> OR (NOT sp(3) AND Madd__AUX_11__or0001 AND N_PZ_1536)
|
| 4411 |
|
|
<br/> OR (regfil_5_0 AND regfil_5_1 AND regfil_5_2 AND
|
| 4412 |
|
|
<br/> N_PZ_1528)
|
| 4413 |
|
|
<br/> OR (regfil_5_2 AND regfil_1_2 AND NOT regfil_1_3 AND
|
| 4414 |
|
|
<br/> N_PZ_1432)
|
| 4415 |
|
|
<br/> OR (regfil_5_2 AND NOT regfil_1_3 AND
|
| 4416 |
|
|
<br/> Madd__addsub0000__or0000 AND N_PZ_1432)
|
| 4417 |
|
|
<br/> OR (regfil_1_2 AND NOT regfil_1_3 AND
|
| 4418 |
|
|
<br/> Madd__addsub0000__or0000 AND N_PZ_1432)
|
| 4419 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4420 |
|
|
<br/> NOT state(1) AND NOT state(0) AND regfil_5_3 AND NOT addrhold(3))
|
| 4421 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4422 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT regfil_5_3 AND addrhold(3))
|
| 4423 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4424 |
|
|
<br/> NOT state(1) AND state(0) AND regfil_5_3 AND N_PZ_1129 AND NOT alures(3)));
|
| 4425 |
|
|
</td></tr><tr><td>
|
| 4426 |
|
|
FTCPE_regfil_5_4: FTCPE port map (regfil_5_4,regfil_5_4_T,clock,'0','0','1');
|
| 4427 |
|
|
<br/> regfil_5_4_T <= ((data(4).PIN AND N_PZ_1062 AND NOT regfil_5_4)
|
| 4428 |
|
|
<br/> OR (NOT data(4).PIN AND N_PZ_1062 AND regfil_5_4)
|
| 4429 |
|
|
<br/> OR (N_PZ_2114 AND NOT regfil_5_4 AND regfil_3_4)
|
| 4430 |
|
|
<br/> OR (regfil_5_4 AND NOT _mux0009(4)72 AND N_PZ_1100)
|
| 4431 |
|
|
<br/> OR (NOT regfil_5_4 AND NOT _COND_18(4) AND N_PZ_2196)
|
| 4432 |
|
|
<br/> OR (N_PZ_2114 AND regfil_5_4 AND NOT _mux0009(4)72 AND
|
| 4433 |
|
|
<br/> NOT regfil_3_4)
|
| 4434 |
|
|
<br/> OR (regfil_5_4 AND NOT _mux0009(4)72 AND _COND_18(4) AND
|
| 4435 |
|
|
<br/> N_PZ_2196)
|
| 4436 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4437 |
|
|
<br/> NOT state(1) AND NOT state(0) AND addrhold(4) AND NOT regfil_5_4)
|
| 4438 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4439 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT addrhold(4) AND regfil_5_4)
|
| 4440 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4441 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_5_4 AND _mux0009(4)72)
|
| 4442 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4443 |
|
|
<br/> NOT state(1) AND state(0) AND N_PZ_1129 AND regfil_5_4 AND NOT alures(4))
|
| 4444 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4445 |
|
|
<br/> NOT state(1) AND state(0) AND N_PZ_1129 AND NOT regfil_5_4 AND alures(4)));
|
| 4446 |
|
|
</td></tr><tr><td>
|
| 4447 |
|
|
FTCPE_regfil_5_5: FTCPE port map (regfil_5_5,regfil_5_5_T,clock,'0','0','1');
|
| 4448 |
|
|
<br/> regfil_5_5_T <= ((data(5).PIN AND N_PZ_1062 AND NOT regfil_5_5)
|
| 4449 |
|
|
<br/> OR (NOT data(5).PIN AND N_PZ_1062 AND regfil_5_5)
|
| 4450 |
|
|
<br/> OR (N_PZ_2114 AND NOT regfil_5_5 AND regfil_3_5)
|
| 4451 |
|
|
<br/> OR (regfil_5_5 AND NOT _mux0009(5)72 AND N_PZ_1100)
|
| 4452 |
|
|
<br/> OR (NOT regfil_5_5 AND NOT _COND_18(5) AND N_PZ_2196)
|
| 4453 |
|
|
<br/> OR (N_PZ_2114 AND regfil_5_5 AND NOT _mux0009(5)72 AND
|
| 4454 |
|
|
<br/> NOT regfil_3_5)
|
| 4455 |
|
|
<br/> OR (regfil_5_5 AND NOT _mux0009(5)72 AND _COND_18(5) AND
|
| 4456 |
|
|
<br/> N_PZ_2196)
|
| 4457 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4458 |
|
|
<br/> NOT state(1) AND NOT state(0) AND addrhold(5) AND NOT regfil_5_5)
|
| 4459 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4460 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT addrhold(5) AND regfil_5_5)
|
| 4461 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4462 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_5_5 AND _mux0009(5)72)
|
| 4463 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4464 |
|
|
<br/> NOT state(1) AND state(0) AND N_PZ_1129 AND regfil_5_5 AND NOT alures(5))
|
| 4465 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4466 |
|
|
<br/> NOT state(1) AND state(0) AND N_PZ_1129 AND NOT regfil_5_5 AND alures(5)));
|
| 4467 |
|
|
</td></tr><tr><td>
|
| 4468 |
|
|
FTCPE_regfil_5_6: FTCPE port map (regfil_5_6,regfil_5_6_T,clock,'0','0','1');
|
| 4469 |
|
|
<br/> regfil_5_6_T <= ((data(6).PIN AND N_PZ_1062 AND NOT regfil_5_6)
|
| 4470 |
|
|
<br/> OR (NOT data(6).PIN AND N_PZ_1062 AND regfil_5_6)
|
| 4471 |
|
|
<br/> OR (N_PZ_2114 AND regfil_3_6 AND NOT regfil_5_6)
|
| 4472 |
|
|
<br/> OR (N_PZ_1129 AND NOT regfil_5_6 AND N_PZ_1888)
|
| 4473 |
|
|
<br/> OR (regfil_5_6 AND NOT _mux0009(6)72 AND N_PZ_1100)
|
| 4474 |
|
|
<br/> OR (N_PZ_2114 AND NOT regfil_3_6 AND regfil_5_6 AND
|
| 4475 |
|
|
<br/> NOT _mux0009(6)72)
|
| 4476 |
|
|
<br/> OR (regfil_5_6 AND NOT _mux0009(6)72 AND _COND_18(6) AND
|
| 4477 |
|
|
<br/> N_PZ_2196)
|
| 4478 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4479 |
|
|
<br/> NOT state(1) AND NOT state(0) AND addrhold(6) AND NOT regfil_5_6)
|
| 4480 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4481 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT addrhold(6) AND regfil_5_6)
|
| 4482 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4483 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_5_6 AND _mux0009(6)72)
|
| 4484 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4485 |
|
|
<br/> NOT state(1) AND state(0) AND N_PZ_1129 AND regfil_5_6 AND NOT alures(6)));
|
| 4486 |
|
|
</td></tr><tr><td>
|
| 4487 |
|
|
FTCPE_regfil_5_7: FTCPE port map (regfil_5_7,regfil_5_7_T,clock,'0','0','1');
|
| 4488 |
|
|
<br/> regfil_5_7_T <= ((data(7).PIN AND NOT regfil_5_7 AND N_PZ_1062)
|
| 4489 |
|
|
<br/> OR (NOT data(7).PIN AND regfil_5_7 AND N_PZ_1062)
|
| 4490 |
|
|
<br/> OR (NOT _COND_18(7) AND NOT regfil_5_7 AND N_PZ_2196)
|
| 4491 |
|
|
<br/> OR (regfil_5_7 AND N_PZ_1100 AND NOT _mux0009(7)72)
|
| 4492 |
|
|
<br/> OR (NOT regfil_5_7 AND N_PZ_2114 AND regfil_3_7)
|
| 4493 |
|
|
<br/> OR (_COND_18(7) AND regfil_5_7 AND N_PZ_2196 AND
|
| 4494 |
|
|
<br/> NOT _mux0009(7)72)
|
| 4495 |
|
|
<br/> OR (regfil_5_7 AND N_PZ_2114 AND NOT regfil_3_7 AND
|
| 4496 |
|
|
<br/> NOT _mux0009(7)72)
|
| 4497 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4498 |
|
|
<br/> NOT state(1) AND NOT state(0) AND regfil_5_7 AND NOT addrhold(7))
|
| 4499 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 4500 |
|
|
<br/> NOT state(1) AND NOT state(0) AND NOT regfil_5_7 AND addrhold(7))
|
| 4501 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4502 |
|
|
<br/> state(1) AND NOT state(0) AND NOT regfil_5_7 AND _mux0009(7)72)
|
| 4503 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4504 |
|
|
<br/> NOT state(1) AND state(0) AND regfil_5_7 AND N_PZ_1129 AND NOT alures(7))
|
| 4505 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4506 |
|
|
<br/> NOT state(1) AND state(0) AND NOT regfil_5_7 AND N_PZ_1129 AND alures(7)));
|
| 4507 |
|
|
</td></tr><tr><td>
|
| 4508 |
|
|
FDCPE_regfil_6_0: FDCPE port map (regfil_6_0,regfil_6_0_D,clock,'0','0','1');
|
| 4509 |
|
|
<br/> regfil_6_0_D <= ((NOT N_PZ_2186 AND regfil_6_0)
|
| 4510 |
|
|
<br/> OR (NOT N_PZ_1268 AND N_PZ_1996 AND regfil_6_0)
|
| 4511 |
|
|
<br/> OR (regd(2) AND regd(1) AND NOT regd(0) AND NOT N_PZ_1268 AND
|
| 4512 |
|
|
<br/> N_PZ_1996 AND NOT regfil_6_0));
|
| 4513 |
|
|
</td></tr><tr><td>
|
| 4514 |
|
|
FTCPE_regfil_6_1: FTCPE port map (regfil_6_1,regfil_6_1_T,clock,'0','0','1');
|
| 4515 |
|
|
<br/> regfil_6_1_T <= ((NOT N_PZ_1262 AND N_PZ_2186 AND regfil_6_1)
|
| 4516 |
|
|
<br/> OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1262 AND
|
| 4517 |
|
|
<br/> NOT regfil_6_1));
|
| 4518 |
|
|
</td></tr><tr><td>
|
| 4519 |
|
|
FTCPE_regfil_6_2: FTCPE port map (regfil_6_2,regfil_6_2_T,clock,'0','0','1');
|
| 4520 |
|
|
<br/> regfil_6_2_T <= ((regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1945 AND
|
| 4521 |
|
|
<br/> regfil_6_2)
|
| 4522 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND NOT state(4) AND
|
| 4523 |
|
|
<br/> NOT state(1) AND state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND
|
| 4524 |
|
|
<br/> alures(2) AND NOT regfil_6_2)
|
| 4525 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 4526 |
|
|
<br/> NOT state(1) AND state(0) AND data(2).PIN AND regd(2) AND regd(1) AND
|
| 4527 |
|
|
<br/> NOT regd(0) AND NOT regfil_6_2)
|
| 4528 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4529 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4530 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND NOT regd(0) AND NOT N_PZ_1373 AND NOT _COND_18(2) AND
|
| 4531 |
|
|
<br/> NOT regfil_6_2));
|
| 4532 |
|
|
</td></tr><tr><td>
|
| 4533 |
|
|
FTCPE_regfil_6_3: FTCPE port map (regfil_6_3,regfil_6_3_T,clock,'0','0','1');
|
| 4534 |
|
|
<br/> regfil_6_3_T <= ((regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1943 AND
|
| 4535 |
|
|
<br/> NOT regfil_6_3)
|
| 4536 |
|
|
<br/> OR (NOT reset AND state(2) AND NOT state(4) AND NOT state(1) AND
|
| 4537 |
|
|
<br/> state(0) AND regd(2) AND regd(1) AND NOT regd(0) AND NOT N_PZ_1943 AND
|
| 4538 |
|
|
<br/> regfil_6_3)
|
| 4539 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4540 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 4541 |
|
|
<br/> NOT _cmp_eq0004 AND NOT N_PZ_1373 AND NOT N_PZ_1943 AND regfil_6_3 AND N_PZ_1921));
|
| 4542 |
|
|
</td></tr><tr><td>
|
| 4543 |
|
|
FDCPE_regfil_6_4: FDCPE port map (regfil_6_4,regfil_6_4_D,clock,'0','0','1');
|
| 4544 |
|
|
<br/> regfil_6_4_D <= ((NOT N_PZ_2186 AND regfil_6_4)
|
| 4545 |
|
|
<br/> OR (N_PZ_1996 AND NOT N_PZ_2181 AND regfil_6_4)
|
| 4546 |
|
|
<br/> OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1996 AND
|
| 4547 |
|
|
<br/> NOT N_PZ_2181 AND NOT regfil_6_4));
|
| 4548 |
|
|
</td></tr><tr><td>
|
| 4549 |
|
|
FTCPE_regfil_6_5: FTCPE port map (regfil_6_5,regfil_6_5_T,clock,'0','0','1');
|
| 4550 |
|
|
<br/> regfil_6_5_T <= ((NOT N_PZ_1265 AND regfil_6_5 AND N_PZ_2186)
|
| 4551 |
|
|
<br/> OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1265 AND
|
| 4552 |
|
|
<br/> NOT regfil_6_5));
|
| 4553 |
|
|
</td></tr><tr><td>
|
| 4554 |
|
|
FTCPE_regfil_6_6: FTCPE port map (regfil_6_6,regfil_6_6_T,clock,'0','0','1');
|
| 4555 |
|
|
<br/> regfil_6_6_T <= ((regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1888 AND
|
| 4556 |
|
|
<br/> NOT regfil_6_6)
|
| 4557 |
|
|
<br/> OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_2106 AND
|
| 4558 |
|
|
<br/> regfil_6_6)
|
| 4559 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 4560 |
|
|
<br/> NOT state(1) AND state(0) AND data(6).PIN AND regd(2) AND regd(1) AND
|
| 4561 |
|
|
<br/> NOT regd(0) AND NOT regfil_6_6));
|
| 4562 |
|
|
</td></tr><tr><td>
|
| 4563 |
|
|
FTCPE_regfil_6_7: FTCPE port map (regfil_6_7,regfil_6_7_T,clock,'0','0','1');
|
| 4564 |
|
|
<br/> regfil_6_7_T <= ((NOT N_PZ_1266 AND N_PZ_2186 AND regfil_6_7)
|
| 4565 |
|
|
<br/> OR (regd(2) AND regd(1) AND NOT regd(0) AND N_PZ_1266 AND
|
| 4566 |
|
|
<br/> NOT regfil_6_7));
|
| 4567 |
|
|
</td></tr><tr><td>
|
| 4568 |
|
|
FTCPE_regfil_7_0: FTCPE port map (regfil_7_0,regfil_7_0_T,clock,'0','0','1');
|
| 4569 |
|
|
<br/> regfil_7_0_T <= ((regfil_7_0 AND NOT alures(0) AND N_PZ_1060)
|
| 4570 |
|
|
<br/> OR (NOT regfil_7_0 AND alures(0) AND N_PZ_1060)
|
| 4571 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 4572 |
|
|
<br/> NOT state(1) AND state(0) AND data(0).PIN AND regd(2) AND regd(1) AND
|
| 4573 |
|
|
<br/> regd(0) AND NOT regfil_7_0)
|
| 4574 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 4575 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(0).PIN AND regd(2) AND regd(1) AND
|
| 4576 |
|
|
<br/> regd(0) AND regfil_7_0)
|
| 4577 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4578 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4579 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4580 |
|
|
<br/> N_PZ_1819)
|
| 4581 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4582 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 4583 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND
|
| 4584 |
|
|
<br/> holding(0) AND NOT regfil_7_0)
|
| 4585 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4586 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 4587 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND
|
| 4588 |
|
|
<br/> NOT holding(0) AND regfil_7_0)
|
| 4589 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4590 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4591 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4592 |
|
|
<br/> NOT data(5).PIN AND regfil_7_0 AND NOT regfil_7_1)
|
| 4593 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4594 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4595 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4596 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_7_0 AND regfil_7_1)
|
| 4597 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4598 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4599 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND regd(0) AND regfil_7_0 AND _COND_18(0) AND
|
| 4600 |
|
|
<br/> NOT N_PZ_1373)
|
| 4601 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4602 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4603 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT regfil_7_0 AND NOT _COND_18(0) AND
|
| 4604 |
|
|
<br/> NOT N_PZ_1373)
|
| 4605 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4606 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 4607 |
|
|
<br/> data(2).PIN AND data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 4608 |
|
|
<br/> NOT data(7).PIN AND NOT data(5).PIN AND carry AND NOT regfil_7_0)
|
| 4609 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4610 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 4611 |
|
|
<br/> data(2).PIN AND data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 4612 |
|
|
<br/> NOT data(7).PIN AND NOT data(5).PIN AND NOT carry AND regfil_7_0)
|
| 4613 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4614 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(3).PIN AND
|
| 4615 |
|
|
<br/> data(2).PIN AND data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 4616 |
|
|
<br/> NOT data(7).PIN AND NOT data(5).PIN AND regfil_7_0 AND NOT regfil_7_7)
|
| 4617 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4618 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND NOT data(3).PIN AND
|
| 4619 |
|
|
<br/> data(2).PIN AND data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 4620 |
|
|
<br/> NOT data(7).PIN AND NOT data(5).PIN AND NOT regfil_7_0 AND regfil_7_7));
|
| 4621 |
|
|
</td></tr><tr><td>
|
| 4622 |
|
|
FTCPE_regfil_7_1: FTCPE port map (regfil_7_1,regfil_7_1_T,clock,'0','0','1');
|
| 4623 |
|
|
<br/> regfil_7_1_T <= ((regfil_7_1 AND NOT alures(1) AND N_PZ_1060)
|
| 4624 |
|
|
<br/> OR (NOT regfil_7_1 AND alures(1) AND N_PZ_1060)
|
| 4625 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 4626 |
|
|
<br/> NOT state(1) AND state(0) AND data(1).PIN AND regd(2) AND regd(1) AND
|
| 4627 |
|
|
<br/> regd(0) AND NOT regfil_7_1)
|
| 4628 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 4629 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(1).PIN AND regd(2) AND regd(1) AND
|
| 4630 |
|
|
<br/> regd(0) AND regfil_7_1)
|
| 4631 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4632 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4633 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4634 |
|
|
<br/> N_PZ_1819)
|
| 4635 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4636 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4637 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4638 |
|
|
<br/> NOT data(5).PIN AND N_PZ_1890)
|
| 4639 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4640 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 4641 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND
|
| 4642 |
|
|
<br/> regfil_7_1 AND NOT holding(1))
|
| 4643 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4644 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 4645 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND
|
| 4646 |
|
|
<br/> NOT regfil_7_1 AND holding(1))
|
| 4647 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4648 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 4649 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4650 |
|
|
<br/> NOT data(5).PIN AND regfil_7_0 AND NOT regfil_7_1)
|
| 4651 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4652 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 4653 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4654 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_7_0 AND regfil_7_1)
|
| 4655 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4656 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4657 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND regd(0) AND regfil_7_1 AND NOT N_PZ_1373 AND
|
| 4658 |
|
|
<br/> _COND_18(1))
|
| 4659 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4660 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4661 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT regfil_7_1 AND NOT N_PZ_1373 AND
|
| 4662 |
|
|
<br/> NOT _COND_18(1)));
|
| 4663 |
|
|
</td></tr><tr><td>
|
| 4664 |
|
|
FTCPE_regfil_7_2: FTCPE port map (regfil_7_2,regfil_7_2_T,clock,'0','0','1');
|
| 4665 |
|
|
<br/> regfil_7_2_T <= ((regfil_7_2 AND NOT alures(2) AND N_PZ_1060)
|
| 4666 |
|
|
<br/> OR (NOT regfil_7_2 AND alures(2) AND N_PZ_1060)
|
| 4667 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 4668 |
|
|
<br/> NOT state(1) AND state(0) AND data(2).PIN AND regd(2) AND regd(1) AND
|
| 4669 |
|
|
<br/> regd(0) AND NOT regfil_7_2)
|
| 4670 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 4671 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(2).PIN AND regd(2) AND regd(1) AND
|
| 4672 |
|
|
<br/> regd(0) AND regfil_7_2)
|
| 4673 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4674 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4675 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4676 |
|
|
<br/> N_PZ_1819)
|
| 4677 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4678 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 4679 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4680 |
|
|
<br/> NOT data(5).PIN AND N_PZ_1890)
|
| 4681 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4682 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 4683 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND
|
| 4684 |
|
|
<br/> regfil_7_2 AND NOT holding(2))
|
| 4685 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4686 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 4687 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND
|
| 4688 |
|
|
<br/> NOT regfil_7_2 AND holding(2))
|
| 4689 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4690 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4691 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4692 |
|
|
<br/> NOT data(5).PIN AND regfil_7_3 AND NOT regfil_7_2)
|
| 4693 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4694 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4695 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4696 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_7_3 AND regfil_7_2)
|
| 4697 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4698 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4699 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND regd(0) AND regfil_7_2 AND NOT N_PZ_1373 AND
|
| 4700 |
|
|
<br/> _COND_18(2))
|
| 4701 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4702 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4703 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT regfil_7_2 AND NOT N_PZ_1373 AND
|
| 4704 |
|
|
<br/> NOT _COND_18(2)));
|
| 4705 |
|
|
</td></tr><tr><td>
|
| 4706 |
|
|
FTCPE_regfil_7_3: FTCPE port map (regfil_7_3,regfil_7_3_T,clock,'0','0','1');
|
| 4707 |
|
|
<br/> regfil_7_3_T <= ((regfil_7_3 AND NOT alures(3) AND N_PZ_1060)
|
| 4708 |
|
|
<br/> OR (NOT regfil_7_3 AND alures(3) AND N_PZ_1060)
|
| 4709 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 4710 |
|
|
<br/> NOT state(1) AND state(0) AND data(3).PIN AND regd(2) AND regd(1) AND
|
| 4711 |
|
|
<br/> regd(0) AND NOT regfil_7_3)
|
| 4712 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 4713 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(3).PIN AND regd(2) AND regd(1) AND
|
| 4714 |
|
|
<br/> regd(0) AND regfil_7_3)
|
| 4715 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4716 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4717 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4718 |
|
|
<br/> N_PZ_1819)
|
| 4719 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4720 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 4721 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND
|
| 4722 |
|
|
<br/> regfil_7_3 AND NOT holding(3))
|
| 4723 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4724 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 4725 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND
|
| 4726 |
|
|
<br/> NOT regfil_7_3 AND holding(3))
|
| 4727 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4728 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4729 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4730 |
|
|
<br/> NOT data(5).PIN AND regfil_7_3 AND NOT regfil_7_4)
|
| 4731 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4732 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4733 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4734 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_7_3 AND regfil_7_4)
|
| 4735 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4736 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 4737 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4738 |
|
|
<br/> NOT data(5).PIN AND regfil_7_3 AND NOT regfil_7_2)
|
| 4739 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4740 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 4741 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4742 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_7_3 AND regfil_7_2)
|
| 4743 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4744 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4745 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND regd(0) AND regfil_7_3 AND NOT N_PZ_1373 AND
|
| 4746 |
|
|
<br/> _COND_18(3))
|
| 4747 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4748 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4749 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT regfil_7_3 AND NOT N_PZ_1373 AND
|
| 4750 |
|
|
<br/> NOT _COND_18(3)));
|
| 4751 |
|
|
</td></tr><tr><td>
|
| 4752 |
|
|
FTCPE_regfil_7_4: FTCPE port map (regfil_7_4,regfil_7_4_T,clock,'0','0','1');
|
| 4753 |
|
|
<br/> regfil_7_4_T <= ((regfil_7_4 AND NOT alures(4) AND N_PZ_1060)
|
| 4754 |
|
|
<br/> OR (NOT regfil_7_4 AND alures(4) AND N_PZ_1060)
|
| 4755 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 4756 |
|
|
<br/> NOT state(1) AND state(0) AND data(4).PIN AND regd(2) AND regd(1) AND
|
| 4757 |
|
|
<br/> regd(0) AND NOT regfil_7_4)
|
| 4758 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 4759 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(4).PIN AND regd(2) AND regd(1) AND
|
| 4760 |
|
|
<br/> regd(0) AND regfil_7_4)
|
| 4761 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4762 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4763 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4764 |
|
|
<br/> N_PZ_1819)
|
| 4765 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4766 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 4767 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND
|
| 4768 |
|
|
<br/> holding(4) AND NOT regfil_7_4)
|
| 4769 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4770 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 4771 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND
|
| 4772 |
|
|
<br/> NOT holding(4) AND regfil_7_4)
|
| 4773 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4774 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4775 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4776 |
|
|
<br/> NOT data(5).PIN AND regfil_7_4 AND NOT regfil_7_5)
|
| 4777 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4778 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4779 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4780 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_7_4 AND regfil_7_5)
|
| 4781 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4782 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 4783 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4784 |
|
|
<br/> NOT data(5).PIN AND regfil_7_3 AND NOT regfil_7_4)
|
| 4785 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4786 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 4787 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4788 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_7_3 AND regfil_7_4)
|
| 4789 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4790 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4791 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT N_PZ_1373 AND regfil_7_4 AND
|
| 4792 |
|
|
<br/> _COND_18(4))
|
| 4793 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4794 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4795 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT N_PZ_1373 AND NOT regfil_7_4 AND
|
| 4796 |
|
|
<br/> NOT _COND_18(4)));
|
| 4797 |
|
|
</td></tr><tr><td>
|
| 4798 |
|
|
FTCPE_regfil_7_5: FTCPE port map (regfil_7_5,regfil_7_5_T,clock,'0','0','1');
|
| 4799 |
|
|
<br/> regfil_7_5_T <= ((regfil_7_5 AND NOT alures(5) AND N_PZ_1060)
|
| 4800 |
|
|
<br/> OR (NOT regfil_7_5 AND alures(5) AND N_PZ_1060)
|
| 4801 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 4802 |
|
|
<br/> NOT state(1) AND state(0) AND data(5).PIN AND regd(2) AND regd(1) AND
|
| 4803 |
|
|
<br/> regd(0) AND NOT regfil_7_5)
|
| 4804 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 4805 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(5).PIN AND regd(2) AND regd(1) AND
|
| 4806 |
|
|
<br/> regd(0) AND regfil_7_5)
|
| 4807 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4808 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4809 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4810 |
|
|
<br/> N_PZ_1819)
|
| 4811 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4812 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 4813 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND
|
| 4814 |
|
|
<br/> regfil_7_5 AND NOT holding(5))
|
| 4815 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4816 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 4817 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND
|
| 4818 |
|
|
<br/> NOT regfil_7_5 AND holding(5))
|
| 4819 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4820 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4821 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4822 |
|
|
<br/> NOT data(5).PIN AND regfil_7_5 AND NOT regfil_7_6)
|
| 4823 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4824 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4825 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4826 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_7_5 AND regfil_7_6)
|
| 4827 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4828 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 4829 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4830 |
|
|
<br/> NOT data(5).PIN AND regfil_7_4 AND NOT regfil_7_5)
|
| 4831 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4832 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 4833 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4834 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_7_4 AND regfil_7_5)
|
| 4835 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4836 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4837 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT N_PZ_1373 AND regfil_7_5 AND
|
| 4838 |
|
|
<br/> _COND_18(5))
|
| 4839 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4840 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4841 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT N_PZ_1373 AND NOT regfil_7_5 AND
|
| 4842 |
|
|
<br/> NOT _COND_18(5)));
|
| 4843 |
|
|
</td></tr><tr><td>
|
| 4844 |
|
|
FTCPE_regfil_7_6: FTCPE port map (regfil_7_6,regfil_7_6_T,clock,'0','0','1');
|
| 4845 |
|
|
<br/> regfil_7_6_T <= ((regfil_7_6 AND NOT alures(6) AND N_PZ_1060)
|
| 4846 |
|
|
<br/> OR (NOT regfil_7_6 AND alures(6) AND N_PZ_1060)
|
| 4847 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 4848 |
|
|
<br/> NOT state(1) AND state(0) AND data(6).PIN AND regd(2) AND regd(1) AND
|
| 4849 |
|
|
<br/> regd(0) AND NOT regfil_7_6)
|
| 4850 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 4851 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(6).PIN AND regd(2) AND regd(1) AND
|
| 4852 |
|
|
<br/> regd(0) AND regfil_7_6)
|
| 4853 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4854 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4855 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4856 |
|
|
<br/> N_PZ_1819)
|
| 4857 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4858 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 4859 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND
|
| 4860 |
|
|
<br/> regfil_7_6 AND NOT holding(6))
|
| 4861 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4862 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 4863 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND
|
| 4864 |
|
|
<br/> NOT regfil_7_6 AND holding(6))
|
| 4865 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4866 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4867 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4868 |
|
|
<br/> NOT data(5).PIN AND regfil_7_6 AND NOT regfil_7_7)
|
| 4869 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4870 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4871 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4872 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_7_6 AND regfil_7_7)
|
| 4873 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4874 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 4875 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4876 |
|
|
<br/> NOT data(5).PIN AND regfil_7_5 AND NOT regfil_7_6)
|
| 4877 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4878 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 4879 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4880 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_7_5 AND regfil_7_6)
|
| 4881 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4882 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4883 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT N_PZ_1373 AND regfil_7_6 AND
|
| 4884 |
|
|
<br/> _COND_18(6))
|
| 4885 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4886 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4887 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT N_PZ_1373 AND NOT regfil_7_6 AND
|
| 4888 |
|
|
<br/> NOT _COND_18(6)));
|
| 4889 |
|
|
</td></tr><tr><td>
|
| 4890 |
|
|
FTCPE_regfil_7_7: FTCPE port map (regfil_7_7,regfil_7_7_T,clock,'0','0','1');
|
| 4891 |
|
|
<br/> regfil_7_7_T <= ((regfil_7_7 AND NOT alures(7) AND N_PZ_1060)
|
| 4892 |
|
|
<br/> OR (NOT regfil_7_7 AND alures(7) AND N_PZ_1060)
|
| 4893 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 4894 |
|
|
<br/> NOT state(1) AND state(0) AND data(7).PIN AND regd(2) AND regd(1) AND
|
| 4895 |
|
|
<br/> regd(0) AND NOT regfil_7_7)
|
| 4896 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 4897 |
|
|
<br/> NOT state(1) AND state(0) AND NOT data(7).PIN AND regd(2) AND regd(1) AND
|
| 4898 |
|
|
<br/> regd(0) AND regfil_7_7)
|
| 4899 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4900 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND data(2).PIN AND
|
| 4901 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4902 |
|
|
<br/> N_PZ_1819)
|
| 4903 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4904 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 4905 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND
|
| 4906 |
|
|
<br/> regfil_7_7 AND NOT holding(7))
|
| 4907 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4908 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 4909 |
|
|
<br/> data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND
|
| 4910 |
|
|
<br/> NOT regfil_7_7 AND holding(7))
|
| 4911 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4912 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND data(3).PIN AND
|
| 4913 |
|
|
<br/> data(2).PIN AND data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 4914 |
|
|
<br/> NOT data(7).PIN AND regfil_7_0 AND NOT regfil_7_7)
|
| 4915 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4916 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(4).PIN AND data(3).PIN AND
|
| 4917 |
|
|
<br/> data(2).PIN AND data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 4918 |
|
|
<br/> NOT data(7).PIN AND NOT regfil_7_0 AND regfil_7_7)
|
| 4919 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4920 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 4921 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4922 |
|
|
<br/> NOT data(5).PIN AND regfil_7_6 AND NOT regfil_7_7)
|
| 4923 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4924 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND data(2).PIN AND
|
| 4925 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4926 |
|
|
<br/> NOT data(5).PIN AND NOT regfil_7_6 AND regfil_7_7)
|
| 4927 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4928 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4929 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND regd(0) AND _COND_18(7) AND NOT N_PZ_1373 AND
|
| 4930 |
|
|
<br/> regfil_7_7)
|
| 4931 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4932 |
|
|
<br/> state(1) AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND regd(2) AND
|
| 4933 |
|
|
<br/> NOT _cmp_eq0004 AND regd(1) AND regd(0) AND NOT _COND_18(7) AND NOT N_PZ_1373 AND
|
| 4934 |
|
|
<br/> NOT regfil_7_7)
|
| 4935 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4936 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 4937 |
|
|
<br/> data(2).PIN AND data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 4938 |
|
|
<br/> NOT data(7).PIN AND NOT data(5).PIN AND carry AND NOT regfil_7_7)
|
| 4939 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4940 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 4941 |
|
|
<br/> data(2).PIN AND data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND
|
| 4942 |
|
|
<br/> NOT data(7).PIN AND NOT data(5).PIN AND NOT carry AND regfil_7_7));
|
| 4943 |
|
|
</td></tr><tr><td>
|
| 4944 |
|
|
FTCPE_regs0: FTCPE port map (regs(0),regs_T(0),clock,'0','0','1');
|
| 4945 |
|
|
<br/> regs_T(0) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4946 |
|
|
<br/> state(1) AND NOT state(0) AND data(0).PIN AND data(6).PIN AND
|
| 4947 |
|
|
<br/> NOT data(7).PIN AND NOT regs(0))
|
| 4948 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4949 |
|
|
<br/> state(1) AND NOT state(0) AND data(0).PIN AND NOT data(6).PIN AND
|
| 4950 |
|
|
<br/> data(7).PIN AND NOT regs(0))
|
| 4951 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4952 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(0).PIN AND NOT data(6).PIN AND
|
| 4953 |
|
|
<br/> data(7).PIN AND regs(0))
|
| 4954 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4955 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(0).PIN AND data(6).PIN AND
|
| 4956 |
|
|
<br/> NOT data(7).PIN AND NOT _cmp_eq0004 AND regs(0))
|
| 4957 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4958 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 4959 |
|
|
<br/> data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND
|
| 4960 |
|
|
<br/> data(5).PIN AND regs(0))
|
| 4961 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4962 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND
|
| 4963 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 4964 |
|
|
<br/> NOT N_PZ_1819 AND NOT regs(0)));
|
| 4965 |
|
|
</td></tr><tr><td>
|
| 4966 |
|
|
FTCPE_regs1: FTCPE port map (regs(1),regs_T(1),clock,'0','0','1');
|
| 4967 |
|
|
<br/> regs_T(1) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4968 |
|
|
<br/> state(1) AND NOT state(0) AND data(1).PIN AND NOT data(6).PIN AND
|
| 4969 |
|
|
<br/> data(7).PIN AND NOT regs(1))
|
| 4970 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4971 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(1).PIN AND NOT data(6).PIN AND
|
| 4972 |
|
|
<br/> data(7).PIN AND regs(1))
|
| 4973 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4974 |
|
|
<br/> state(1) AND NOT state(0) AND data(1).PIN AND data(6).PIN AND
|
| 4975 |
|
|
<br/> NOT data(7).PIN AND NOT _cmp_eq0004 AND NOT regs(1))
|
| 4976 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4977 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(1).PIN AND data(6).PIN AND
|
| 4978 |
|
|
<br/> NOT data(7).PIN AND NOT _cmp_eq0004 AND regs(1))
|
| 4979 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4980 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 4981 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND data(5).PIN AND
|
| 4982 |
|
|
<br/> NOT regs(1))
|
| 4983 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4984 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND
|
| 4985 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(5).PIN AND
|
| 4986 |
|
|
<br/> NOT regs(1)));
|
| 4987 |
|
|
</td></tr><tr><td>
|
| 4988 |
|
|
FTCPE_regs2: FTCPE port map (regs(2),regs_T(2),clock,'0','0','1');
|
| 4989 |
|
|
<br/> regs_T(2) <= ((NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4990 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND NOT data(6).PIN AND
|
| 4991 |
|
|
<br/> data(7).PIN AND NOT regs(2))
|
| 4992 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4993 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(2).PIN AND NOT data(6).PIN AND
|
| 4994 |
|
|
<br/> data(7).PIN AND regs(2))
|
| 4995 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4996 |
|
|
<br/> state(1) AND NOT state(0) AND data(2).PIN AND data(6).PIN AND
|
| 4997 |
|
|
<br/> NOT data(7).PIN AND NOT _cmp_eq0004 AND NOT regs(2))
|
| 4998 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 4999 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(2).PIN AND data(6).PIN AND
|
| 5000 |
|
|
<br/> NOT data(7).PIN AND NOT _cmp_eq0004 AND regs(2))
|
| 5001 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5002 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 5003 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5004 |
|
|
<br/> data(5).PIN AND NOT regs(2))
|
| 5005 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5006 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND
|
| 5007 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5008 |
|
|
<br/> NOT data(5).PIN AND NOT regs(2)));
|
| 5009 |
|
|
</td></tr><tr><td>
|
| 5010 |
|
|
FDCPE_sign: FDCPE port map (sign,sign_D,clock,'0','0','1');
|
| 5011 |
|
|
<br/> sign_D <= ((N_PZ_1894 AND alures(7))
|
| 5012 |
|
|
<br/> OR (NOT N_PZ_1894 AND sign));
|
| 5013 |
|
|
</td></tr><tr><td>
|
| 5014 |
|
|
FTCPE_sp0: FTCPE port map (sp(0),sp_T(0),clock,'0','0','1');
|
| 5015 |
|
|
<br/> sp_T(0) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5016 |
|
|
<br/> NOT state(1) AND state(0) AND addrhold(0) AND NOT sp(0))
|
| 5017 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5018 |
|
|
<br/> NOT state(1) AND state(0) AND NOT addrhold(0) AND sp(0))
|
| 5019 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5020 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 5021 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5022 |
|
|
<br/> data(5).PIN)
|
| 5023 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5024 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5025 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5026 |
|
|
<br/> data(7).PIN AND data(5).PIN AND regfil_5_0 AND NOT sp(0))
|
| 5027 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5028 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5029 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5030 |
|
|
<br/> data(7).PIN AND data(5).PIN AND NOT regfil_5_0 AND sp(0)));
|
| 5031 |
|
|
</td></tr><tr><td>
|
| 5032 |
|
|
FTCPE_sp1: FTCPE port map (sp(1),sp_T(1),clock,'0','0','1');
|
| 5033 |
|
|
<br/> sp_T(1) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5034 |
|
|
<br/> NOT state(1) AND state(0) AND addrhold(1) AND NOT sp(1))
|
| 5035 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5036 |
|
|
<br/> NOT state(1) AND state(0) AND NOT addrhold(1) AND sp(1))
|
| 5037 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5038 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 5039 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5040 |
|
|
<br/> data(5).PIN AND sp(0))
|
| 5041 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5042 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5043 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5044 |
|
|
<br/> data(7).PIN AND data(5).PIN AND regfil_5_1 AND NOT sp(1))
|
| 5045 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5046 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5047 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5048 |
|
|
<br/> data(7).PIN AND data(5).PIN AND NOT regfil_5_1 AND sp(1)));
|
| 5049 |
|
|
</td></tr><tr><td>
|
| 5050 |
|
|
FTCPE_sp2: FTCPE port map (sp(2),sp_T(2),clock,'0','0','1');
|
| 5051 |
|
|
<br/> sp_T(2) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5052 |
|
|
<br/> NOT state(1) AND state(0) AND addrhold(2) AND NOT sp(2))
|
| 5053 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5054 |
|
|
<br/> NOT state(1) AND state(0) AND NOT addrhold(2) AND sp(2))
|
| 5055 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5056 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 5057 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5058 |
|
|
<br/> data(5).PIN AND sp(0) AND sp(1))
|
| 5059 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5060 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5061 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5062 |
|
|
<br/> data(7).PIN AND data(5).PIN AND regfil_5_2 AND NOT sp(2))
|
| 5063 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5064 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5065 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5066 |
|
|
<br/> data(7).PIN AND data(5).PIN AND NOT regfil_5_2 AND sp(2)));
|
| 5067 |
|
|
</td></tr><tr><td>
|
| 5068 |
|
|
FTCPE_sp3: FTCPE port map (sp(3),sp_T(3),clock,'0','0','1');
|
| 5069 |
|
|
<br/> sp_T(3) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5070 |
|
|
<br/> NOT state(1) AND state(0) AND addrhold(3) AND NOT sp(3))
|
| 5071 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5072 |
|
|
<br/> NOT state(1) AND state(0) AND NOT addrhold(3) AND sp(3))
|
| 5073 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5074 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5075 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5076 |
|
|
<br/> data(7).PIN AND data(5).PIN AND regfil_5_3 AND NOT sp(3))
|
| 5077 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5078 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5079 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5080 |
|
|
<br/> data(7).PIN AND data(5).PIN AND NOT regfil_5_3 AND sp(3))
|
| 5081 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5082 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 5083 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5084 |
|
|
<br/> data(5).PIN AND sp(2) AND sp(0) AND sp(1)));
|
| 5085 |
|
|
</td></tr><tr><td>
|
| 5086 |
|
|
FTCPE_sp4: FTCPE port map (sp(4),sp_T(4),clock,'0','0','1');
|
| 5087 |
|
|
<br/> sp_T(4) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5088 |
|
|
<br/> NOT state(1) AND state(0) AND addrhold(4) AND NOT sp(4))
|
| 5089 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5090 |
|
|
<br/> NOT state(1) AND state(0) AND NOT addrhold(4) AND sp(4))
|
| 5091 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5092 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5093 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5094 |
|
|
<br/> data(7).PIN AND data(5).PIN AND N_PZ_2168)
|
| 5095 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5096 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 5097 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5098 |
|
|
<br/> data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(3)));
|
| 5099 |
|
|
</td></tr><tr><td>
|
| 5100 |
|
|
FTCPE_sp5: FTCPE port map (sp(5),sp_T(5),clock,'0','0','1');
|
| 5101 |
|
|
<br/> sp_T(5) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5102 |
|
|
<br/> NOT state(1) AND state(0) AND addrhold(5) AND NOT sp(5))
|
| 5103 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5104 |
|
|
<br/> NOT state(1) AND state(0) AND NOT addrhold(5) AND sp(5))
|
| 5105 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5106 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5107 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5108 |
|
|
<br/> data(7).PIN AND data(5).PIN AND NOT N_PZ_1981)
|
| 5109 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5110 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 5111 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5112 |
|
|
<br/> data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(3) AND sp(4)));
|
| 5113 |
|
|
</td></tr><tr><td>
|
| 5114 |
|
|
FTCPE_sp6: FTCPE port map (sp(6),sp_T(6),clock,'0','0','1');
|
| 5115 |
|
|
<br/> sp_T(6) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5116 |
|
|
<br/> NOT state(1) AND state(0) AND addrhold(6) AND NOT sp(6))
|
| 5117 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5118 |
|
|
<br/> NOT state(1) AND state(0) AND NOT addrhold(6) AND sp(6))
|
| 5119 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5120 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5121 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5122 |
|
|
<br/> data(7).PIN AND data(5).PIN AND N_PZ_2169)
|
| 5123 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5124 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 5125 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5126 |
|
|
<br/> data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4)));
|
| 5127 |
|
|
</td></tr><tr><td>
|
| 5128 |
|
|
FTCPE_sp7: FTCPE port map (sp(7),sp_T(7),clock,'0','0','1');
|
| 5129 |
|
|
<br/> sp_T(7) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5130 |
|
|
<br/> NOT state(1) AND state(0) AND addrhold(7) AND NOT sp(7))
|
| 5131 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5132 |
|
|
<br/> NOT state(1) AND state(0) AND NOT addrhold(7) AND sp(7))
|
| 5133 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5134 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5135 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5136 |
|
|
<br/> data(7).PIN AND data(5).PIN AND NOT N_PZ_1982)
|
| 5137 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5138 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 5139 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5140 |
|
|
<br/> data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4) AND
|
| 5141 |
|
|
<br/> sp(6)));
|
| 5142 |
|
|
</td></tr><tr><td>
|
| 5143 |
|
|
FTCPE_sp8: FTCPE port map (sp(8),sp_T(8),clock,'0','0','1');
|
| 5144 |
|
|
<br/> sp_T(8) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5145 |
|
|
<br/> NOT state(1) AND state(0) AND addrhold(8) AND NOT sp(8))
|
| 5146 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5147 |
|
|
<br/> NOT state(1) AND state(0) AND NOT addrhold(8) AND sp(8))
|
| 5148 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5149 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5150 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5151 |
|
|
<br/> data(7).PIN AND data(5).PIN AND regfil_4_0 AND NOT sp(8))
|
| 5152 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5153 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5154 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5155 |
|
|
<br/> data(7).PIN AND data(5).PIN AND NOT regfil_4_0 AND sp(8))
|
| 5156 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5157 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 5158 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5159 |
|
|
<br/> data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4) AND
|
| 5160 |
|
|
<br/> sp(6) AND sp(7)));
|
| 5161 |
|
|
</td></tr><tr><td>
|
| 5162 |
|
|
FTCPE_sp9: FTCPE port map (sp(9),sp_T(9),clock,'0','0','1');
|
| 5163 |
|
|
<br/> sp_T(9) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5164 |
|
|
<br/> NOT state(1) AND state(0) AND addrhold(9) AND NOT sp(9))
|
| 5165 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5166 |
|
|
<br/> NOT state(1) AND state(0) AND NOT addrhold(9) AND sp(9))
|
| 5167 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5168 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5169 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5170 |
|
|
<br/> data(7).PIN AND data(5).PIN AND regfil_4_1 AND NOT sp(9))
|
| 5171 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5172 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5173 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5174 |
|
|
<br/> data(7).PIN AND data(5).PIN AND NOT regfil_4_1 AND sp(9))
|
| 5175 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5176 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 5177 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5178 |
|
|
<br/> data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4) AND
|
| 5179 |
|
|
<br/> sp(6) AND sp(7) AND sp(8)));
|
| 5180 |
|
|
</td></tr><tr><td>
|
| 5181 |
|
|
FTCPE_sp10: FTCPE port map (sp(10),sp_T(10),clock,'0','0','1');
|
| 5182 |
|
|
<br/> sp_T(10) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5183 |
|
|
<br/> NOT state(1) AND state(0) AND addrhold(10) AND NOT sp(10))
|
| 5184 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5185 |
|
|
<br/> NOT state(1) AND state(0) AND NOT addrhold(10) AND sp(10))
|
| 5186 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5187 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5188 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5189 |
|
|
<br/> data(7).PIN AND data(5).PIN AND regfil_4_2 AND NOT sp(10))
|
| 5190 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5191 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5192 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5193 |
|
|
<br/> data(7).PIN AND data(5).PIN AND NOT regfil_4_2 AND sp(10))
|
| 5194 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5195 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 5196 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5197 |
|
|
<br/> data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4) AND
|
| 5198 |
|
|
<br/> sp(6) AND sp(7) AND sp(8) AND sp(9)));
|
| 5199 |
|
|
</td></tr><tr><td>
|
| 5200 |
|
|
FTCPE_sp11: FTCPE port map (sp(11),sp_T(11),clock,'0','0','1');
|
| 5201 |
|
|
<br/> sp_T(11) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5202 |
|
|
<br/> NOT state(1) AND state(0) AND addrhold(11) AND NOT sp(11))
|
| 5203 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5204 |
|
|
<br/> NOT state(1) AND state(0) AND NOT addrhold(11) AND sp(11))
|
| 5205 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5206 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5207 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5208 |
|
|
<br/> data(7).PIN AND data(5).PIN AND regfil_4_3 AND NOT sp(11))
|
| 5209 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5210 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5211 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5212 |
|
|
<br/> data(7).PIN AND data(5).PIN AND NOT regfil_4_3 AND sp(11))
|
| 5213 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5214 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 5215 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5216 |
|
|
<br/> data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4) AND
|
| 5217 |
|
|
<br/> sp(6) AND sp(10) AND sp(7) AND sp(8) AND sp(9)));
|
| 5218 |
|
|
</td></tr><tr><td>
|
| 5219 |
|
|
FTCPE_sp12: FTCPE port map (sp(12),sp_T(12),clock,'0','0','1');
|
| 5220 |
|
|
<br/> sp_T(12) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5221 |
|
|
<br/> NOT state(1) AND state(0) AND addrhold(12) AND NOT sp(12))
|
| 5222 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5223 |
|
|
<br/> NOT state(1) AND state(0) AND NOT addrhold(12) AND sp(12))
|
| 5224 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5225 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5226 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5227 |
|
|
<br/> data(7).PIN AND data(5).PIN AND NOT N_PZ_1929)
|
| 5228 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5229 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 5230 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5231 |
|
|
<br/> data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4) AND
|
| 5232 |
|
|
<br/> sp(6) AND sp(11) AND sp(10) AND sp(7) AND sp(8) AND sp(9)));
|
| 5233 |
|
|
</td></tr><tr><td>
|
| 5234 |
|
|
FTCPE_sp13: FTCPE port map (sp(13),sp_T(13),clock,'0','0','1');
|
| 5235 |
|
|
<br/> sp_T(13) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5236 |
|
|
<br/> NOT state(1) AND state(0) AND addrhold(13) AND NOT sp(13))
|
| 5237 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5238 |
|
|
<br/> NOT state(1) AND state(0) AND NOT addrhold(13) AND sp(13))
|
| 5239 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5240 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5241 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5242 |
|
|
<br/> data(7).PIN AND data(5).PIN AND NOT N_PZ_1848)
|
| 5243 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5244 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 5245 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5246 |
|
|
<br/> data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4) AND
|
| 5247 |
|
|
<br/> sp(6) AND sp(11) AND sp(10) AND sp(7) AND sp(8) AND sp(9) AND
|
| 5248 |
|
|
<br/> sp(12)));
|
| 5249 |
|
|
</td></tr><tr><td>
|
| 5250 |
|
|
FTCPE_sp14: FTCPE port map (sp(14),sp_T(14),clock,'0','0','1');
|
| 5251 |
|
|
<br/> sp_T(14) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5252 |
|
|
<br/> NOT state(1) AND state(0) AND addrhold(14) AND NOT sp(14))
|
| 5253 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5254 |
|
|
<br/> NOT state(1) AND state(0) AND NOT addrhold(14) AND sp(14))
|
| 5255 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5256 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5257 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5258 |
|
|
<br/> data(7).PIN AND data(5).PIN AND N_PZ_2105)
|
| 5259 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5260 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 5261 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5262 |
|
|
<br/> data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4) AND
|
| 5263 |
|
|
<br/> sp(6) AND sp(11) AND sp(10) AND sp(7) AND sp(8) AND sp(9) AND
|
| 5264 |
|
|
<br/> sp(12) AND sp(13)));
|
| 5265 |
|
|
</td></tr><tr><td>
|
| 5266 |
|
|
FTCPE_sp15: FTCPE port map (sp(15),sp_T(15),clock,'0','0','1');
|
| 5267 |
|
|
<br/> sp_T(15) <= ((NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5268 |
|
|
<br/> NOT state(1) AND state(0) AND sp(15) AND NOT addrhold(15))
|
| 5269 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND state(4) AND
|
| 5270 |
|
|
<br/> NOT state(1) AND state(0) AND NOT sp(15) AND addrhold(15))
|
| 5271 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5272 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5273 |
|
|
<br/> NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND data(6).PIN AND
|
| 5274 |
|
|
<br/> data(7).PIN AND data(5).PIN AND NOT N_PZ_1849)
|
| 5275 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5276 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 5277 |
|
|
<br/> data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5278 |
|
|
<br/> data(5).PIN AND sp(2) AND sp(0) AND sp(1) AND sp(5) AND sp(3) AND sp(4) AND
|
| 5279 |
|
|
<br/> sp(6) AND sp(11) AND sp(10) AND sp(7) AND sp(8) AND sp(9) AND
|
| 5280 |
|
|
<br/> sp(12) AND sp(13) AND sp(14)));
|
| 5281 |
|
|
</td></tr><tr><td>
|
| 5282 |
|
|
FTCPE_state0: FTCPE port map (state(0),state_T(0),clock,'0','0','1');
|
| 5283 |
|
|
<br/> state_T(0) <= ((N_PZ_1065)
|
| 5284 |
|
|
<br/> OR (reset AND NOT state(0))
|
| 5285 |
|
|
<br/> OR (NOT reset AND state(2) AND state(1))
|
| 5286 |
|
|
<br/> OR (state(3) AND state(1) AND NOT N_PZ_1209)
|
| 5287 |
|
|
<br/> OR (NOT state(3) AND NOT state(0) AND NOT N_PZ_1209)
|
| 5288 |
|
|
<br/> OR (NOT state(2) AND NOT state(0) AND NOT N_PZ_1209)
|
| 5289 |
|
|
<br/> OR (NOT reset AND NOT state(1) AND NOT statehold(0) AND N_PZ_1209)
|
| 5290 |
|
|
<br/> OR (state(3) AND state(2) AND state(4) AND NOT N_PZ_1209)
|
| 5291 |
|
|
<br/> OR (NOT state(0) AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5292 |
|
|
<br/> N_PZ_1209)
|
| 5293 |
|
|
<br/> OR (NOT state(0) AND NOT data(7).PIN AND N_PZ_1209 AND NOT N_PZ_1921)
|
| 5294 |
|
|
<br/> OR (NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 5295 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND N_PZ_1209)
|
| 5296 |
|
|
<br/> OR (NOT state(3) AND NOT state(4) AND NOT state(1) AND NOT N_PZ_1209 AND
|
| 5297 |
|
|
<br/> regd(2) AND regd(1) AND NOT regd(0))
|
| 5298 |
|
|
<br/> OR (NOT state(0) AND data(2).PIN AND data(1).PIN AND
|
| 5299 |
|
|
<br/> data(0).PIN AND data(6).PIN AND data(7).PIN AND N_PZ_1209)
|
| 5300 |
|
|
<br/> OR (NOT state(0) AND data(1).PIN AND data(6).PIN AND
|
| 5301 |
|
|
<br/> data(7).PIN AND N_PZ_1209 AND N_PZ_1916 AND NOT parity)
|
| 5302 |
|
|
<br/> OR (NOT state(0) AND data(4).PIN AND data(1).PIN AND
|
| 5303 |
|
|
<br/> data(0).PIN AND data(6).PIN AND data(7).PIN AND data(5).PIN AND
|
| 5304 |
|
|
<br/> N_PZ_1209)
|
| 5305 |
|
|
<br/> OR (NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 5306 |
|
|
<br/> data(0).PIN AND data(6).PIN AND data(7).PIN AND data(5).PIN AND
|
| 5307 |
|
|
<br/> N_PZ_1209)
|
| 5308 |
|
|
<br/> OR (NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 5309 |
|
|
<br/> data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(7).PIN AND
|
| 5310 |
|
|
<br/> data(5).PIN AND N_PZ_1209)
|
| 5311 |
|
|
<br/> OR (NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5312 |
|
|
<br/> NOT data(2).PIN AND data(1).PIN AND data(6).PIN AND data(7).PIN AND
|
| 5313 |
|
|
<br/> data(5).PIN AND N_PZ_1209 AND NOT sign)
|
| 5314 |
|
|
<br/> OR (NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 5315 |
|
|
<br/> NOT data(2).PIN AND data(1).PIN AND data(6).PIN AND data(7).PIN AND
|
| 5316 |
|
|
<br/> data(5).PIN AND N_PZ_1209 AND sign)
|
| 5317 |
|
|
<br/> OR (NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND
|
| 5318 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND data(6).PIN AND data(7).PIN AND
|
| 5319 |
|
|
<br/> N_PZ_1209 AND N_PZ_1819 AND parity)
|
| 5320 |
|
|
<br/> OR (NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5321 |
|
|
<br/> NOT data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND data(6).PIN AND
|
| 5322 |
|
|
<br/> data(7).PIN AND NOT data(5).PIN AND N_PZ_1209 AND NOT carry)
|
| 5323 |
|
|
<br/> OR (NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 5324 |
|
|
<br/> NOT data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND data(6).PIN AND
|
| 5325 |
|
|
<br/> data(7).PIN AND NOT data(5).PIN AND N_PZ_1209 AND carry)
|
| 5326 |
|
|
<br/> OR (NOT state(0) AND NOT data(4).PIN AND data(3).PIN AND
|
| 5327 |
|
|
<br/> NOT data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND data(6).PIN AND
|
| 5328 |
|
|
<br/> data(7).PIN AND NOT data(5).PIN AND N_PZ_1209 AND NOT zero)
|
| 5329 |
|
|
<br/> OR (NOT state(0) AND NOT data(4).PIN AND NOT data(3).PIN AND
|
| 5330 |
|
|
<br/> NOT data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND data(6).PIN AND
|
| 5331 |
|
|
<br/> data(7).PIN AND NOT data(5).PIN AND N_PZ_1209 AND zero));
|
| 5332 |
|
|
</td></tr><tr><td>
|
| 5333 |
|
|
FDCPE_state1: FDCPE port map (state(1),state_D(1),clock,'0','0','1');
|
| 5334 |
|
|
<br/> state_D(1) <= ((state(1) AND N_PZ_1066)
|
| 5335 |
|
|
<br/> OR (NOT reset AND NOT state(1) AND N_PZ_1209 AND statehold(1))
|
| 5336 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND NOT data(6).PIN AND data(7).PIN AND
|
| 5337 |
|
|
<br/> N_PZ_1209)
|
| 5338 |
|
|
<br/> OR (state(3) AND state(2) AND NOT state(4) AND NOT state(0) AND
|
| 5339 |
|
|
<br/> NOT N_PZ_1209)
|
| 5340 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND NOT state(4) AND state(0) AND
|
| 5341 |
|
|
<br/> NOT N_PZ_1209)
|
| 5342 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND NOT data(3).PIN AND NOT data(1).PIN AND
|
| 5343 |
|
|
<br/> data(7).PIN AND N_PZ_1209)
|
| 5344 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND data(2).PIN AND NOT data(1).PIN AND
|
| 5345 |
|
|
<br/> data(7).PIN AND N_PZ_1209)
|
| 5346 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND data(2).PIN AND NOT data(0).PIN AND
|
| 5347 |
|
|
<br/> data(7).PIN AND N_PZ_1209)
|
| 5348 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND NOT data(1).PIN AND NOT data(0).PIN AND
|
| 5349 |
|
|
<br/> data(7).PIN AND N_PZ_1209)
|
| 5350 |
|
|
<br/> OR (state(3) AND state(2) AND state(4) AND NOT state(1) AND
|
| 5351 |
|
|
<br/> state(0) AND NOT N_PZ_1209)
|
| 5352 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND NOT data(2).PIN AND data(0).PIN AND
|
| 5353 |
|
|
<br/> data(7).PIN AND NOT data(5).PIN AND N_PZ_1209)
|
| 5354 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND NOT data(4).PIN AND NOT data(3).PIN AND
|
| 5355 |
|
|
<br/> NOT data(2).PIN AND data(0).PIN AND data(7).PIN AND N_PZ_1209)
|
| 5356 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND data(3).PIN AND NOT data(0).PIN AND
|
| 5357 |
|
|
<br/> data(7).PIN AND N_PZ_1209 AND N_PZ_1819 AND parity)
|
| 5358 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND
|
| 5359 |
|
|
<br/> data(7).PIN AND N_PZ_1209 AND N_PZ_1819 AND NOT parity)
|
| 5360 |
|
|
<br/> OR (NOT state(3) AND NOT state(4) AND NOT state(1) AND state(0) AND
|
| 5361 |
|
|
<br/> NOT N_PZ_1209 AND regd(2) AND regd(1) AND NOT regd(0))
|
| 5362 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5363 |
|
|
<br/> NOT data(0).PIN AND data(7).PIN AND data(5).PIN AND N_PZ_1209 AND sign)
|
| 5364 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5365 |
|
|
<br/> NOT data(0).PIN AND data(7).PIN AND NOT data(5).PIN AND N_PZ_1209 AND carry)
|
| 5366 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 5367 |
|
|
<br/> NOT data(0).PIN AND data(7).PIN AND data(5).PIN AND N_PZ_1209 AND NOT sign)
|
| 5368 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 5369 |
|
|
<br/> NOT data(0).PIN AND data(7).PIN AND NOT data(5).PIN AND N_PZ_1209 AND NOT carry)
|
| 5370 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND NOT data(4).PIN AND data(3).PIN AND
|
| 5371 |
|
|
<br/> NOT data(0).PIN AND data(7).PIN AND NOT data(5).PIN AND N_PZ_1209 AND zero)
|
| 5372 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND NOT data(4).PIN AND NOT data(3).PIN AND
|
| 5373 |
|
|
<br/> NOT data(0).PIN AND data(7).PIN AND NOT data(5).PIN AND N_PZ_1209 AND NOT zero)
|
| 5374 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND
|
| 5375 |
|
|
<br/> N_PZ_1209 AND regd(2) AND regd(1) AND NOT regd(0) AND NOT N_PZ_1373)
|
| 5376 |
|
|
<br/> OR (NOT reset AND NOT state(0) AND data(4).PIN AND NOT data(3).PIN AND
|
| 5377 |
|
|
<br/> data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND data(6).PIN AND
|
| 5378 |
|
|
<br/> data(5).PIN AND N_PZ_1209));
|
| 5379 |
|
|
</td></tr><tr><td>
|
| 5380 |
|
|
FDCPE_state2: FDCPE port map (state(2),state_D(2),clock,'0','0','1');
|
| 5381 |
|
|
<br/> state_D(2) <= ((NOT reset AND state(2) AND state(1) AND NOT state(0))
|
| 5382 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND state(4) AND
|
| 5383 |
|
|
<br/> NOT state(1))
|
| 5384 |
|
|
<br/> OR (NOT reset AND state(3) AND NOT state(2) AND state(1) AND
|
| 5385 |
|
|
<br/> state(0))
|
| 5386 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 5387 |
|
|
<br/> NOT state(0))
|
| 5388 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND state(4) AND
|
| 5389 |
|
|
<br/> NOT state(1) AND state(0) AND statehold(2))
|
| 5390 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND state(2) AND NOT state(4) AND
|
| 5391 |
|
|
<br/> NOT state(1) AND regd(2) AND regd(1) AND NOT regd(0))
|
| 5392 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(4) AND state(1) AND
|
| 5393 |
|
|
<br/> NOT state(0) AND data(1).PIN AND data(6).PIN AND N_PZ_1966)
|
| 5394 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(4) AND state(1) AND
|
| 5395 |
|
|
<br/> NOT state(0) AND data(6).PIN AND NOT data(7).PIN AND NOT _cmp_eq0004 AND
|
| 5396 |
|
|
<br/> N_PZ_1921));
|
| 5397 |
|
|
</td></tr><tr><td>
|
| 5398 |
|
|
FTCPE_state3: FTCPE port map (state(3),state_T(3),clock,'0','0','1');
|
| 5399 |
|
|
<br/> state_T(3) <= ((N_PZ_1894)
|
| 5400 |
|
|
<br/> OR (reset AND state(3))
|
| 5401 |
|
|
<br/> OR (NOT reset AND state(2) AND state(1) AND state(0))
|
| 5402 |
|
|
<br/> OR (state(3) AND NOT state(2) AND NOT state(1) AND state(0))
|
| 5403 |
|
|
<br/> OR (NOT reset AND NOT state(2) AND NOT state(1) AND state(0) AND
|
| 5404 |
|
|
<br/> NOT N_PZ_1065 AND statehold(3))
|
| 5405 |
|
|
<br/> OR (NOT reset AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 5406 |
|
|
<br/> NOT state(0) AND data(1).PIN AND N_PZ_1966)
|
| 5407 |
|
|
<br/> OR (NOT reset AND NOT state(2) AND NOT state(4) AND state(1) AND
|
| 5408 |
|
|
<br/> NOT state(0) AND NOT data(6).PIN AND data(7).PIN));
|
| 5409 |
|
|
</td></tr><tr><td>
|
| 5410 |
|
|
FTCPE_state4: FTCPE port map (state(4),state_T(4),clock,'0','0','1');
|
| 5411 |
|
|
<br/> state_T(4) <= ((reset AND state(4))
|
| 5412 |
|
|
<br/> OR (NOT state(3) AND state(2) AND state(4) AND NOT state(1))
|
| 5413 |
|
|
<br/> OR (NOT state(3) AND NOT state(2) AND state(4) AND state(1))
|
| 5414 |
|
|
<br/> OR (NOT reset AND state(3) AND state(2) AND state(1) AND
|
| 5415 |
|
|
<br/> state(0))
|
| 5416 |
|
|
<br/> OR (state(3) AND NOT state(2) AND state(4) AND NOT state(1) AND
|
| 5417 |
|
|
<br/> state(0))
|
| 5418 |
|
|
<br/> OR (NOT state(2) AND state(4) AND NOT state(1) AND state(0) AND
|
| 5419 |
|
|
<br/> NOT statehold(4)));
|
| 5420 |
|
|
</td></tr><tr><td>
|
| 5421 |
|
|
FTCPE_statehold0: FTCPE port map (statehold(0),statehold_T(0),clock,'0','0','1');
|
| 5422 |
|
|
<br/> statehold_T(0) <= ((statehold(0) AND N_PZ_2232)
|
| 5423 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5424 |
|
|
<br/> state(1) AND NOT state(0) AND statehold(0) AND NOT data(2).PIN AND
|
| 5425 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5426 |
|
|
<br/> data(5).PIN)
|
| 5427 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5428 |
|
|
<br/> state(1) AND NOT state(0) AND statehold(0) AND NOT data(4).PIN AND
|
| 5429 |
|
|
<br/> NOT data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND
|
| 5430 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN)
|
| 5431 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5432 |
|
|
<br/> state(1) AND NOT state(0) AND NOT statehold(0) AND data(4).PIN AND
|
| 5433 |
|
|
<br/> NOT data(3).PIN AND NOT data(2).PIN AND NOT data(1).PIN AND data(0).PIN AND
|
| 5434 |
|
|
<br/> NOT data(6).PIN AND NOT data(7).PIN));
|
| 5435 |
|
|
</td></tr><tr><td>
|
| 5436 |
|
|
FTCPE_statehold1: FTCPE port map (statehold(1),statehold_T(1),clock,'0','0','1');
|
| 5437 |
|
|
<br/> statehold_T(1) <= ((N_PZ_2232 AND NOT statehold(1))
|
| 5438 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5439 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(2).PIN AND data(1).PIN AND
|
| 5440 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND
|
| 5441 |
|
|
<br/> NOT statehold(1))
|
| 5442 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5443 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND
|
| 5444 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5445 |
|
|
<br/> data(5).PIN AND NOT statehold(1))
|
| 5446 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5447 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND
|
| 5448 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5449 |
|
|
<br/> data(5).PIN AND statehold(1))
|
| 5450 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5451 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND
|
| 5452 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5453 |
|
|
<br/> NOT data(5).PIN AND NOT statehold(1))
|
| 5454 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5455 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND data(3).PIN AND
|
| 5456 |
|
|
<br/> NOT data(2).PIN AND data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND
|
| 5457 |
|
|
<br/> NOT data(7).PIN AND data(5).PIN AND statehold(1)));
|
| 5458 |
|
|
</td></tr><tr><td>
|
| 5459 |
|
|
FTCPE_statehold2: FTCPE port map (statehold(2),statehold_T(2),clock,'0','0','1');
|
| 5460 |
|
|
<br/> statehold_T(2) <= ((N_PZ_2232 AND statehold(2))
|
| 5461 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5462 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 5463 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5464 |
|
|
<br/> data(5).PIN AND NOT statehold(2))
|
| 5465 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5466 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 5467 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5468 |
|
|
<br/> data(5).PIN AND NOT statehold(2))
|
| 5469 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5470 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND
|
| 5471 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5472 |
|
|
<br/> N_PZ_1819 AND statehold(2))
|
| 5473 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5474 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND
|
| 5475 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5476 |
|
|
<br/> data(5).PIN AND NOT statehold(2))
|
| 5477 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5478 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND
|
| 5479 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5480 |
|
|
<br/> NOT data(5).PIN AND statehold(2)));
|
| 5481 |
|
|
</td></tr><tr><td>
|
| 5482 |
|
|
FTCPE_statehold3: FTCPE port map (statehold(3),statehold_T(3),clock,'0','0','1');
|
| 5483 |
|
|
<br/> statehold_T(3) <= ((N_PZ_2232 AND statehold(3))
|
| 5484 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5485 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND
|
| 5486 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5487 |
|
|
<br/> statehold(3))
|
| 5488 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5489 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 5490 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5491 |
|
|
<br/> data(5).PIN AND statehold(3))
|
| 5492 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5493 |
|
|
<br/> state(1) AND NOT state(0) AND data(3).PIN AND NOT data(2).PIN AND
|
| 5494 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5495 |
|
|
<br/> data(5).PIN AND statehold(3))
|
| 5496 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5497 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND
|
| 5498 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5499 |
|
|
<br/> N_PZ_1819 AND NOT statehold(3)));
|
| 5500 |
|
|
</td></tr><tr><td>
|
| 5501 |
|
|
FTCPE_statehold4: FTCPE port map (statehold(4),statehold_T(4),clock,'0','0','1');
|
| 5502 |
|
|
<br/> statehold_T(4) <= ((N_PZ_2232 AND statehold(4))
|
| 5503 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5504 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(3).PIN AND NOT data(2).PIN AND
|
| 5505 |
|
|
<br/> NOT data(1).PIN AND data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5506 |
|
|
<br/> NOT statehold(4))
|
| 5507 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5508 |
|
|
<br/> state(1) AND NOT state(0) AND NOT data(2).PIN AND data(1).PIN AND
|
| 5509 |
|
|
<br/> NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND N_PZ_1819 AND
|
| 5510 |
|
|
<br/> NOT statehold(4))
|
| 5511 |
|
|
<br/> OR (NOT reset AND NOT state(3) AND NOT state(2) AND NOT state(4) AND
|
| 5512 |
|
|
<br/> state(1) AND NOT state(0) AND data(4).PIN AND NOT data(2).PIN AND
|
| 5513 |
|
|
<br/> data(1).PIN AND NOT data(0).PIN AND NOT data(6).PIN AND NOT data(7).PIN AND
|
| 5514 |
|
|
<br/> data(5).PIN AND statehold(4)));
|
| 5515 |
|
|
</td></tr><tr><td>
|
| 5516 |
|
|
FDCPE_zero: FDCPE port map (zero,zero_D,clock,'0','0','1');
|
| 5517 |
|
|
<br/> zero_D <= ((N_PZ_1894 AND aluzout)
|
| 5518 |
|
|
<br/> OR (NOT N_PZ_1894 AND zero));
|
| 5519 |
|
|
</td></tr><tr><td>
|
| 5520 |
|
|
</td></tr><tr><td>
|
| 5521 |
|
|
Register Legend:
|
| 5522 |
|
|
<br/> FDCPE (Q,D,C,CLR,PRE,CE);
|
| 5523 |
|
|
<br/> FDDCPE (Q,D,C,CLR,PRE,CE);
|
| 5524 |
|
|
<br/> FTCPE (Q,D,C,CLR,PRE,CE);
|
| 5525 |
|
|
<br/> FTDCPE (Q,D,C,CLR,PRE,CE);
|
| 5526 |
|
|
<br/> LDCP (Q,D,G,CLR,PRE);
|
| 5527 |
|
|
</td></tr><tr><td>
|
| 5528 |
|
|
</td></tr>
|
| 5529 |
|
|
</table>
|
| 5530 |
|
|
<form><span class="pgRef"><table width="90%" align="center"><tr>
|
| 5531 |
|
|
<td align="left"><input type="button" onclick="javascript:parent.leftnav.showTop()" onmouseover="window.status='goto top of page'; return true;" onmouseout="window.status=''" value="back to top"></td>
|
| 5532 |
|
|
<td align="right"><input type="button" onclick="window.print()" onmouseover="window.status='print page'; return true;" onmouseout="window.status=''" value="print page"></td>
|
| 5533 |
|
|
</tr></table></span></form>
|
| 5534 |
|
|
</body></html>
|
