OpenCores
URL https://opencores.org/ocsvn/cpu8080/cpu8080/trunk

Subversion Repositories cpu8080

[/] [cpu8080/] [trunk/] [project/] [cpu8080_tbw.tfw] - Blame information for rev 11

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 11 samiam9512 
////////////////////////////////////////////////////////////////////////////////
2 
// Copyright (c) 1995-2003 Xilinx, Inc.
3 
// All Right Reserved.
4 
////////////////////////////////////////////////////////////////////////////////
5 
//   ____  ____
6 
//  /   /\/   /
7 
// /___/  \  /    Vendor: Xilinx
8 
// \   \   \/     Version : 8.2.02i
9 
//  \   \         Application : ISE
10 
//  /   /         Filename : cpu8080_tbw.tfw
11 
// /___/   /\     Timestamp : Sat Oct 28 22:18:07 2006
12 
// \   \  /  \
13 
//  \___\/\___\
14 
//
15 
//Command:
16 
//Design Name: cpu8080_tbw
17 
//Device: Xilinx
18 
//
19 
`timescale 1ns/1ps
20 
 
21 
module cpu8080_tbw;
22 
    wire [15:0] addr;
23 
    reg [7:0] data$inout$reg = 8'b00000000;
24 
    wire [7:0] data = data$inout$reg;
25 
    wire readmem;
26 
    wire writemem;
27 
    wire readio;
28 
    wire writeio;
29 
    wire intr;
30 
    wire inta;
31 
    reg waitr = 1'b0;
32 
    wire [2:0] r;
33 
    wire [2:0] g;
34 
    wire [2:0] b;
35 
    wire hsync_n;
36 
    wire vsync_n;
37 
    reg reset_n = 1'b1;
38 
    reg clock = 1'b0;
39 
 
40 
    parameter PERIOD = 40;
41 
    parameter real DUTY_CYCLE = 0.5;
42 
    parameter OFFSET = 100;
43 
 
44 
    initial    // Clock process for clock
45 
    begin
46 
        #OFFSET;
47 
        forever
48 
        begin
49 
            clock = 1'b0;
50 
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clock = 1'b1;
51 
            #(PERIOD*DUTY_CYCLE);
52 
        end
53 
    end
54 
 
55 
    testbench UUT (
56 
        .addr(addr),
57 
        .data(data),
58 
        .readmem(readmem),
59 
        .writemem(writemem),
60 
        .readio(readio),
61 
        .writeio(writeio),
62 
        .intr(intr),
63 
        .inta(inta),
64 
        .waitr(waitr),
65 
        .r(r),
66 
        .g(g),
67 
        .b(b),
68 
        .hsync_n(hsync_n),
69 
        .vsync_n(vsync_n),
70 
        .reset_n(reset_n),
71 
        .clock(clock));
72 
 
73 
    integer TX_FILE = 0;
74 
    integer TX_ERROR = 0;
75 
 
76 
    initial begin  // Open the results file...
77 
        TX_FILE = $fopen("results.txt");
78 
        #100040 // Final time:  100040 ns
79 
        if (TX_ERROR == 0) begin
80 
            $display("No errors or warnings.");
81 
            $fdisplay(TX_FILE, "No errors or warnings.");
82 
        end else begin
83 
            $display("%d errors found in simulation.", TX_ERROR);
84 
            $fdisplay(TX_FILE, "%d errors found in simulation.", TX_ERROR);
85 
        end
86 
        $fclose(TX_FILE);
87 
        $stop;
88 
    end
89 
 
90 
    initial begin
91 
        // -------------  Current Time:  110ns
92 
        #110;
93 
        reset_n = 1'b0;
94 
        data$inout$reg = 8'bZZZZZZZZ;
95 
        // -------------------------------------
96 
        // -------------  Current Time:  270ns
97 
        #160;
98 
        reset_n = 1'b1;
99 
        // -------------------------------------
100 
    end
101 
 
102 
    task CHECK_addr;
103 
        input [15:0] NEXT_addr;
104 
 
105 
        #0 begin
106 
            if (NEXT_addr !== addr) begin
107 
                $display("Error at time=%dns addr=%b, expected=%b", $time, addr, NEXT_addr);
108 
                $fdisplay(TX_FILE, "Error at time=%dns addr=%b, expected=%b", $time, addr, NEXT_addr);
109 
                $fflush(TX_FILE);
110 
                TX_ERROR = TX_ERROR + 1;
111 
            end
112 
        end
113 
    endtask
114 
    task CHECK_readmem;
115 
        input NEXT_readmem;
116 
 
117 
        #0 begin
118 
            if (NEXT_readmem !== readmem) begin
119 
                $display("Error at time=%dns readmem=%b, expected=%b", $time, readmem, NEXT_readmem);
120 
                $fdisplay(TX_FILE, "Error at time=%dns readmem=%b, expected=%b", $time, readmem, NEXT_readmem);
121 
                $fflush(TX_FILE);
122 
                TX_ERROR = TX_ERROR + 1;
123 
            end
124 
        end
125 
    endtask
126 
    task CHECK_writemem;
127 
        input NEXT_writemem;
128 
 
129 
        #0 begin
130 
            if (NEXT_writemem !== writemem) begin
131 
                $display("Error at time=%dns writemem=%b, expected=%b", $time, writemem, NEXT_writemem);
132 
                $fdisplay(TX_FILE, "Error at time=%dns writemem=%b, expected=%b", $time, writemem, NEXT_writemem);
133 
                $fflush(TX_FILE);
134 
                TX_ERROR = TX_ERROR + 1;
135 
            end
136 
        end
137 
    endtask
138 
    task CHECK_readio;
139 
        input NEXT_readio;
140 
 
141 
        #0 begin
142 
            if (NEXT_readio !== readio) begin
143 
                $display("Error at time=%dns readio=%b, expected=%b", $time, readio, NEXT_readio);
144 
                $fdisplay(TX_FILE, "Error at time=%dns readio=%b, expected=%b", $time, readio, NEXT_readio);
145 
                $fflush(TX_FILE);
146 
                TX_ERROR = TX_ERROR + 1;
147 
            end
148 
        end
149 
    endtask
150 
    task CHECK_writeio;
151 
        input NEXT_writeio;
152 
 
153 
        #0 begin
154 
            if (NEXT_writeio !== writeio) begin
155 
                $display("Error at time=%dns writeio=%b, expected=%b", $time, writeio, NEXT_writeio);
156 
                $fdisplay(TX_FILE, "Error at time=%dns writeio=%b, expected=%b", $time, writeio, NEXT_writeio);
157 
                $fflush(TX_FILE);
158 
                TX_ERROR = TX_ERROR + 1;
159 
            end
160 
        end
161 
    endtask
162 
    task CHECK_intr;
163 
        input NEXT_intr;
164 
 
165 
        #0 begin
166 
            if (NEXT_intr !== intr) begin
167 
                $display("Error at time=%dns intr=%b, expected=%b", $time, intr, NEXT_intr);
168 
                $fdisplay(TX_FILE, "Error at time=%dns intr=%b, expected=%b", $time, intr, NEXT_intr);
169 
                $fflush(TX_FILE);
170 
                TX_ERROR = TX_ERROR + 1;
171 
            end
172 
        end
173 
    endtask
174 
    task CHECK_inta;
175 
        input NEXT_inta;
176 
 
177 
        #0 begin
178 
            if (NEXT_inta !== inta) begin
179 
                $display("Error at time=%dns inta=%b, expected=%b", $time, inta, NEXT_inta);
180 
                $fdisplay(TX_FILE, "Error at time=%dns inta=%b, expected=%b", $time, inta, NEXT_inta);
181 
                $fflush(TX_FILE);
182 
                TX_ERROR = TX_ERROR + 1;
183 
            end
184 
        end
185 
    endtask
186 
    task CHECK_r;
187 
        input [2:0] NEXT_r;
188 
 
189 
        #0 begin
190 
            if (NEXT_r !== r) begin
191 
                $display("Error at time=%dns r=%b, expected=%b", $time, r, NEXT_r);
192 
                $fdisplay(TX_FILE, "Error at time=%dns r=%b, expected=%b", $time, r, NEXT_r);
193 
                $fflush(TX_FILE);
194 
                TX_ERROR = TX_ERROR + 1;
195 
            end
196 
        end
197 
    endtask
198 
    task CHECK_g;
199 
        input [2:0] NEXT_g;
200 
 
201 
        #0 begin
202 
            if (NEXT_g !== g) begin
203 
                $display("Error at time=%dns g=%b, expected=%b", $time, g, NEXT_g);
204 
                $fdisplay(TX_FILE, "Error at time=%dns g=%b, expected=%b", $time, g, NEXT_g);
205 
                $fflush(TX_FILE);
206 
                TX_ERROR = TX_ERROR + 1;
207 
            end
208 
        end
209 
    endtask
210 
    task CHECK_b;
211 
        input [2:0] NEXT_b;
212 
 
213 
        #0 begin
214 
            if (NEXT_b !== b) begin
215 
                $display("Error at time=%dns b=%b, expected=%b", $time, b, NEXT_b);
216 
                $fdisplay(TX_FILE, "Error at time=%dns b=%b, expected=%b", $time, b, NEXT_b);
217 
                $fflush(TX_FILE);
218 
                TX_ERROR = TX_ERROR + 1;
219 
            end
220 
        end
221 
    endtask
222 
    task CHECK_hsync_n;
223 
        input NEXT_hsync_n;
224 
 
225 
        #0 begin
226 
            if (NEXT_hsync_n !== hsync_n) begin
227 
                $display("Error at time=%dns hsync_n=%b, expected=%b", $time, hsync_n, NEXT_hsync_n);
228 
                $fdisplay(TX_FILE, "Error at time=%dns hsync_n=%b, expected=%b", $time, hsync_n, NEXT_hsync_n);
229 
                $fflush(TX_FILE);
230 
                TX_ERROR = TX_ERROR + 1;
231 
            end
232 
        end
233 
    endtask
234 
    task CHECK_vsync_n;
235 
        input NEXT_vsync_n;
236 
 
237 
        #0 begin
238 
            if (NEXT_vsync_n !== vsync_n) begin
239 
                $display("Error at time=%dns vsync_n=%b, expected=%b", $time, vsync_n, NEXT_vsync_n);
240 
                $fdisplay(TX_FILE, "Error at time=%dns vsync_n=%b, expected=%b", $time, vsync_n, NEXT_vsync_n);
241 
                $fflush(TX_FILE);
242 
                TX_ERROR = TX_ERROR + 1;
243 
            end
244 
        end
245 
    endtask
246 
 
247 
endmodule
248 
 

powered by: WebSVN 2.1.0

© copyright 1999-2025 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.