URL https://opencores.org/ocsvn/cpu8080/cpu8080/trunk

Subversion Repositories cpu8080

[/] [cpu8080/] [trunk/] [project/] [cpu_tbw.tbw] - Blame information for rev 12

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version 3
C:/Xilinx/ISEexamples/cpu8080/testbench.v
testbench
VERILOG
VERILOG
cpu_tbw.xwv
Clocked
-
-
100000000000
ns
GSR:false
PRLD:false
100000000
CLOCK_LIST_BEGIN
clock
100000000
100000000
15000000
15000000
 
RISING
CLOCK_LIST_END
SIGNAL_LIST_BEGIN
addr
clock
b
clock
data
clock
g
clock
hsync_n
clock
inta
clock
intr
clock
junk
clock
r
clock
readio
clock
readmem
clock
reset
clock
vsync_n
clock
waitr
clock
writeio
clock
writemem
clock
SIGNAL_LIST_END
SIGNALS_NOT_ON_DISPLAY
addr_DIFF
b_DIFF
g_DIFF
hsync_n_DIFF
inta_DIFF
intr_DIFF
r_DIFF
readio_DIFF
readmem_DIFF
vsync_n_DIFF
writeio_DIFF
writemem_DIFF
SIGNALS_NOT_ON_DISPLAY_END
MARKER_LIST_BEGIN
MARKER_LIST_END
MEASURE_LIST_BEGIN
MEASURE_LIST_END
SIGNAL_ORDER_BEGIN
clock
intr
reset
waitr
inta
readio
readmem
writeio
writemem
addr
data
b
g
r
hsync_n
vsync_n
SIGNAL_ORDER_END
-X-X-X-
 

Line No.	Rev	Author	Line
1	2	samiam9512	`version 3`
2			`C:/Xilinx/ISEexamples/cpu8080/testbench.v`
3			`testbench`
4			`VERILOG`
5			`VERILOG`
6			`cpu_tbw.xwv`
7			`Clocked`
8			`-`
9			`-`
10	11	samiam9512	`100000000000`
11	2	samiam9512	`ns`
12			`GSR:false`
13			`PRLD:false`
14			`100000000`
15			`CLOCK_LIST_BEGIN`
16			`clock`
17			`100000000`
18			`100000000`
19			`15000000`
20			`15000000`
21
22			`RISING`
23			`CLOCK_LIST_END`
24			`SIGNAL_LIST_BEGIN`
25			`addr`
26			`clock`
27	11	samiam9512	`b`
28			`clock`
29	2	samiam9512	`data`
30			`clock`
31	11	samiam9512	`g`
32			`clock`
33			`hsync_n`
34			`clock`
35	2	samiam9512	`inta`
36			`clock`
37			`intr`
38			`clock`
39			`junk`
40			`clock`
41	11	samiam9512	`r`
42			`clock`
43	2	samiam9512	`readio`
44			`clock`
45			`readmem`
46			`clock`
47			`reset`
48			`clock`
49	11	samiam9512	`vsync_n`
50			`clock`
51	2	samiam9512	`waitr`
52			`clock`
53			`writeio`
54			`clock`
55			`writemem`
56			`clock`
57			`SIGNAL_LIST_END`
58			`SIGNALS_NOT_ON_DISPLAY`
59			`addr_DIFF`
60	11	samiam9512	`b_DIFF`
61			`g_DIFF`
62			`hsync_n_DIFF`
63	2	samiam9512	`inta_DIFF`
64	11	samiam9512	`intr_DIFF`
65			`r_DIFF`
66	2	samiam9512	`readio_DIFF`
67			`readmem_DIFF`
68	11	samiam9512	`vsync_n_DIFF`
69	2	samiam9512	`writeio_DIFF`
70			`writemem_DIFF`
71			`SIGNALS_NOT_ON_DISPLAY_END`
72			`MARKER_LIST_BEGIN`
73			`MARKER_LIST_END`
74			`MEASURE_LIST_BEGIN`
75			`MEASURE_LIST_END`
76			`SIGNAL_ORDER_BEGIN`
77			`clock`
78			`intr`
79			`reset`
80			`waitr`
81			`inta`
82			`readio`
83			`readmem`
84			`writeio`
85			`writemem`
86			`addr`
87			`data`
88	11	samiam9512	`b`
89			`g`
90			`r`
91			`hsync_n`
92			`vsync_n`
93	2	samiam9512	`SIGNAL_ORDER_END`
94			`-X-X-X-`
95

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Subversion Repositories cpu8080

[/] [cpu8080/] [trunk/] [project/] [cpu_tbw.tbw] - Blame information for rev 12