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[/] [cpu8080/] [trunk/] [project/] [cpu_tbw.tfw] - Blame information for rev 33

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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2003 Xilinx, Inc.
// All Right Reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version : 8.2.02i
//  \   \         Application : ISE
//  /   /         Filename : cpu_tbw.tfw
// /___/   /\     Timestamp : Sat Oct 28 09:12:59 2006
// \   \  /  \
//  \___\/\___\
//
//Command:
//Design Name: cpu_tbw
//Device: Xilinx
//
`timescale 1ns/1ps
 
module cpu_tbw;
    wire [15:0] addr;
    reg [7:0] data$inout$reg = 8'bZ1Z00000;
    wire [7:0] data = data$inout$reg;
    wire readmem;
    wire writemem;
    wire readio;
    wire writeio;
    wire intr;
    wire inta;
    reg waitr = 1'b0;
    wire [2:0] r;
    wire [2:0] g;
    wire [2:0] b;
    wire hsync_n;
    wire vsync_n;
    reg reset = 1'b0;
    reg clock = 1'b0;
 
    parameter PERIOD = 200;
    parameter real DUTY_CYCLE = 0.5;
    parameter OFFSET = 0;
 
    initial    // Clock process for clock
    begin
        #OFFSET;
        forever
        begin
            clock = 1'b0;
            #(PERIOD-(PERIOD*DUTY_CYCLE)) clock = 1'b1;
            #(PERIOD*DUTY_CYCLE);
        end
    end
 
    testbench UUT (
        .addr(addr),
        .data(data),
        .readmem(readmem),
        .writemem(writemem),
        .readio(readio),
        .writeio(writeio),
        .intr(intr),
        .inta(inta),
        .waitr(waitr),
        .r(r),
        .g(g),
        .b(b),
        .hsync_n(hsync_n),
        .vsync_n(vsync_n),
        .reset(reset),
        .clock(clock));
 
        integer TX_ERROR = 0;
 
        initial begin  // Open the results file...
            #100200 // Final time:  100200 ns
            if (TX_ERROR == 0) begin
                $display("No errors or warnings.");
                end else begin
                    $display("%d errors found in simulation.", TX_ERROR);
                    end
                    $stop;
                end
 
                initial begin
                    // -------------  Current Time:  85ns
                    #85;
                    reset = 1'b1;
                    data$inout$reg = 8'bZZZZZZZZ;
                    // -------------------------------------
                    // -------------  Current Time:  485ns
                    #400;
                    reset = 1'b0;
                    // -------------------------------------
                end
 
                task CHECK_addr;
                    input [15:0] NEXT_addr;
 
                    #0 begin
                        if (NEXT_addr !== addr) begin
                            $display("Error at time=%dns addr=%b, expected=%b", $time, addr, NEXT_addr);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask
                task CHECK_readmem;
                    input NEXT_readmem;
 
                    #0 begin
                        if (NEXT_readmem !== readmem) begin
                            $display("Error at time=%dns readmem=%b, expected=%b", $time, readmem, NEXT_readmem);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask
                task CHECK_writemem;
                    input NEXT_writemem;
 
                    #0 begin
                        if (NEXT_writemem !== writemem) begin
                            $display("Error at time=%dns writemem=%b, expected=%b", $time, writemem, NEXT_writemem);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask
                task CHECK_readio;
                    input NEXT_readio;
 
                    #0 begin
                        if (NEXT_readio !== readio) begin
                            $display("Error at time=%dns readio=%b, expected=%b", $time, readio, NEXT_readio);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask
                task CHECK_writeio;
                    input NEXT_writeio;
 
                    #0 begin
                        if (NEXT_writeio !== writeio) begin
                            $display("Error at time=%dns writeio=%b, expected=%b", $time, writeio, NEXT_writeio);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask
                task CHECK_intr;
                    input NEXT_intr;
 
                    #0 begin
                        if (NEXT_intr !== intr) begin
                            $display("Error at time=%dns intr=%b, expected=%b", $time, intr, NEXT_intr);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask
                task CHECK_inta;
                    input NEXT_inta;
 
                    #0 begin
                        if (NEXT_inta !== inta) begin
                            $display("Error at time=%dns inta=%b, expected=%b", $time, inta, NEXT_inta);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask
                task CHECK_r;
                    input [2:0] NEXT_r;
 
                    #0 begin
                        if (NEXT_r !== r) begin
                            $display("Error at time=%dns r=%b, expected=%b", $time, r, NEXT_r);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask
                task CHECK_g;
                    input [2:0] NEXT_g;
 
                    #0 begin
                        if (NEXT_g !== g) begin
                            $display("Error at time=%dns g=%b, expected=%b", $time, g, NEXT_g);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask
                task CHECK_b;
                    input [2:0] NEXT_b;
 
                    #0 begin
                        if (NEXT_b !== b) begin
                            $display("Error at time=%dns b=%b, expected=%b", $time, b, NEXT_b);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask
                task CHECK_hsync_n;
                    input NEXT_hsync_n;
 
                    #0 begin
                        if (NEXT_hsync_n !== hsync_n) begin
                            $display("Error at time=%dns hsync_n=%b, expected=%b", $time, hsync_n, NEXT_hsync_n);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask
                task CHECK_vsync_n;
                    input NEXT_vsync_n;
 
                    #0 begin
                        if (NEXT_vsync_n !== vsync_n) begin
                            $display("Error at time=%dns vsync_n=%b, expected=%b", $time, vsync_n, NEXT_vsync_n);
                            TX_ERROR = TX_ERROR + 1;
                        end
                    end
                endtask
 
            endmodule
 

Line No.	Rev	Author	Line
1	2	samiam9512	`////////////////////////////////////////////////////////////////////////////////`
2			`// Copyright (c) 1995-2003 Xilinx, Inc.`
3			`// All Right Reserved.`
4			`////////////////////////////////////////////////////////////////////////////////`
5			`// ____ ____`
6			`// / /\/ /`
7			`// /___/ \ / Vendor: Xilinx`
8			`// \ \ \/ Version : 8.2.02i`
9			`// \ \ Application : ISE`
10			`// / / Filename : cpu_tbw.tfw`
11	11	samiam9512	`// /___/ /\ Timestamp : Sat Oct 28 09:12:59 2006`
12	2	samiam9512	`// \ \ / \`
13			`// \___\/\___\`
14			`//`
15			`//Command:`
16			`//Design Name: cpu_tbw`
17			`//Device: Xilinx`
18			`//`
19			`timescale 1ns/1ps
20
21			`module cpu_tbw;`
22			`wire [15:0] addr;`
23	11	samiam9512	`reg [7:0] data$inout$reg = 8'bZ1Z00000;`
24	2	samiam9512	`wire [7:0] data = data$inout$reg;`
25			`wire readmem;`
26			`wire writemem;`
27			`wire readio;`
28			`wire writeio;`
29	9	samiam9512	`wire intr;`
30	2	samiam9512	`wire inta;`
31			`reg waitr = 1'b0;`
32	11	samiam9512	`wire [2:0] r;`
33			`wire [2:0] g;`
34			`wire [2:0] b;`
35			`wire hsync_n;`
36			`wire vsync_n;`
37			`reg reset = 1'b0;`
38	2	samiam9512	`reg clock = 1'b0;`
39
40			`parameter PERIOD = 200;`
41			`parameter real DUTY_CYCLE = 0.5;`
42			`parameter OFFSET = 0;`
43
44			`initial // Clock process for clock`
45			`begin`
46			`#OFFSET;`
47			`forever`
48			`begin`
49			`clock = 1'b0;`
50			`#(PERIOD-(PERIOD*DUTY_CYCLE)) clock = 1'b1;`
51			`#(PERIOD*DUTY_CYCLE);`
52			`end`
53			`end`
54
55			`testbench UUT (`
56			`.addr(addr),`
57			`.data(data),`
58			`.readmem(readmem),`
59			`.writemem(writemem),`
60			`.readio(readio),`
61			`.writeio(writeio),`
62			`.intr(intr),`
63			`.inta(inta),`
64			`.waitr(waitr),`
65	11	samiam9512	`.r(r),`
66			`.g(g),`
67			`.b(b),`
68			`.hsync_n(hsync_n),`
69			`.vsync_n(vsync_n),`
70	2	samiam9512	`.reset(reset),`
71			`.clock(clock));`
72
73	11	samiam9512	`integer TX_ERROR = 0;`
74
75			`initial begin // Open the results file...`
76			`#100200 // Final time: 100200 ns`
77			`if (TX_ERROR == 0) begin`
78			`$display("No errors or warnings.");`
79			`end else begin`
80			`$display("%d errors found in simulation.", TX_ERROR);`
81			`end`
82			`$stop;`
83			`end`
84	2	samiam9512
85	11	samiam9512	`initial begin`
86			`// ------------- Current Time: 85ns`
87			`#85;`
88			`reset = 1'b1;`
89			`data$inout$reg = 8'bZZZZZZZZ;`
90			`// -------------------------------------`
91			`// ------------- Current Time: 485ns`
92			`#400;`
93			`reset = 1'b0;`
94			`// -------------------------------------`
95			`end`
96	2	samiam9512
97	11	samiam9512	`task CHECK_addr;`
98			`input [15:0] NEXT_addr;`
99	2	samiam9512
100	11	samiam9512	`#0 begin`
101			`if (NEXT_addr !== addr) begin`
102			`$display("Error at time=%dns addr=%b, expected=%b", $time, addr, NEXT_addr);`
103			`TX_ERROR = TX_ERROR + 1;`
104			`end`
105			`end`
106			`endtask`
107			`task CHECK_readmem;`
108			`input NEXT_readmem;`
109	2	samiam9512
110	11	samiam9512	`#0 begin`
111			`if (NEXT_readmem !== readmem) begin`
112			`$display("Error at time=%dns readmem=%b, expected=%b", $time, readmem, NEXT_readmem);`
113			`TX_ERROR = TX_ERROR + 1;`
114			`end`
115			`end`
116			`endtask`
117			`task CHECK_writemem;`
118			`input NEXT_writemem;`
119	2	samiam9512
120	11	samiam9512	`#0 begin`
121			`if (NEXT_writemem !== writemem) begin`
122			`$display("Error at time=%dns writemem=%b, expected=%b", $time, writemem, NEXT_writemem);`
123			`TX_ERROR = TX_ERROR + 1;`
124			`end`
125			`end`
126			`endtask`
127			`task CHECK_readio;`
128			`input NEXT_readio;`
129	2	samiam9512
130	11	samiam9512	`#0 begin`
131			`if (NEXT_readio !== readio) begin`
132			`$display("Error at time=%dns readio=%b, expected=%b", $time, readio, NEXT_readio);`
133			`TX_ERROR = TX_ERROR + 1;`
134			`end`
135			`end`
136			`endtask`
137			`task CHECK_writeio;`
138			`input NEXT_writeio;`
139	2	samiam9512
140	11	samiam9512	`#0 begin`
141			`if (NEXT_writeio !== writeio) begin`
142			`$display("Error at time=%dns writeio=%b, expected=%b", $time, writeio, NEXT_writeio);`
143			`TX_ERROR = TX_ERROR + 1;`
144			`end`
145			`end`
146			`endtask`
147			`task CHECK_intr;`
148			`input NEXT_intr;`
149	9	samiam9512
150	11	samiam9512	`#0 begin`
151			`if (NEXT_intr !== intr) begin`
152			`$display("Error at time=%dns intr=%b, expected=%b", $time, intr, NEXT_intr);`
153			`TX_ERROR = TX_ERROR + 1;`
154			`end`
155			`end`
156			`endtask`
157			`task CHECK_inta;`
158			`input NEXT_inta;`
159	2	samiam9512
160	11	samiam9512	`#0 begin`
161			`if (NEXT_inta !== inta) begin`
162			`$display("Error at time=%dns inta=%b, expected=%b", $time, inta, NEXT_inta);`
163			`TX_ERROR = TX_ERROR + 1;`
164			`end`
165			`end`
166			`endtask`
167			`task CHECK_r;`
168			`input [2:0] NEXT_r;`
169	2	samiam9512
170	11	samiam9512	`#0 begin`
171			`if (NEXT_r !== r) begin`
172			`$display("Error at time=%dns r=%b, expected=%b", $time, r, NEXT_r);`
173			`TX_ERROR = TX_ERROR + 1;`
174			`end`
175			`end`
176			`endtask`
177			`task CHECK_g;`
178			`input [2:0] NEXT_g;`
179	2	samiam9512
180	11	samiam9512	`#0 begin`
181			`if (NEXT_g !== g) begin`
182			`$display("Error at time=%dns g=%b, expected=%b", $time, g, NEXT_g);`
183			`TX_ERROR = TX_ERROR + 1;`
184			`end`
185			`end`
186			`endtask`
187			`task CHECK_b;`
188			`input [2:0] NEXT_b;`
189
190			`#0 begin`
191			`if (NEXT_b !== b) begin`
192			`$display("Error at time=%dns b=%b, expected=%b", $time, b, NEXT_b);`
193			`TX_ERROR = TX_ERROR + 1;`
194			`end`
195			`end`
196			`endtask`
197			`task CHECK_hsync_n;`
198			`input NEXT_hsync_n;`
199
200			`#0 begin`
201			`if (NEXT_hsync_n !== hsync_n) begin`
202			`$display("Error at time=%dns hsync_n=%b, expected=%b", $time, hsync_n, NEXT_hsync_n);`
203			`TX_ERROR = TX_ERROR + 1;`
204			`end`
205			`end`
206			`endtask`
207			`task CHECK_vsync_n;`
208			`input NEXT_vsync_n;`
209
210			`#0 begin`
211			`if (NEXT_vsync_n !== vsync_n) begin`
212			`$display("Error at time=%dns vsync_n=%b, expected=%b", $time, vsync_n, NEXT_vsync_n);`
213			`TX_ERROR = TX_ERROR + 1;`
214			`end`
215			`end`
216			`endtask`
217
218			`endmodule`
219

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[/] [cpu8080/] [trunk/] [project/] [cpu_tbw.tfw] - Blame information for rev 33