URL https://opencores.org/ocsvn/cpu8080/cpu8080/trunk

Subversion Repositories cpu8080

[/] [cpu8080/] [trunk/] [project/] [isim/] [temp/] [hdpdeps.ref] - Blame information for rev 33

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V3 11
FL $XILINX/ISEexamples/cpu8080/cpu8080.v 2006/09/20.00:13:38 I.33
MO isim_temp/cpu8080    FL $XILINX/ISEexamples/cpu8080/cpu8080.v MI alu
MO isim_temp/alu        FL $XILINX/ISEexamples/cpu8080/cpu8080.v
FL $XILINX/ISEexamples/cpu8080/testbench.v 2006/09/22.09:36:04 I.33
MO isim_temp/testbench  FL $XILINX/ISEexamples/cpu8080/testbench.v MI cpu8080 \
      MI rom
MO isim_temp/rom        FL $XILINX/ISEexamples/cpu8080/testbench.v
FL $XILINX/verilog/src/glbl.v 2006/05/17.11:09:08 I.33
MO isim_temp/glbl       FL $XILINX/verilog/src/glbl.v

Line No.	Rev	Author	Line
1	2	samiam9512	`V3 11`
2			`FL $XILINX/ISEexamples/cpu8080/cpu8080.v 2006/09/20.00:13:38 I.33`
3			`MO isim_temp/cpu8080 FL $XILINX/ISEexamples/cpu8080/cpu8080.v MI alu`
4			`MO isim_temp/alu FL $XILINX/ISEexamples/cpu8080/cpu8080.v`
5			`FL $XILINX/ISEexamples/cpu8080/testbench.v 2006/09/22.09:36:04 I.33`
6			`MO isim_temp/testbench FL $XILINX/ISEexamples/cpu8080/testbench.v MI cpu8080 \`
7			`MI rom`
8			`MO isim_temp/rom FL $XILINX/ISEexamples/cpu8080/testbench.v`
9			`FL $XILINX/verilog/src/glbl.v 2006/05/17.11:09:08 I.33`
10			`MO isim_temp/glbl FL $XILINX/verilog/src/glbl.v`

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[/] [cpu8080/] [trunk/] [project/] [isim/] [temp/] [hdpdeps.ref] - Blame information for rev 33