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URL https://opencores.org/ocsvn/cpu8080/cpu8080/trunk

Subversion Repositories cpu8080

[/] [cpu8080/] [trunk/] [project/] [isim.log] - Blame information for rev 30

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Line No. Rev Author Line
1 2 samiam9512 
 command line:
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   ./cpu8080_tbw_isim_beh.exe
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     -intstyle  ise
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     -ipchost  localhost
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     -ipcport  1179
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Sat Nov 18 23:42:47 2006
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Total Line Count = 5816
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 Elaboration time 0.015625 sec.
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 Estimate current memory usage 36.7329 Meg.
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 Total signals 323
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 Total nets 542
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 Total signal drivers 184
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 Total blocks 40
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 Total primitive blocks 29
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 Total processes 186
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ntrace select -o on -n /cpu8080_tbw/clock
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ntrace select -o on -n /cpu8080_tbw/writemem
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ntrace select -o on -n /cpu8080_tbw/readmem
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ntrace select -o on -n /cpu8080_tbw/readio
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ntrace select -o on -n /cpu8080_tbw/writeio
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ntrace select -o on -n /cpu8080_tbw/data
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ntrace select -o on -n /cpu8080_tbw/addr
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ntrace select -o on -n /cpu8080_tbw/waitr
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ntrace select -o on -n /cpu8080_tbw/intr
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ntrace select -o on -n /cpu8080_tbw/inta
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ntrace select -o on -n /cpu8080_tbw/UUT/reset
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ntrace select -o on -n /cpu8080_tbw/UUT/cpu/zero
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ntrace select -o on -n /cpu8080_tbw/UUT/ramsel
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ntrace select -o on -n /cpu8080_tbw/UUT/romsel
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ntrace select -o on -n /cpu8080_tbw/UUT/cpu/state
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ntrace select -o on -n /cpu8080_tbw/UUT/cpu/statesel
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ntrace select -o on -n /cpu8080_tbw/UUT/cpu/rdatahold
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ntrace select -o on -n /cpu8080_tbw/UUT/cpu/carry
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ntrace select -o on -n /cpu8080_tbw/UUT/cpu/alures
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ntrace select -o on -n /cpu8080_tbw/UUT/cpu/waddrhold
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ntrace select -o on -n /cpu8080_tbw/UUT/cpu/wdatahold
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ntrace select -o on -n /cpu8080_tbw/UUT/cpu/aluopra
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ntrace select -o on -n /cpu8080_tbw/UUT/cpu/aluoprb
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ntrace select -o on -n /cpu8080_tbw/UUT/cpu/alucin
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ntrace select -o on -n /cpu8080_tbw/UUT/cpu/alusel
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ntrace select -o on -n /cpu8080_tbw/UUT/cpu/regfil
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WARNING:Simulator:131 - Request to trace variable regfil was ignored. Tracing of
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   array of vector type is not supported.
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ntrace select -o on -n /cpu8080_tbw/UUT/cpu/auxcar
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ntrace start
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run all
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Simulator is doing circuit initialization process.
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Finished circuit initialization process.

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