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[/] [cpu8080/] [trunk/] [project/] [netgen/] [par/] [testbench_timesim.nlf] - Blame information for rev 18
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samiam9512 |
Release 8.2.02i - netgen I.33
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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Command Line: netgen -intstyle ise -s 4 -pcf testbench.pcf -sdf_anno true
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-sdf_path netgen/par -insert_glbl true -w -dir netgen/par -ofmt verilog -sim
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testbench.ncd testbench_timesim.v
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Read and Annotate design 'testbench.ncd' ...
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Loading device for application Rf_Device from file '3s1000.nph' in environment
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C:\Xilinx.
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"testbench" is an NCD, version 3.1, device xc3s1000, package ft256, speed -4
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Loading constraints from 'testbench.pcf'...
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The speed grade (-4) differs from the speed grade specified in the .ncd file
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(-4).
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samiam9512 |
The number of routable networks is 5271
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samiam9512 |
Flattening design ...
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Processing design ...
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Preping design's networks ...
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Preping design's macros ...
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Writing Verilog SDF file 'netgen\par\testbench_timesim.sdf' ...
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Writing Verilog netlist file
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'C:\Xilinx\ISEexamples\cpu8080\netgen\par\testbench_timesim.v' ...
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INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx SIMPRIM
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simulation primitives and has to be used with SIMPRIM simulation library for
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correct compilation and simulation.
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Number of warnings: 0
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Number of info messages: 1
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samiam9512 |
Total memory usage is 217748 kilobytes
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