URL
https://opencores.org/ocsvn/cpu8080/cpu8080/trunk
[/] [cpu8080/] [trunk/] [project/] [netgen/] [par/] [testbench_timesim.nlf] - Blame information for rev 33
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
11 |
samiam9512 |
Release 8.2.02i - netgen I.33
|
| 2 |
|
|
Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
|
| 3 |
|
|
|
| 4 |
|
|
Command Line: netgen -intstyle ise -s 4 -pcf testbench.pcf -sdf_anno true
|
| 5 |
|
|
-sdf_path netgen/par -insert_glbl true -w -dir netgen/par -ofmt verilog -sim
|
| 6 |
|
|
testbench.ncd testbench_timesim.v
|
| 7 |
|
|
|
| 8 |
|
|
Read and Annotate design 'testbench.ncd' ...
|
| 9 |
|
|
Loading device for application Rf_Device from file '3s1000.nph' in environment
|
| 10 |
|
|
C:\Xilinx.
|
| 11 |
|
|
"testbench" is an NCD, version 3.1, device xc3s1000, package ft256, speed -4
|
| 12 |
|
|
Loading constraints from 'testbench.pcf'...
|
| 13 |
|
|
The speed grade (-4) differs from the speed grade specified in the .ncd file
|
| 14 |
|
|
(-4).
|
| 15 |
18 |
samiam9512 |
The number of routable networks is 5271
|
| 16 |
11 |
samiam9512 |
Flattening design ...
|
| 17 |
|
|
Processing design ...
|
| 18 |
|
|
Preping design's networks ...
|
| 19 |
|
|
Preping design's macros ...
|
| 20 |
|
|
Writing Verilog SDF file 'netgen\par\testbench_timesim.sdf' ...
|
| 21 |
|
|
Writing Verilog netlist file
|
| 22 |
|
|
'C:\Xilinx\ISEexamples\cpu8080\netgen\par\testbench_timesim.v' ...
|
| 23 |
|
|
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx SIMPRIM
|
| 24 |
|
|
simulation primitives and has to be used with SIMPRIM simulation library for
|
| 25 |
|
|
correct compilation and simulation.
|
| 26 |
|
|
Number of warnings: 0
|
| 27 |
|
|
Number of info messages: 1
|
| 28 |
18 |
samiam9512 |
Total memory usage is 217748 kilobytes
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.