URL https://opencores.org/ocsvn/cpu8080/cpu8080/trunk

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[/] [cpu8080/] [trunk/] [project/] [netgen/] [synthesis/] [_synthesis.nlf] - Blame information for rev 33

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Release 8.2.02i - netgen I.33
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
 
Command Line: netgen -intstyle ise -insert_glbl true -w -dir netgen/synthesis
-ofmt verilog -sim testbench.ngc _synthesis.v
 
Reading design 'testbench.ngc' ...
Flattening design ...
Processing design ...
  Preping design's networks ...
  Preping design's macros ...
Writing Verilog netlist file
'C:\Xilinx\ISEexamples\cpu8080\netgen\synthesis\_synthesis.v' ...
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx UNISIM
   simulation primitives and has to be used with UNISIM simulation library for
   correct compilation and simulation.
Number of warnings: 0
Number of info messages: 1
Total memory usage is 63980 kilobytes

Line No.	Rev	Author	Line
1	2	samiam9512	`Release 8.2.02i - netgen I.33`
2			`Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.`
3
4			`Command Line: netgen -intstyle ise -insert_glbl true -w -dir netgen/synthesis`
5			`-ofmt verilog -sim testbench.ngc _synthesis.v`
6
7			`Reading design 'testbench.ngc' ...`
8			`Flattening design ...`
9			`Processing design ...`
10			`Preping design's networks ...`
11			`Preping design's macros ...`
12			`Writing Verilog netlist file`
13			`'C:\Xilinx\ISEexamples\cpu8080\netgen\synthesis\_synthesis.v' ...`
14			`INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx UNISIM`
15			`simulation primitives and has to be used with UNISIM simulation library for`
16			`correct compilation and simulation.`
17			`Number of warnings: 0`
18			`Number of info messages: 1`
19	11	samiam9512	`Total memory usage is 63980 kilobytes`

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