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samiam9512 |
////////////////////////////////////////////////////////////////////////////////
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// Company: //
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// Engineer: Scott Moore //
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// //
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// Create Date: 11:45:32 09/04/2006 //
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// Design Name: //
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// Module Name: cpu8080 //
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// Project Name: cpu8080 //
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// Target Devices: xc3c200, xc3s1000 //
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// Tool versions: //
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// Description: //
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// //
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// Executes the 8080 instruction set. It is designed to be an internal //
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// cell. Each of the I/Os are positive logic, and all signals are //
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// constant with the exception of the data bus. The control signals are //
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// fully decoded (unlike the orignal 8080), and features read and write //
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// signals for both memory and I/O space. The I/O space is an 8 bit //
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// address as in the original 8080. It does NOT echo the lower 8 bits to //
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// the higher 8 bits, as was the practice in some systems. //
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// //
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// Like the original 8080, the interrupt vectoring is fully external. The //
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// the external controller forces a full instruction onto the data bus. //
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// The sequence begins with the assertion of interrupt request. The CPU //
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// will then assert interrupt acknowledge, then it will run a special //
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// read cycle with inta asserted for each cycle of a possibly //
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// multibyte instruction. This matches the original 8080, which typically //
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// used single byte restart instructions to form a simple interrupt //
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// controller, but was capable of full vectoring via insertion of a jump, //
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// call or similar instruction. //
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// //
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// Note that the interrupt vector instruction should branch. This is //
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// because the PC gets changed by the vector instruction, so if it does //
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// not branch, it will have skipped a number of bytes after the interrupt //
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// equivalent to the vector instruction. The only instructions that //
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// should really be used to vector are jmp, rst and call instructions. //
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// Specifically, rst and call instruction compensate for the pc movement //
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// by putting the pc unmodified on the stack. //
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// //
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// The memory, I/O and interrupt fetches all obey a simple clocking //
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// sequence as follows. The CPU uses the positive clock edge to assert //
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// and sample signals and data. The external logic theoretically uses the //
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// negative edge to check signal assertions and sample data, but it can //
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// either use the negative edge, or actually be asynronous logic. //
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// //
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// A standard read sequence is as follows: //
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// //
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// 1. At the positive clock edge, readmem, readio or readint is asserted. //
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// 2. At the negative clock edge (or immediately), the external memory //
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// places data onto the data bus. //
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// 3. We hold automatically for one cycle. //
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// 4. At the next positive clock edge, the data is sampled, and the read //
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// Signal is deasserted. //
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// //
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// A standard write sequence is as follows: //
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// //
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// 1. At the positive edge, data is asserted on the data bus. //
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// 2. At the next postive clock edge, writemem or writeio is asserted. //
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// 3. At the next positive clock edge, writemem or writeio is deasserted. //
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// 4. At the next positive edge, the data is deasserted. //
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// //
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// Dependencies: //
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// //
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// Revision: //
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// Revision 0.01 - File Created //
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// Additional Comments: //
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// //
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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//
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// CPU states
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//
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`define cpus_idle 6'h00 // Idle
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`define cpus_fetchi 6'h01 // Instruction fetch
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`define cpus_fetchi2 6'h02 // Instruction fetch 2
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`define cpus_fetchi3 6'h03 // Instruction fetch 3
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`define cpus_fetchi4 6'h04 // Instruction fetch 4
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`define cpus_halt 6'h05 // Halt (wait for interrupt)
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`define cpus_alucb 6'h06 // alu cycleback
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`define cpus_indcb 6'h07 // inr/dcr cycleback
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`define cpus_movmtbc 6'h08 // Move memory to bc
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`define cpus_movmtde 6'h09 // Move memory to de
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`define cpus_movmthl 6'h0a // Move memory to hl
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`define cpus_movmtsp 6'h0b // Move memory to sp
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`define cpus_lhld 6'h0c // LHLD
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`define cpus_jmp 6'h0d // JMP
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`define cpus_write 6'h0e // write byte
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`define cpus_write2 6'h0f // write byte #2
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`define cpus_write3 6'h10 // write byte #3
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`define cpus_write4 6'h11 // write byte #4
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`define cpus_read 6'h12 // read byte
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`define cpus_read2 6'h13 // read byte #2
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`define cpus_read3 6'h14 // read byte #3
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`define cpus_pop 6'h15 // POP completion
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`define cpus_in 6'h16 // IN
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`define cpus_in2 6'h17 // IN #2
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`define cpus_in3 6'h18 // IN #3
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`define cpus_out 6'h19 // OUT
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`define cpus_out2 6'h1a // OUT #2
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`define cpus_out3 6'h1b // OUT #3
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`define cpus_out4 6'h1c // OUT #4
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`define cpus_movtr 6'h1d // move to register
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`define cpus_movrtw 6'h1e // move read to write
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`define cpus_movrtwa 6'h1f // move read to write address
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`define cpus_movrtra 6'h20 // move read to read address
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`define cpus_accimm 6'h21 // accumulator immediate operations
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`define cpus_daa 6'h22 // DAA completion
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//
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// Register numbers
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//
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`define reg_b 3'b000 // B
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`define reg_c 3'b001 // C
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`define reg_d 3'b010 // D
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`define reg_e 3'b011 // E
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`define reg_h 3'b100 // H
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`define reg_l 3'b101 // L
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`define reg_m 3'b110 // M
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`define reg_a 3'b111 // A
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//
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// ALU operations
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//
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`define aluop_add 3'b000 // add
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`define aluop_adc 3'b001 // add with carry in
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`define aluop_sub 3'b010 // subtract
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`define aluop_sbb 3'b011 // subtract with borrow in
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`define aluop_and 3'b100 // and
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`define aluop_xor 3'b101 // xor
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`define aluop_or 3'b110 // or
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`define aluop_cmp 3'b111 // compare
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//
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// State macros
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//
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`define mac_writebyte 1 // write a byte
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`define mac_readbtoreg 2 // read a byte, place in register
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`define mac_readdtobc 4 // read double byte to BC
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`define mac_readdtode 6 // read double byte to DE
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`define mac_readdtohl 8 // read double byte to HL
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`define mac_readdtosp 10 // read double byte to SP
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`define mac_readbmtw 12 // read byte and move to write
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`define mac_readbmtr 14 // read byte and move to register
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`define mac_sta 16 // STA
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`define mac_lda 20 // LDA
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`define mac_shld 25 // SHLD
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`define mac_lhld 30 // LHLD
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`define mac_writedbyte 36 // write double byte
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`define mac_pop 38 // POP
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`define mac_xthl 40 // XTHL
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`define mac_accimm 44 // accumulator immediate
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`define mac_jmp 45 // JMP
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`define mac_call 47 // CALL
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`define mac_in 51 // IN
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`define mac_out 52 // OUT
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`define mac_rst 53 // RST
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module SM8080 (addr, // Address out
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data, // Data bus
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readmem, // Memory read
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writemem, // Memory write
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readio, // Read I/O space
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writeio, // Write I/O space
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intr, // Interrupt request
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inta, // Interrupt request
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waitr, // Wait request
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reset, // Reset
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clock); // System clock
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output [15:0] addr;
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inout [7:0] data;
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output readmem;
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output writemem;
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output readio;
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output writeio;
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input intr;
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output inta;
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input waitr;
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input reset;
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input clock; // synthesis clock
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// Output or input lines that need to be registered
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reg readmem;
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reg writemem;
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reg [15:0] pc;
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reg [15:0] addr;
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reg readio;
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reg writeio;
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reg inta;
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reg [15:0] sp;
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// Local registers
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reg [5:0] state; // CPU state machine
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reg [2:0] regd; // Destination register
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reg [7:0] datao; // Data output register
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reg dataeno; // Enable output data
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reg [15:0] waddrhold; // address holding for write
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reg [15:0] raddrhold; // address holding for read
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reg [7:0] wdatahold; // single byte write data holding
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reg [7:0] wdatahold2; // single byte write data holding
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reg [7:0] rdatahold; // single byte read data holding
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reg [7:0] rdatahold2; // single byte read data holding
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reg [1:0] popdes; // POP destination code
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reg [5:0] statesel; // state map selector
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reg [5:0] nextstate; // next state output
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reg eienb; // interrupt enable delay shift reg
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reg [7:0] opcode; // opcode holding
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// Register file. Note that 3'b110 (6) is not used, and is the code for a
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// memory reference.
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reg [7:0] regfil[0:7];
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// The flags are represented individually
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reg carry; // carry bit
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reg auxcar; // auxiliary carry bit
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reg sign; // sign bit
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reg zero; // zero bit
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reg parity; // parity bit
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reg ei; // interrupt enable
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reg intcyc; // in interrupt cycle
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// ALU communication
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wire [7:0] alures; // result
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reg [7:0] aluopra; // left side operand
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reg [7:0] aluoprb; // right side operand
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reg alucin; // carry in
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wire alucout; // carry out
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wire alupar; // parity out
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wire aluaxc; // auxiliary carry
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reg [2:0] alusel; // alu operational select
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wire aluzout; // CNS
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wire alusout; // CNS
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// Instantiate the ALU
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alu alu(alures, aluopra, aluoprb, alucin, alucout, aluzout, alusout, alupar, aluaxc, alusel);
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always @(posedge clock)
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if (reset) begin // syncronous reset actions
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state <= `cpus_fetchi; // Clear CPU state to initial fetch
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pc <= 0; // reset program counter to 1st location
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dataeno <= 0; // get off the data bus
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readmem <= 0; // all signals out false
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writemem<= 0;
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readio <= 0;
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writeio <= 0;
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inta <= 0;
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intcyc <= 0;
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ei <= 1;
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eienb <= 0;
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end else case (state)
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`cpus_fetchi: begin // start of instruction fetch
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// if interrupt request is on, enter interrupt cycle, else exit it now
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if (intr&&ei) begin
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intcyc <= 1;// enter interrupt cycle
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inta <= 1; // activate interrupt acknowledge
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ei <= 0; // disable interrupts
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end else begin
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intcyc <= 0; // leave interrupt cycle
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readmem <= 1; // activate instruction memory read
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end
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addr <= pc; // place current program count on output
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if (eienb) ei <=1; // process delayed interrupt enable
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eienb <=0; // reset interrupt enabler
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state <= `cpus_fetchi2; // next state
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end
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`cpus_fetchi2: begin // wait
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state <= `cpus_fetchi3; // next state
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end
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`cpus_fetchi3: begin // complete instruction memory read
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if (!waitr) begin // no wait selected, otherwise cycle
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opcode <= data; // latch opcode
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readmem <= 0; // Deactivate instruction memory read
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inta <= 0; // and interrupt acknowledge
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state <= `cpus_fetchi4; // next state
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end
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end
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`cpus_fetchi4: begin // complete instruction memory read
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// We split off the instructions into 4 groups. Most of the 8080
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// instructions are in the MOV and ACC operations class.
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case (opcode[7:6]) // Decode top level
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2'b00: begin // 00: Data transfers and others
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case (opcode[5:0]) // decode these instructions
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6'b000000: begin // NOP
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// yes, do nothing
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state <= `cpus_fetchi; // Fetch next instruction
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pc <= pc+1'b1; // Next instruction byte CNS
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end
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6'b110111: begin // STC
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carry <= 1; // set carry flag
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state <= `cpus_fetchi; // Fetch next instruction
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pc <= pc+1'b1; // Next instruction byte CNS
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end
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6'b111111: begin // CMC
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|
| 336 |
|
|
carry <= ~carry; // complement carry flag
|
| 337 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 338 |
|
|
pc <= pc+1'b1; // Next instruction byte CNS
|
| 339 |
|
|
|
| 340 |
|
|
end
|
| 341 |
|
|
|
| 342 |
|
|
6'b101111: begin // CMA
|
| 343 |
|
|
|
| 344 |
|
|
regfil[`reg_a] <= ~regfil[`reg_a]; // complement accumulator
|
| 345 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 346 |
|
|
pc <= pc+1'b1; // Next instruction byte CNS
|
| 347 |
|
|
|
| 348 |
|
|
end
|
| 349 |
|
|
|
| 350 |
|
|
6'b100111: begin // DAA
|
| 351 |
|
|
|
| 352 |
|
|
// decimal adjust accumulator, or remove by carry any
|
| 353 |
|
|
// results in nybbles greater than 9
|
| 354 |
|
|
|
| 355 |
|
|
if (regfil[`reg_a][3:0] > 9 || auxcar) begin
|
| 356 |
|
|
|
| 357 |
|
|
{ carry, regfil[`reg_a] } <= regfil[`reg_a]+ 3'b110; // CNS 6
|
| 358 |
|
|
auxcar <= ((regfil[`reg_a][3:0]+6 >> 4) & 1'b1) ? 1'b1:1'b0; // cns
|
| 359 |
|
|
|
| 360 |
|
|
end
|
| 361 |
|
|
state <= `cpus_daa; // finish DAA
|
| 362 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 363 |
|
|
|
| 364 |
|
|
end
|
| 365 |
|
|
|
| 366 |
|
|
6'b000100, 6'b001100, 6'b010100, 6'b011100, 6'b100100,
|
| 367 |
|
|
6'b101100, 6'b110100, 6'b111100, 6'b000101, 6'b001101,
|
| 368 |
|
|
6'b010101, 6'b011101, 6'b100101, 6'b101101, 6'b110101,
|
| 369 |
|
|
6'b111101: begin // INR/DCR
|
| 370 |
|
|
|
| 371 |
|
|
regd <= opcode[5:3]; // get source/destination reg
|
| 372 |
|
|
aluopra <= regfil[opcode[5:3]]; // load as alu a
|
| 373 |
|
|
aluoprb <= 1; // load 1 as alu b
|
| 374 |
|
|
if (opcode[0]) alusel <= `aluop_sub; // set subtract
|
| 375 |
|
|
else alusel <= `aluop_add; // set add
|
| 376 |
|
|
state <= `cpus_indcb; // go inr/dcr cycleback
|
| 377 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 378 |
|
|
|
| 379 |
|
|
end
|
| 380 |
|
|
|
| 381 |
|
|
6'b000010, 6'b010010: begin // STAX
|
| 382 |
|
|
|
| 383 |
|
|
wdatahold <= regfil[`reg_a]; // place A as source
|
| 384 |
|
|
if (opcode[4]) // use DE pair
|
| 385 |
|
|
waddrhold <= regfil[`reg_d]<<8|regfil[`reg_d];
|
| 386 |
|
|
else // use BC pair
|
| 387 |
|
|
waddrhold <= regfil[`reg_b] << 8|regfil[`reg_c];
|
| 388 |
|
|
statesel <= `mac_writebyte; // write byte
|
| 389 |
|
|
state <= `cpus_write;
|
| 390 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 391 |
|
|
|
| 392 |
|
|
end
|
| 393 |
|
|
|
| 394 |
|
|
6'b001010, 6'b011010: begin // LDAX
|
| 395 |
|
|
|
| 396 |
|
|
regd <= `reg_a; // set A as destination
|
| 397 |
|
|
if (opcode[4]) // use DE pair
|
| 398 |
|
|
raddrhold <= regfil[`reg_d]<<8|regfil[`reg_d];
|
| 399 |
|
|
else // use BC pair
|
| 400 |
|
|
raddrhold <= regfil[`reg_b]<<8|regfil[`reg_c];
|
| 401 |
|
|
statesel <= `mac_readbtoreg; // read byte to register
|
| 402 |
|
|
state <= `cpus_read;
|
| 403 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 404 |
|
|
|
| 405 |
|
|
end
|
| 406 |
|
|
|
| 407 |
|
|
6'b000111: begin // RLC
|
| 408 |
|
|
|
| 409 |
|
|
// rotate left circular
|
| 410 |
|
|
{ carry, regfil[`reg_a] } <=
|
| 411 |
|
|
(regfil[`reg_a] << 1)+regfil[`reg_a][7];
|
| 412 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 413 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 414 |
|
|
|
| 415 |
|
|
end
|
| 416 |
|
|
|
| 417 |
|
|
6'b010111: begin // RAL
|
| 418 |
|
|
|
| 419 |
|
|
// rotate left through carry
|
| 420 |
|
|
{ carry, regfil[`reg_a] } <= (regfil[`reg_a] << 1)+carry;
|
| 421 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 422 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 423 |
|
|
|
| 424 |
|
|
end
|
| 425 |
|
|
|
| 426 |
|
|
6'b001111: begin // RRC
|
| 427 |
|
|
|
| 428 |
|
|
// rotate right circular
|
| 429 |
|
|
regfil[`reg_a] <=
|
| 430 |
|
|
(regfil[`reg_a] >> 1)+(regfil[`reg_a][0] << 7);
|
| 431 |
|
|
carry <= regfil[`reg_a][0];
|
| 432 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 433 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 434 |
|
|
|
| 435 |
|
|
end
|
| 436 |
|
|
|
| 437 |
|
|
6'b011111: begin // RAR
|
| 438 |
|
|
|
| 439 |
|
|
// rotate right through carry
|
| 440 |
|
|
regfil[`reg_a] <= (regfil[`reg_a] >> 1)+(carry << 7);
|
| 441 |
|
|
carry <= regfil[`reg_a][0];
|
| 442 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 443 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 444 |
|
|
|
| 445 |
|
|
end
|
| 446 |
|
|
|
| 447 |
|
|
6'b001001: begin // DAD B
|
| 448 |
|
|
|
| 449 |
|
|
// add BC to HL
|
| 450 |
|
|
{ carry, regfil[`reg_h], regfil[`reg_l] } <=
|
| 451 |
|
|
(regfil[`reg_h] << 8)+regfil[`reg_l]+
|
| 452 |
|
|
(regfil[`reg_b] << 8)+regfil[`reg_c];
|
| 453 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 454 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 455 |
|
|
|
| 456 |
|
|
end
|
| 457 |
|
|
|
| 458 |
|
|
6'b011001: begin // DAD D
|
| 459 |
|
|
|
| 460 |
|
|
// add DE to HL
|
| 461 |
|
|
{ carry, regfil[`reg_h], regfil[`reg_l] } <=
|
| 462 |
|
|
(regfil[`reg_h] << 8)+regfil[`reg_l]+
|
| 463 |
|
|
(regfil[`reg_d] << 8)+regfil[`reg_e];
|
| 464 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 465 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 466 |
|
|
|
| 467 |
|
|
end
|
| 468 |
|
|
|
| 469 |
|
|
6'b101001: begin // DAD H
|
| 470 |
|
|
|
| 471 |
|
|
// add HL to HL
|
| 472 |
|
|
{ carry, regfil[`reg_h], regfil[`reg_l] } <=
|
| 473 |
|
|
(regfil[`reg_h] << 8)+regfil[`reg_l]+
|
| 474 |
|
|
(regfil[`reg_h] << 8)+regfil[`reg_l];
|
| 475 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 476 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 477 |
|
|
|
| 478 |
|
|
end
|
| 479 |
|
|
|
| 480 |
|
|
6'b111001: begin // DAD SP
|
| 481 |
|
|
|
| 482 |
|
|
// add SP to HL
|
| 483 |
|
|
{ carry, regfil[`reg_h], regfil[`reg_l] } <=
|
| 484 |
|
|
(regfil[`reg_h] << 8)+regfil[`reg_l]+sp;
|
| 485 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 486 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 487 |
|
|
|
| 488 |
|
|
end
|
| 489 |
|
|
|
| 490 |
|
|
6'b000011: begin // INX B
|
| 491 |
|
|
|
| 492 |
|
|
// increment BC, no flags set
|
| 493 |
|
|
regfil[`reg_b] <=
|
| 494 |
|
|
(((regfil[`reg_b] << 8)+regfil[`reg_c])+1'b1)>>8;
|
| 495 |
|
|
regfil[`reg_c] <=
|
| 496 |
|
|
((regfil[`reg_b] << 8)+regfil[`reg_c])+1'b1;
|
| 497 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 498 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 499 |
|
|
|
| 500 |
|
|
end
|
| 501 |
|
|
|
| 502 |
|
|
6'b010011: begin // INX D
|
| 503 |
|
|
|
| 504 |
|
|
// increment DE, no flags set
|
| 505 |
|
|
regfil[`reg_d] <=
|
| 506 |
|
|
(((regfil[`reg_d] << 8)+regfil[`reg_e])+1'b1)>>8;
|
| 507 |
|
|
regfil[`reg_e] <=
|
| 508 |
|
|
((regfil[`reg_d] << 8)+regfil[`reg_e])+1'b1;
|
| 509 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 510 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 511 |
|
|
|
| 512 |
|
|
end
|
| 513 |
|
|
|
| 514 |
|
|
6'b100011: begin // INX H
|
| 515 |
|
|
|
| 516 |
|
|
// increment HL, no flags set
|
| 517 |
|
|
regfil[`reg_h] <=
|
| 518 |
|
|
(((regfil[`reg_h] << 8)+regfil[`reg_l])+1'b1)>>8;
|
| 519 |
|
|
regfil[`reg_l] <=
|
| 520 |
|
|
((regfil[`reg_h] << 8)+regfil[`reg_l])+1'b1;
|
| 521 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 522 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 523 |
|
|
|
| 524 |
|
|
end
|
| 525 |
|
|
|
| 526 |
|
|
6'b110011: begin // INX SP
|
| 527 |
|
|
|
| 528 |
|
|
// increment SP, no flags set
|
| 529 |
|
|
sp <= sp + 16'b1;
|
| 530 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 531 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 532 |
|
|
|
| 533 |
|
|
end
|
| 534 |
|
|
|
| 535 |
|
|
6'b001011: begin // DCX B
|
| 536 |
|
|
|
| 537 |
|
|
// decrement BC, no flags set
|
| 538 |
|
|
regfil[`reg_b] <=
|
| 539 |
|
|
(((regfil[`reg_b] << 8)+regfil[`reg_c]) - 8'b1)>>8;
|
| 540 |
|
|
regfil[`reg_c] <=
|
| 541 |
|
|
((regfil[`reg_b] << 8)+regfil[`reg_c])- 8'b1;
|
| 542 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 543 |
|
|
pc <= pc + 1'b1; // Next instruction byte
|
| 544 |
|
|
|
| 545 |
|
|
end
|
| 546 |
|
|
|
| 547 |
|
|
6'b011011: begin // DCX D
|
| 548 |
|
|
|
| 549 |
|
|
// decrement DE, no flags set
|
| 550 |
|
|
regfil[`reg_d] <=
|
| 551 |
|
|
(((regfil[`reg_d] << 8)+regfil[`reg_e]) - 8'b1)>>8;
|
| 552 |
|
|
regfil[`reg_e] <=
|
| 553 |
|
|
((regfil[`reg_d] << 8)+regfil[`reg_e])- 8'd11; // cns 11
|
| 554 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 555 |
|
|
pc <= pc + 1'b1; // Next instruction byte
|
| 556 |
|
|
|
| 557 |
|
|
end
|
| 558 |
|
|
|
| 559 |
|
|
6'b101011: begin // DCX H
|
| 560 |
|
|
|
| 561 |
|
|
// decrement HL, no flags set
|
| 562 |
|
|
regfil[`reg_h] <=
|
| 563 |
|
|
(((regfil[`reg_h] << 8)+regfil[`reg_l])- 8'b1)>>8;
|
| 564 |
|
|
regfil[`reg_l] <=
|
| 565 |
|
|
((regfil[`reg_h] << 8)+regfil[`reg_l]) - 8'b1;
|
| 566 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 567 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 568 |
|
|
|
| 569 |
|
|
end
|
| 570 |
|
|
|
| 571 |
|
|
6'b111011: begin // DCX SP
|
| 572 |
|
|
|
| 573 |
|
|
// decrement SP, no flags set
|
| 574 |
|
|
sp <= sp - 16'b1;
|
| 575 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 576 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 577 |
|
|
|
| 578 |
|
|
end
|
| 579 |
|
|
|
| 580 |
|
|
6'b000001: begin // LXI B
|
| 581 |
|
|
|
| 582 |
|
|
raddrhold <= pc+1'b1; // pick up after instruction
|
| 583 |
|
|
statesel <= `mac_readdtobc; // read double to BC
|
| 584 |
|
|
state <= `cpus_read;
|
| 585 |
|
|
pc <= pc + 16'h3; // skip
|
| 586 |
|
|
|
| 587 |
|
|
end
|
| 588 |
|
|
|
| 589 |
|
|
6'b010001: begin // LXI D
|
| 590 |
|
|
|
| 591 |
|
|
raddrhold <= pc+1'b1; // pick up after instruction
|
| 592 |
|
|
statesel <= `mac_readdtode; // read double to DE
|
| 593 |
|
|
state <= `cpus_read;
|
| 594 |
|
|
pc <= pc + 16'h3; // skip
|
| 595 |
|
|
|
| 596 |
|
|
end
|
| 597 |
|
|
|
| 598 |
|
|
6'b100001: begin // LXI H
|
| 599 |
|
|
|
| 600 |
|
|
raddrhold <= pc+1'b1; // pick up after instruction
|
| 601 |
|
|
statesel <= `mac_readdtohl; // read double to HL
|
| 602 |
|
|
state <= `cpus_read;
|
| 603 |
|
|
pc <= pc + 16'h3; // skip
|
| 604 |
|
|
|
| 605 |
|
|
end
|
| 606 |
|
|
|
| 607 |
|
|
6'b110001: begin // LXI SP
|
| 608 |
|
|
|
| 609 |
|
|
raddrhold <= pc+1'b1; // pick up after instruction
|
| 610 |
|
|
pc <= pc + 16'h3; // skip
|
| 611 |
|
|
statesel <= `mac_readdtosp; // read double to SP
|
| 612 |
|
|
state <= `cpus_read;
|
| 613 |
|
|
pc <= pc + 16'h3; // skip
|
| 614 |
|
|
|
| 615 |
|
|
end
|
| 616 |
|
|
|
| 617 |
|
|
6'b000110, 6'b001110, 6'b010110, 6'b011110, 6'b100110,
|
| 618 |
|
|
6'b101110, 6'b110110, 6'b111110: begin // MVI
|
| 619 |
|
|
|
| 620 |
|
|
// move immediate to register
|
| 621 |
|
|
regd <= opcode[5:3]; // set destination register
|
| 622 |
|
|
raddrhold <= pc+1'b1; // set pickup address
|
| 623 |
|
|
if (opcode[5:3] == `reg_m) begin // it's mvi m,imm
|
| 624 |
|
|
|
| 625 |
|
|
regd <= opcode[5:3]; // set destination register
|
| 626 |
|
|
// set destination address
|
| 627 |
|
|
waddrhold <= { regfil[`reg_h], regfil[`reg_l] };
|
| 628 |
|
|
statesel <= `mac_readbmtw; // read byte and move to write
|
| 629 |
|
|
|
| 630 |
|
|
end else
|
| 631 |
|
|
statesel <= `mac_readbmtr; // read byte and move to register
|
| 632 |
|
|
state <= `cpus_read;
|
| 633 |
|
|
pc <= pc + 16'h2; // advance over byte
|
| 634 |
|
|
|
| 635 |
|
|
end
|
| 636 |
|
|
|
| 637 |
|
|
6'b110010: begin // STA
|
| 638 |
|
|
|
| 639 |
|
|
wdatahold <= regfil[`reg_a]; // set write data
|
| 640 |
|
|
raddrhold <= pc+1'b1; // set read address
|
| 641 |
|
|
statesel <= `mac_sta; // perform sta
|
| 642 |
|
|
state <= `cpus_read;
|
| 643 |
|
|
pc <= pc + 16'h3; // next
|
| 644 |
|
|
|
| 645 |
|
|
end
|
| 646 |
|
|
|
| 647 |
|
|
6'b111010: begin // LDA
|
| 648 |
|
|
|
| 649 |
|
|
raddrhold <= pc+1'b1; // set read address
|
| 650 |
|
|
regd <= `reg_a; // set destination
|
| 651 |
|
|
statesel <= `mac_lda; // perform lda
|
| 652 |
|
|
state <= `cpus_read;
|
| 653 |
|
|
pc <= pc + 16'h3; // next
|
| 654 |
|
|
|
| 655 |
|
|
end
|
| 656 |
|
|
|
| 657 |
|
|
6'b100010: begin // SHLD
|
| 658 |
|
|
|
| 659 |
|
|
wdatahold <= regfil[`reg_l]; // set write data
|
| 660 |
|
|
wdatahold2 <= regfil[`reg_h];
|
| 661 |
|
|
raddrhold <= pc+1'b1; // set read address
|
| 662 |
|
|
statesel <= `mac_shld; // perform SHLD
|
| 663 |
|
|
state <= `cpus_read;
|
| 664 |
|
|
pc <= pc + 16'h3; // next
|
| 665 |
|
|
|
| 666 |
|
|
end
|
| 667 |
|
|
|
| 668 |
|
|
6'b101010: begin // LHLD
|
| 669 |
|
|
|
| 670 |
|
|
raddrhold <= pc+1'b1; // set read address
|
| 671 |
|
|
statesel <= `mac_lhld; // perform LHLD
|
| 672 |
|
|
state <= `cpus_read;
|
| 673 |
|
|
pc <= pc + 16'h3; // next
|
| 674 |
|
|
|
| 675 |
|
|
end
|
| 676 |
|
|
|
| 677 |
|
|
// the illegal opcodes behave as NOPs
|
| 678 |
|
|
|
| 679 |
|
|
6'b001000, 6'b010000, 6'b011000, 6'b100000, 6'b101000,
|
| 680 |
|
|
6'b110000, 6'b110000: begin
|
| 681 |
|
|
|
| 682 |
|
|
state <= `cpus_fetchi; // fetch next instruction
|
| 683 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 684 |
|
|
|
| 685 |
|
|
end
|
| 686 |
|
|
|
| 687 |
|
|
endcase
|
| 688 |
|
|
|
| 689 |
|
|
end
|
| 690 |
|
|
|
| 691 |
|
|
2'b01: begin // 01: MOV instruction
|
| 692 |
|
|
|
| 693 |
|
|
// Check its the halt instruction, which occupies the invalid
|
| 694 |
|
|
// "MOV M,M" instruction.
|
| 695 |
|
|
if (opcode == 8'b01110110) state <= `cpus_halt;
|
| 696 |
|
|
// Otherwise, the 01 prefix is single instruction format.
|
| 697 |
|
|
else begin
|
| 698 |
|
|
|
| 699 |
|
|
// Format 01DDDSSS
|
| 700 |
|
|
|
| 701 |
|
|
// Check memory source, use state if so
|
| 702 |
|
|
if (opcode[2:0] == `reg_m) begin
|
| 703 |
|
|
|
| 704 |
|
|
// place hl as address
|
| 705 |
|
|
raddrhold <= regfil[`reg_h]<<8|regfil[`reg_l];
|
| 706 |
|
|
regd <= opcode[5:3]; // set destination
|
| 707 |
|
|
statesel <= `mac_readbtoreg; // read byte to register
|
| 708 |
|
|
state <= `cpus_read;
|
| 709 |
|
|
|
| 710 |
|
|
// Check memory destination, use state if so
|
| 711 |
|
|
end else if (regd == `reg_m) begin
|
| 712 |
|
|
|
| 713 |
|
|
// place hl as address
|
| 714 |
|
|
waddrhold <= regfil[`reg_h]<<8|regfil[`reg_l];
|
| 715 |
|
|
wdatahold <= regfil[opcode[2:0]]; // place data to write
|
| 716 |
|
|
statesel <= `mac_writebyte; // write byte
|
| 717 |
|
|
state <= `cpus_write;
|
| 718 |
|
|
|
| 719 |
|
|
// otherwise simple register to register
|
| 720 |
|
|
end else begin
|
| 721 |
|
|
|
| 722 |
|
|
regfil[opcode[5:3]] <= regfil[opcode[2:0]];
|
| 723 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 724 |
|
|
|
| 725 |
|
|
end
|
| 726 |
|
|
|
| 727 |
|
|
end
|
| 728 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 729 |
|
|
|
| 730 |
|
|
end
|
| 731 |
|
|
|
| 732 |
|
|
2'b10: begin // 10: Reg or mem to accumulator ops
|
| 733 |
|
|
|
| 734 |
|
|
// 10 prefix is single instruction format
|
| 735 |
|
|
aluopra <= regfil[`reg_a]; // load as alu a
|
| 736 |
|
|
aluoprb <= regfil[opcode[2:0]]; // load as alu b
|
| 737 |
|
|
alusel <= opcode[5:3]; // set alu operation from instruction
|
| 738 |
|
|
alucin <= carry; // input carry
|
| 739 |
|
|
if (opcode[2:0] == `reg_m) begin
|
| 740 |
|
|
|
| 741 |
|
|
// set read address
|
| 742 |
|
|
raddrhold <= regfil[`reg_h]<<8|regfil[`reg_l];
|
| 743 |
|
|
regd <= `reg_a; // set destination always a
|
| 744 |
|
|
statesel <= `mac_readbtoreg; // read byte to register
|
| 745 |
|
|
state <= `cpus_read;
|
| 746 |
|
|
|
| 747 |
|
|
end else
|
| 748 |
|
|
state <= `cpus_alucb; // go to alu cycleback
|
| 749 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 750 |
|
|
|
| 751 |
|
|
end
|
| 752 |
|
|
|
| 753 |
|
|
2'b11: begin // 11: jmp/call and others
|
| 754 |
|
|
|
| 755 |
|
|
case (opcode[5:0]) // decode these instructions
|
| 756 |
|
|
|
| 757 |
|
|
6'b000101, 6'b010101, 6'b100101, 6'b110101: begin // PUSH
|
| 758 |
|
|
|
| 759 |
|
|
waddrhold <= sp - 16'h2; // write to stack
|
| 760 |
|
|
sp <= sp - 16'h2; // pushdown stack
|
| 761 |
|
|
case (opcode[5:4]) // register set
|
| 762 |
|
|
|
| 763 |
|
|
2'b00: { wdatahold2, wdatahold } <=
|
| 764 |
|
|
{ regfil[`reg_b], regfil[`reg_c] };
|
| 765 |
|
|
2'b01: { wdatahold2, wdatahold } <=
|
| 766 |
|
|
{ regfil[`reg_d], regfil[`reg_e] };
|
| 767 |
|
|
2'b10: { wdatahold2, wdatahold } <=
|
| 768 |
|
|
{ regfil[`reg_h], regfil[`reg_l] };
|
| 769 |
|
|
2'b11: { wdatahold2, wdatahold } <=
|
| 770 |
|
|
{ regfil[`reg_a], sign, zero, 1'b0, auxcar,
|
| 771 |
|
|
1'b0, parity, 1'b1, carry };
|
| 772 |
|
|
|
| 773 |
|
|
endcase
|
| 774 |
|
|
statesel <= `mac_writedbyte; // write double byte
|
| 775 |
|
|
state <= `cpus_write;
|
| 776 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 777 |
|
|
|
| 778 |
|
|
end
|
| 779 |
|
|
|
| 780 |
|
|
6'b000001, 6'b010001, 6'b100001, 6'b110001: begin // POP
|
| 781 |
|
|
|
| 782 |
|
|
popdes <= opcode[5:4]; // set destination
|
| 783 |
|
|
raddrhold <= sp; // read from stack
|
| 784 |
|
|
sp <= sp + 16'h2; // pushup stack
|
| 785 |
|
|
statesel <= `mac_pop; // perform POP
|
| 786 |
|
|
state <= `cpus_read;
|
| 787 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 788 |
|
|
|
| 789 |
|
|
end
|
| 790 |
|
|
|
| 791 |
|
|
6'b101011: begin // XCHG
|
| 792 |
|
|
|
| 793 |
|
|
regfil[`reg_d] <= regfil[`reg_h];
|
| 794 |
|
|
regfil[`reg_e] <= regfil[`reg_l];
|
| 795 |
|
|
regfil[`reg_h] <= regfil[`reg_d];
|
| 796 |
|
|
regfil[`reg_l] <= regfil[`reg_e];
|
| 797 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 798 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 799 |
|
|
|
| 800 |
|
|
end
|
| 801 |
|
|
|
| 802 |
|
|
6'b100011: begin // XTHL
|
| 803 |
|
|
|
| 804 |
|
|
raddrhold <= sp; // address SP for read
|
| 805 |
|
|
waddrhold <= sp; // address SP for write
|
| 806 |
|
|
wdatahold <= regfil[`reg_l]; // set data is HL
|
| 807 |
|
|
wdatahold2 <= regfil[`reg_h];
|
| 808 |
|
|
statesel <= `mac_xthl; // perform XTHL
|
| 809 |
|
|
state <= `cpus_read;
|
| 810 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 811 |
|
|
|
| 812 |
|
|
end
|
| 813 |
|
|
|
| 814 |
|
|
6'b111001: begin // SPHL
|
| 815 |
|
|
|
| 816 |
|
|
sp <= { regfil[`reg_h], regfil[`reg_l] };
|
| 817 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 818 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 819 |
|
|
|
| 820 |
|
|
end
|
| 821 |
|
|
|
| 822 |
|
|
6'b000110, 6'b001110, 6'b010110, 6'b011110, 6'b100110,
|
| 823 |
|
|
6'b101110, 6'b110110,
|
| 824 |
|
|
6'b111110: begin // immediate arithmetic to accumulator
|
| 825 |
|
|
|
| 826 |
|
|
aluopra <= regfil[`reg_a]; // load as alu a
|
| 827 |
|
|
alusel <= opcode[5:3]; // set alu operation from instruction
|
| 828 |
|
|
alucin <= carry; // input carry
|
| 829 |
|
|
raddrhold <= pc + 1'b1; // read at PC
|
| 830 |
|
|
statesel <= `mac_accimm; // finish accumulator immediate
|
| 831 |
|
|
state <= `cpus_read;
|
| 832 |
|
|
pc <= pc + 16'h2; // skip immediate byte
|
| 833 |
|
|
|
| 834 |
|
|
end
|
| 835 |
|
|
|
| 836 |
|
|
6'b101001: begin // PCHL
|
| 837 |
|
|
|
| 838 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 839 |
|
|
pc <= { regfil[`reg_h], regfil[`reg_l] };
|
| 840 |
|
|
|
| 841 |
|
|
end
|
| 842 |
|
|
|
| 843 |
|
|
6'b000011: begin // JMP
|
| 844 |
|
|
|
| 845 |
|
|
raddrhold <= pc+1'b1; // pick up jump address
|
| 846 |
|
|
statesel <= `mac_jmp; // finish JMP
|
| 847 |
|
|
state <= `cpus_read;
|
| 848 |
|
|
|
| 849 |
|
|
end
|
| 850 |
|
|
|
| 851 |
|
|
6'b000010, 6'b001010, 6'b010010, 6'b011010, 6'b100010,
|
| 852 |
|
|
6'b101010, 6'b110010, 6'b111010: begin // Jcc
|
| 853 |
|
|
|
| 854 |
|
|
raddrhold <= pc+1'b1; // pick up jump address
|
| 855 |
|
|
statesel <= `mac_jmp; // finish JMP
|
| 856 |
|
|
// choose continue or read according to condition
|
| 857 |
|
|
case (opcode[5:3]) // decode flag cases
|
| 858 |
|
|
|
| 859 |
|
|
3'b000: if (zero) state <= `cpus_fetchi;
|
| 860 |
|
|
else state <= `cpus_read;
|
| 861 |
|
|
3'b001: if (!zero) state <= `cpus_fetchi;
|
| 862 |
|
|
else state <= `cpus_read;
|
| 863 |
|
|
3'b010: if (carry) state <= `cpus_fetchi;
|
| 864 |
|
|
else state <= `cpus_read;
|
| 865 |
|
|
3'b011: if (!carry) state <= `cpus_fetchi;
|
| 866 |
|
|
else state <= `cpus_read;
|
| 867 |
|
|
3'b100: if (parity) state <= `cpus_fetchi;
|
| 868 |
|
|
else state <= `cpus_read;
|
| 869 |
|
|
3'b101: if (!parity) state <= `cpus_fetchi;
|
| 870 |
|
|
else state <= `cpus_read;
|
| 871 |
|
|
3'b110: if (sign) state <= `cpus_fetchi;
|
| 872 |
|
|
else state <= `cpus_read;
|
| 873 |
|
|
3'b111: if (!sign) state <= `cpus_fetchi;
|
| 874 |
|
|
else state <= `cpus_read;
|
| 875 |
|
|
|
| 876 |
|
|
endcase
|
| 877 |
|
|
pc <= pc + 16'h3; // advance after jump for false
|
| 878 |
|
|
|
| 879 |
|
|
end
|
| 880 |
|
|
|
| 881 |
|
|
6'b001101: begin // CALL
|
| 882 |
|
|
|
| 883 |
|
|
raddrhold <= pc+1'b1; // pick up call address
|
| 884 |
|
|
waddrhold <= sp - 16'h2; // place address on stack
|
| 885 |
|
|
// if interrupt cycle, use current pc, else use address
|
| 886 |
|
|
// after call
|
| 887 |
|
|
if (intcyc) { wdatahold2, wdatahold } <= pc;
|
| 888 |
|
|
else { wdatahold2, wdatahold } <= pc + 16'h3;
|
| 889 |
|
|
sp <= sp - 16'h2; // pushdown stack
|
| 890 |
|
|
statesel <= `mac_call; // finish CALL
|
| 891 |
|
|
state <= `cpus_read;
|
| 892 |
|
|
|
| 893 |
|
|
end
|
| 894 |
|
|
|
| 895 |
|
|
6'b000100, 6'b001100, 6'b010100, 6'b011100, 6'b100100,
|
| 896 |
|
|
6'b101100, 6'b110100, 6'b111100: begin // Ccc
|
| 897 |
|
|
|
| 898 |
|
|
raddrhold <= pc + 1'b1; // pick up call address
|
| 899 |
|
|
waddrhold <= sp - 16'h2; // place address on stack
|
| 900 |
|
|
{ wdatahold2, wdatahold } <= pc + 16'h3; // of address after call
|
| 901 |
|
|
sp <= sp - 16'h2; // pushdown stack
|
| 902 |
|
|
statesel <= `mac_call; // finish CALL
|
| 903 |
|
|
// choose continue or read according to condition
|
| 904 |
|
|
case (opcode[5:3]) // decode flag cases
|
| 905 |
|
|
|
| 906 |
|
|
3'b000: if (zero) state <= `cpus_fetchi;
|
| 907 |
|
|
else state <= `cpus_read;
|
| 908 |
|
|
3'b001: if (!zero) state <= `cpus_fetchi;
|
| 909 |
|
|
else state <= `cpus_read;
|
| 910 |
|
|
3'b010: if (carry) state <= `cpus_fetchi;
|
| 911 |
|
|
else state <= `cpus_read;
|
| 912 |
|
|
3'b011: if (!carry) state <= `cpus_fetchi;
|
| 913 |
|
|
else state <= `cpus_read;
|
| 914 |
|
|
3'b100: if (parity) state <= `cpus_fetchi;
|
| 915 |
|
|
else state <= `cpus_read;
|
| 916 |
|
|
3'b101: if (!parity) state <= `cpus_fetchi;
|
| 917 |
|
|
else state <= `cpus_read;
|
| 918 |
|
|
3'b110: if (sign) state <= `cpus_fetchi;
|
| 919 |
|
|
else state <= `cpus_read;
|
| 920 |
|
|
3'b111: if (!sign) state <= `cpus_fetchi;
|
| 921 |
|
|
else state <= `cpus_read;
|
| 922 |
|
|
|
| 923 |
|
|
endcase
|
| 924 |
|
|
pc <= pc + 16'h3; // advance after jump for false
|
| 925 |
|
|
|
| 926 |
|
|
end
|
| 927 |
|
|
|
| 928 |
|
|
6'b001001: begin // RET
|
| 929 |
|
|
|
| 930 |
|
|
raddrhold <= sp; // read from stack
|
| 931 |
|
|
sp <= sp + 16'h2; // pushup stack
|
| 932 |
|
|
statesel <= `mac_jmp; // finish JMP
|
| 933 |
|
|
state <= `cpus_read;
|
| 934 |
|
|
|
| 935 |
|
|
end
|
| 936 |
|
|
|
| 937 |
|
|
6'b000000, 6'b001000, 6'b010000, 6'b011000, 6'b100000,
|
| 938 |
|
|
6'b101000, 6'b110000, 6'b111000: begin // Rcc
|
| 939 |
|
|
|
| 940 |
|
|
raddrhold <= sp; // read from stack
|
| 941 |
|
|
sp <= sp + 16'h2; // pushup stack
|
| 942 |
|
|
statesel <= `mac_jmp; // finish JMP
|
| 943 |
|
|
// choose read or continue according to condition
|
| 944 |
|
|
case (opcode[5:3]) // decode flag cases
|
| 945 |
|
|
|
| 946 |
|
|
3'b000: if (zero) state <= `cpus_fetchi;
|
| 947 |
|
|
else state <= `cpus_read;
|
| 948 |
|
|
3'b001: if (!zero) state <= `cpus_fetchi;
|
| 949 |
|
|
else state <= `cpus_read;
|
| 950 |
|
|
3'b010: if (carry) state <= `cpus_fetchi;
|
| 951 |
|
|
else state <= `cpus_read;
|
| 952 |
|
|
3'b011: if (!carry) state <= `cpus_fetchi;
|
| 953 |
|
|
else state <= `cpus_read;
|
| 954 |
|
|
3'b100: if (parity) state <= `cpus_fetchi;
|
| 955 |
|
|
else state <= `cpus_read;
|
| 956 |
|
|
3'b101: if (!parity) state <= `cpus_fetchi;
|
| 957 |
|
|
else state <= `cpus_read;
|
| 958 |
|
|
3'b110: if (sign) state <= `cpus_fetchi;
|
| 959 |
|
|
else state <= `cpus_read;
|
| 960 |
|
|
3'b111: if (!sign) state <= `cpus_fetchi;
|
| 961 |
|
|
else state <= `cpus_read;
|
| 962 |
|
|
|
| 963 |
|
|
endcase
|
| 964 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 965 |
|
|
|
| 966 |
|
|
end
|
| 967 |
|
|
|
| 968 |
|
|
6'b000111, 6'b001111, 6'b010111, 6'b011111, 6'b100111,
|
| 969 |
|
|
6'b101111, 6'b110111, 6'b111111: begin // RST
|
| 970 |
|
|
|
| 971 |
|
|
pc <= opcode & 8'b00111000; // place restart value in PC
|
| 972 |
|
|
waddrhold <= sp - 16'h2; // place address on stack
|
| 973 |
|
|
// if interrupt cycle, use current pc, else use address
|
| 974 |
|
|
// after call
|
| 975 |
|
|
if (intcyc) { wdatahold2, wdatahold } <= pc;
|
| 976 |
|
|
else { wdatahold2, wdatahold } <= pc + 16'h3; // cns 3
|
| 977 |
|
|
{ wdatahold2, wdatahold } <= pc + 1'b1; // of address after call
|
| 978 |
|
|
sp <= sp - 16'h2; // pushdown stack CNS 2
|
| 979 |
|
|
statesel <= `mac_writedbyte; // finish RST
|
| 980 |
|
|
state <= `cpus_write; // write to stack
|
| 981 |
|
|
|
| 982 |
|
|
end
|
| 983 |
|
|
|
| 984 |
|
|
6'b111011: begin // EI
|
| 985 |
|
|
|
| 986 |
|
|
eienb <= 1'b1; // set delayed interrupt enable
|
| 987 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 988 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 989 |
|
|
|
| 990 |
|
|
end
|
| 991 |
|
|
|
| 992 |
|
|
6'b110011: begin // DI
|
| 993 |
|
|
|
| 994 |
|
|
ei <= 1'b0;
|
| 995 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 996 |
|
|
pc <= pc+1'b1; // Next instruction byte
|
| 997 |
|
|
|
| 998 |
|
|
end
|
| 999 |
|
|
|
| 1000 |
|
|
6'b011011: begin // IN p
|
| 1001 |
|
|
|
| 1002 |
|
|
raddrhold <= pc+1'b1; // pick up byte I/O address
|
| 1003 |
|
|
pc <= pc + 2'b10; // next
|
| 1004 |
|
|
statesel <= `mac_in; // finish IN
|
| 1005 |
|
|
state <= `cpus_read;
|
| 1006 |
|
|
pc <= pc + 2'b10; // Next instruction byte
|
| 1007 |
|
|
|
| 1008 |
|
|
end
|
| 1009 |
|
|
|
| 1010 |
|
|
6'b010011: begin // OUT p
|
| 1011 |
|
|
|
| 1012 |
|
|
raddrhold <= pc+1'b1; // pick up byte I/O address
|
| 1013 |
|
|
pc <= pc + 2'b10; // next
|
| 1014 |
|
|
statesel <= `mac_out; // finish OUT
|
| 1015 |
|
|
state <= `cpus_read;
|
| 1016 |
|
|
pc <= pc + 2'b10; // Next instruction byte
|
| 1017 |
|
|
|
| 1018 |
|
|
end
|
| 1019 |
|
|
|
| 1020 |
|
|
// the illegal opcodes behave as NOPs
|
| 1021 |
|
|
|
| 1022 |
|
|
6'b001011, 6'b011001, 6'b011101, 6'b101101,
|
| 1023 |
|
|
6'b111101: begin
|
| 1024 |
|
|
|
| 1025 |
|
|
state <= `cpus_fetchi; // fetch next instruction
|
| 1026 |
|
|
pc <= pc + 2'b10; // Next instruction byte, cns 2
|
| 1027 |
|
|
|
| 1028 |
|
|
end
|
| 1029 |
|
|
|
| 1030 |
|
|
endcase
|
| 1031 |
|
|
|
| 1032 |
|
|
end
|
| 1033 |
|
|
|
| 1034 |
|
|
endcase
|
| 1035 |
|
|
|
| 1036 |
|
|
end
|
| 1037 |
|
|
|
| 1038 |
|
|
// Follow states. These state handlers implement the following cycles past
|
| 1039 |
|
|
// M1, or primary fetch state.
|
| 1040 |
|
|
|
| 1041 |
|
|
//
|
| 1042 |
|
|
// single byte write, writes wdatahold to the waddrhold address
|
| 1043 |
|
|
//
|
| 1044 |
|
|
|
| 1045 |
|
|
`cpus_write: begin
|
| 1046 |
|
|
|
| 1047 |
|
|
addr <= waddrhold; // place address on output
|
| 1048 |
|
|
waddrhold <= waddrhold + 1'b1; // next address
|
| 1049 |
|
|
datao <= wdatahold; // set data to output
|
| 1050 |
|
|
wdatahold <= wdatahold2; // next data
|
| 1051 |
|
|
dataeno <= 1; // enable output data
|
| 1052 |
|
|
state <= `cpus_write2; // next state
|
| 1053 |
|
|
|
| 1054 |
|
|
end
|
| 1055 |
|
|
|
| 1056 |
|
|
`cpus_write2: begin // continue write #2
|
| 1057 |
|
|
|
| 1058 |
|
|
writemem <= 1; // enable write memory data
|
| 1059 |
|
|
state <= `cpus_write3; // idle one cycle for write
|
| 1060 |
|
|
|
| 1061 |
|
|
end
|
| 1062 |
|
|
|
| 1063 |
|
|
`cpus_write3: begin // continue write #3
|
| 1064 |
|
|
|
| 1065 |
|
|
if (!waitr) begin // no wait selected, otherwise cycle
|
| 1066 |
|
|
|
| 1067 |
|
|
writemem <= 0; // disable write memory data
|
| 1068 |
|
|
state <= `cpus_write4; // idle hold time
|
| 1069 |
|
|
|
| 1070 |
|
|
end
|
| 1071 |
|
|
|
| 1072 |
|
|
end
|
| 1073 |
|
|
|
| 1074 |
|
|
`cpus_write4: begin // continue write #4
|
| 1075 |
|
|
|
| 1076 |
|
|
dataeno <= 0; // disable output data
|
| 1077 |
|
|
state <= nextstate; // get next macro state
|
| 1078 |
|
|
statesel <= statesel+1'b1; // and index next in macro
|
| 1079 |
|
|
|
| 1080 |
|
|
end
|
| 1081 |
|
|
|
| 1082 |
|
|
//
|
| 1083 |
|
|
// single byte read, reads rdatahold from the raddrhold address
|
| 1084 |
|
|
//
|
| 1085 |
|
|
|
| 1086 |
|
|
`cpus_read: begin
|
| 1087 |
|
|
|
| 1088 |
|
|
addr <= raddrhold; // place address on output
|
| 1089 |
|
|
raddrhold <= raddrhold + 1'b1; // next address
|
| 1090 |
|
|
if (intcyc) inta <= 1; // activate interrupt acknowledge
|
| 1091 |
|
|
else readmem <= 1; // activate memory read
|
| 1092 |
|
|
state <= `cpus_read2; // next state
|
| 1093 |
|
|
|
| 1094 |
|
|
end
|
| 1095 |
|
|
|
| 1096 |
|
|
`cpus_read2: begin // continue read #2
|
| 1097 |
|
|
|
| 1098 |
|
|
// wait one cycle
|
| 1099 |
|
|
state <= `cpus_read3; // next state
|
| 1100 |
|
|
|
| 1101 |
|
|
end
|
| 1102 |
|
|
|
| 1103 |
|
|
`cpus_read3: begin // continue read #3
|
| 1104 |
|
|
|
| 1105 |
|
|
if (!waitr) begin // no wait selected, otherwise cycle
|
| 1106 |
|
|
|
| 1107 |
|
|
rdatahold2 <= rdatahold; // shift data
|
| 1108 |
|
|
rdatahold <= data; // read new data
|
| 1109 |
|
|
readmem <= 0; // deactivate instruction memory read
|
| 1110 |
|
|
inta <= 0; // deactivate interrupt acknowledge
|
| 1111 |
|
|
state <= nextstate; // get next macro state
|
| 1112 |
|
|
statesel <= statesel+1'b1; // and index next in macro
|
| 1113 |
|
|
|
| 1114 |
|
|
end
|
| 1115 |
|
|
|
| 1116 |
|
|
end
|
| 1117 |
|
|
|
| 1118 |
|
|
`cpus_pop: begin // finish POP instruction
|
| 1119 |
|
|
|
| 1120 |
|
|
case (popdes) // register set
|
| 1121 |
|
|
|
| 1122 |
|
|
2'b00: { regfil[`reg_b], regfil[`reg_c] } <=
|
| 1123 |
|
|
{ rdatahold, rdatahold2 };
|
| 1124 |
|
|
2'b01: { regfil[`reg_d], regfil[`reg_e] } <=
|
| 1125 |
|
|
{ rdatahold, rdatahold2 };
|
| 1126 |
|
|
2'b10: { regfil[`reg_h], regfil[`reg_l] } <=
|
| 1127 |
|
|
{ rdatahold, rdatahold2 };
|
| 1128 |
|
|
2'b11: begin
|
| 1129 |
|
|
|
| 1130 |
|
|
regfil[`reg_a] <= rdatahold;
|
| 1131 |
|
|
sign <= ((rdatahold2 >> 7)& 1'b1) ? 1'b1:1'b0;
|
| 1132 |
|
|
zero <= ((rdatahold2 >> 6)& 1'b1) ? 1'b1:1'b0;
|
| 1133 |
|
|
auxcar <= ((rdatahold2 >> 4)& 1'b1) ? 1'b1:1'b0;
|
| 1134 |
|
|
parity <= ((rdatahold2 >> 2)& 1'b1) ? 1'b1:1'b0;
|
| 1135 |
|
|
carry <= ((rdatahold2 >> 1)& 1'b1) ? 1'b1:1'b0;
|
| 1136 |
|
|
|
| 1137 |
|
|
end
|
| 1138 |
|
|
|
| 1139 |
|
|
endcase
|
| 1140 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 1141 |
|
|
|
| 1142 |
|
|
end
|
| 1143 |
|
|
|
| 1144 |
|
|
`cpus_jmp: begin // jump address
|
| 1145 |
|
|
|
| 1146 |
|
|
state <= `cpus_fetchi; // and return to instruction fetch
|
| 1147 |
|
|
pc <= { rdatahold, rdatahold2 };
|
| 1148 |
|
|
|
| 1149 |
|
|
end
|
| 1150 |
|
|
|
| 1151 |
|
|
`cpus_in: begin // input single byte to A
|
| 1152 |
|
|
|
| 1153 |
|
|
addr <= rdatahold; // place I/O address on address lines
|
| 1154 |
|
|
readio <= 1; // set read I/O
|
| 1155 |
|
|
state <= `cpus_in2; // continue
|
| 1156 |
|
|
|
| 1157 |
|
|
end
|
| 1158 |
|
|
|
| 1159 |
|
|
`cpus_in2: begin // input single byte to A #2
|
| 1160 |
|
|
|
| 1161 |
|
|
// wait one cycle
|
| 1162 |
|
|
state <= `cpus_in3; // continue
|
| 1163 |
|
|
|
| 1164 |
|
|
end
|
| 1165 |
|
|
|
| 1166 |
|
|
`cpus_in3: begin // input single byte to A #3
|
| 1167 |
|
|
|
| 1168 |
|
|
if (!waitr) begin // no wait selected, otherwise cycle
|
| 1169 |
|
|
|
| 1170 |
|
|
regfil[`reg_a] <= data; // place input data
|
| 1171 |
|
|
readio <= 0; // clear read I/O
|
| 1172 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 1173 |
|
|
|
| 1174 |
|
|
end
|
| 1175 |
|
|
|
| 1176 |
|
|
end
|
| 1177 |
|
|
|
| 1178 |
|
|
`cpus_out: begin // output single byte from A
|
| 1179 |
|
|
|
| 1180 |
|
|
addr <= rdatahold; // place address on output
|
| 1181 |
|
|
datao <= regfil[`reg_a]; // set data to output
|
| 1182 |
|
|
dataeno <= 1; // enable output data
|
| 1183 |
|
|
state <= `cpus_out2; // next state
|
| 1184 |
|
|
|
| 1185 |
|
|
end
|
| 1186 |
|
|
|
| 1187 |
|
|
`cpus_out2: begin // continue out #2
|
| 1188 |
|
|
|
| 1189 |
|
|
writeio <= 1; // enable write I/O data
|
| 1190 |
|
|
state <= `cpus_out3; // idle one cycle for write
|
| 1191 |
|
|
|
| 1192 |
|
|
end
|
| 1193 |
|
|
|
| 1194 |
|
|
`cpus_out3: begin // continue out #3
|
| 1195 |
|
|
|
| 1196 |
|
|
if (!waitr) begin // no wait selected, otherwise cycle
|
| 1197 |
|
|
|
| 1198 |
|
|
writeio <= 0; // disable write I/O data
|
| 1199 |
|
|
state <= `cpus_out4; // idle hold time
|
| 1200 |
|
|
|
| 1201 |
|
|
end
|
| 1202 |
|
|
|
| 1203 |
|
|
end
|
| 1204 |
|
|
|
| 1205 |
|
|
`cpus_out4: begin // continue write #4
|
| 1206 |
|
|
|
| 1207 |
|
|
dataeno <= 0; // disable output data
|
| 1208 |
|
|
state <= `cpus_fetchi; // Fetch next instruction
|
| 1209 |
|
|
|
| 1210 |
|
|
end
|
| 1211 |
|
|
|
| 1212 |
|
|
`cpus_halt: begin // Halt waiting for interrupt
|
| 1213 |
|
|
|
| 1214 |
|
|
// If there is an interrupt request and interrupts are enabled, then we
|
| 1215 |
|
|
// can leave halt. Otherwise we stay here.
|
| 1216 |
|
|
if (intr&&ei) state <= `cpus_fetchi; // Fetch next instruction
|
| 1217 |
|
|
else state <= `cpus_halt;
|
| 1218 |
|
|
|
| 1219 |
|
|
|
| 1220 |
|
|
end
|
| 1221 |
|
|
|
| 1222 |
|
|
`cpus_movtr: begin // move to register
|
| 1223 |
|
|
|
| 1224 |
|
|
regfil[regd] <= rdatahold; // place data
|
| 1225 |
|
|
state <= nextstate; // get next macro state
|
| 1226 |
|
|
statesel <= statesel+1'b1; // and index next in macro
|
| 1227 |
|
|
|
| 1228 |
|
|
end
|
| 1229 |
|
|
|
| 1230 |
|
|
`cpus_alucb: begin // alu cycleback
|
| 1231 |
|
|
|
| 1232 |
|
|
regfil[`reg_a] <= alures; // place alu result back to A
|
| 1233 |
|
|
carry <= alucout; // place carry
|
| 1234 |
|
|
sign <= alusout; // place sign
|
| 1235 |
|
|
zero <= aluzout; // place zero
|
| 1236 |
|
|
parity <= alupar; // place parity
|
| 1237 |
|
|
auxcar <= aluaxc; // place auxiliary carry
|
| 1238 |
|
|
state <= `cpus_fetchi; // and return to instruction fetch
|
| 1239 |
|
|
|
| 1240 |
|
|
end
|
| 1241 |
|
|
|
| 1242 |
|
|
`cpus_indcb: begin // inr/dcr cycleback
|
| 1243 |
|
|
|
| 1244 |
|
|
regfil[regd] <= alures; // place alu result back to source/dest
|
| 1245 |
|
|
sign <= alures[7]; // place sign
|
| 1246 |
|
|
zero <= aluzout; // place zero
|
| 1247 |
|
|
parity <= alupar; // place parity
|
| 1248 |
|
|
auxcar <= aluaxc; // place auxiliary carry
|
| 1249 |
|
|
state <= `cpus_fetchi; // and return to instruction fetch
|
| 1250 |
|
|
|
| 1251 |
|
|
end
|
| 1252 |
|
|
|
| 1253 |
|
|
`cpus_movmtbc: begin // finish LXI B
|
| 1254 |
|
|
|
| 1255 |
|
|
regfil[`reg_b] <= rdatahold; // place upper
|
| 1256 |
|
|
regfil[`reg_c] <= rdatahold2; // place lower
|
| 1257 |
|
|
state <= `cpus_fetchi; // and return to instruction fetch
|
| 1258 |
|
|
|
| 1259 |
|
|
end
|
| 1260 |
|
|
|
| 1261 |
|
|
`cpus_movmtde: begin // finish LXI D
|
| 1262 |
|
|
|
| 1263 |
|
|
regfil[`reg_d] <= rdatahold; // place upper
|
| 1264 |
|
|
regfil[`reg_e] <= rdatahold2; // place lower
|
| 1265 |
|
|
state <= `cpus_fetchi; // and return to instruction fetch
|
| 1266 |
|
|
|
| 1267 |
|
|
end
|
| 1268 |
|
|
|
| 1269 |
|
|
`cpus_movmthl: begin // finish LXI H
|
| 1270 |
|
|
|
| 1271 |
|
|
regfil[`reg_h] <= rdatahold; // place upper
|
| 1272 |
|
|
regfil[`reg_l] <= rdatahold2; // place lower
|
| 1273 |
|
|
state <= `cpus_fetchi; // and return to instruction fetch
|
| 1274 |
|
|
|
| 1275 |
|
|
end
|
| 1276 |
|
|
|
| 1277 |
|
|
`cpus_movmtsp: begin // finish LXI SP
|
| 1278 |
|
|
|
| 1279 |
|
|
sp <= { rdatahold, rdatahold2 }; // place
|
| 1280 |
|
|
state <= `cpus_fetchi; // and return to instruction fetch
|
| 1281 |
|
|
|
| 1282 |
|
|
end
|
| 1283 |
|
|
|
| 1284 |
|
|
`cpus_movrtw: begin // move read to write
|
| 1285 |
|
|
|
| 1286 |
|
|
wdatahold <= rdatahold; // move read to write data
|
| 1287 |
|
|
state <= nextstate; // get next macro state
|
| 1288 |
|
|
statesel <= statesel+1'b1; // and index next in macro cns
|
| 1289 |
|
|
|
| 1290 |
|
|
end
|
| 1291 |
|
|
|
| 1292 |
|
|
`cpus_movrtwa: begin // move read data to write address
|
| 1293 |
|
|
|
| 1294 |
|
|
waddrhold <= { rdatahold, rdatahold2 };
|
| 1295 |
|
|
state <= nextstate; // get next macro state
|
| 1296 |
|
|
statesel <= statesel+1'b1; // and index next in macro cns
|
| 1297 |
|
|
|
| 1298 |
|
|
end
|
| 1299 |
|
|
|
| 1300 |
|
|
`cpus_movrtra: begin // move read data to read address
|
| 1301 |
|
|
|
| 1302 |
|
|
raddrhold <= { rdatahold, rdatahold2 };
|
| 1303 |
|
|
state <= nextstate; // get next macro state
|
| 1304 |
|
|
statesel <= statesel+1'b1; // and index next in macro cns
|
| 1305 |
|
|
|
| 1306 |
|
|
end
|
| 1307 |
|
|
|
| 1308 |
|
|
`cpus_lhld: begin // load HL from read data
|
| 1309 |
|
|
|
| 1310 |
|
|
regfil[`reg_l] <= rdatahold2; // low
|
| 1311 |
|
|
regfil[`reg_h] <= rdatahold; // high
|
| 1312 |
|
|
state <= nextstate; // get next macro state
|
| 1313 |
|
|
statesel <= statesel+1'b1; // and index next in macro CNS
|
| 1314 |
|
|
|
| 1315 |
|
|
end
|
| 1316 |
|
|
|
| 1317 |
|
|
`cpus_accimm: begin
|
| 1318 |
|
|
|
| 1319 |
|
|
aluoprb <= rdatahold; // load as alu b
|
| 1320 |
|
|
state <= `cpus_alucb; // go to alu cycleback
|
| 1321 |
|
|
|
| 1322 |
|
|
end
|
| 1323 |
|
|
|
| 1324 |
|
|
`cpus_daa: begin
|
| 1325 |
|
|
|
| 1326 |
|
|
if (regfil[`reg_a][7:4] > 9 || carry) begin
|
| 1327 |
|
|
|
| 1328 |
|
|
{ carry, regfil[`reg_a] } <= regfil[`reg_a]+8'h60;
|
| 1329 |
|
|
|
| 1330 |
|
|
end
|
| 1331 |
|
|
state <= `cpus_fetchi; // and return to instruction fetch
|
| 1332 |
|
|
|
| 1333 |
|
|
end
|
| 1334 |
|
|
|
| 1335 |
|
|
default: state <= 5'bx;
|
| 1336 |
|
|
|
| 1337 |
|
|
endcase
|
| 1338 |
|
|
|
| 1339 |
|
|
// Enable drive for data output
|
| 1340 |
|
|
assign data = dataeno ? datao: 8'bz;
|
| 1341 |
|
|
|
| 1342 |
|
|
//
|
| 1343 |
|
|
// State macro generator
|
| 1344 |
|
|
//
|
| 1345 |
|
|
// This ROM contains series of state execution lists that perform various
|
| 1346 |
|
|
// tasks, usually involving reads or writes.
|
| 1347 |
|
|
//
|
| 1348 |
|
|
|
| 1349 |
|
|
always @(statesel) case (statesel)
|
| 1350 |
|
|
|
| 1351 |
|
|
// mac_writebyte: write a byte
|
| 1352 |
|
|
|
| 1353 |
|
|
1: nextstate = `cpus_fetchi; // fetch next instruction
|
| 1354 |
|
|
|
| 1355 |
|
|
// mac_readbtoreg: read a byte, place in register
|
| 1356 |
|
|
|
| 1357 |
|
|
2: nextstate = `cpus_movtr; // move to register
|
| 1358 |
|
|
3: nextstate = `cpus_fetchi; // Fetch next instruction
|
| 1359 |
|
|
|
| 1360 |
|
|
// mac_readdtobc: read double byte to BC
|
| 1361 |
|
|
|
| 1362 |
|
|
4: nextstate = `cpus_read; // get high byte
|
| 1363 |
|
|
5: nextstate = `cpus_movmtbc; // place in BC
|
| 1364 |
|
|
|
| 1365 |
|
|
// mac_readdtode: read double byte to DE
|
| 1366 |
|
|
|
| 1367 |
|
|
6: nextstate = `cpus_read; // get high byte
|
| 1368 |
|
|
7: nextstate = `cpus_movmtde; // place in DE
|
| 1369 |
|
|
|
| 1370 |
|
|
// mac_readdtohl: read double byte to HL
|
| 1371 |
|
|
|
| 1372 |
|
|
8: nextstate = `cpus_read; // get high byte
|
| 1373 |
|
|
9: nextstate = `cpus_movmthl; // place in HL
|
| 1374 |
|
|
|
| 1375 |
|
|
// mac_readdtosp: read double byte to SP
|
| 1376 |
|
|
|
| 1377 |
|
|
10: nextstate = `cpus_read; // get high byte
|
| 1378 |
|
|
11: nextstate = `cpus_movmtsp; // place in SP
|
| 1379 |
|
|
|
| 1380 |
|
|
// mac_readbmtw: read byte and move to write
|
| 1381 |
|
|
|
| 1382 |
|
|
12: nextstate = `cpus_movrtw; // move read to write
|
| 1383 |
|
|
13: nextstate = `cpus_fetchi; // Fetch next instruction
|
| 1384 |
|
|
|
| 1385 |
|
|
// mac_readbmtr: read byte and move to register
|
| 1386 |
|
|
|
| 1387 |
|
|
14: nextstate = `cpus_movtr; // place in register
|
| 1388 |
|
|
15: nextstate = `cpus_fetchi; // Fetch next instruction
|
| 1389 |
|
|
|
| 1390 |
|
|
// mac_sta: STA
|
| 1391 |
|
|
|
| 1392 |
|
|
16: nextstate = `cpus_read; // read high byte
|
| 1393 |
|
|
17: nextstate = `cpus_movrtwa; // move read to write address
|
| 1394 |
|
|
18: nextstate = `cpus_write; // write to destination
|
| 1395 |
|
|
19: nextstate = `cpus_fetchi; // Fetch next instruction
|
| 1396 |
|
|
|
| 1397 |
|
|
// mac_lda: LDA
|
| 1398 |
|
|
|
| 1399 |
|
|
20: nextstate = `cpus_read; // read high byte
|
| 1400 |
|
|
21: nextstate = `cpus_movrtra; // move read to write address
|
| 1401 |
|
|
22: nextstate = `cpus_read; // read byte
|
| 1402 |
|
|
23: nextstate = `cpus_movtr; // move to register
|
| 1403 |
|
|
24: nextstate = `cpus_fetchi; // Fetch next instruction
|
| 1404 |
|
|
|
| 1405 |
|
|
// mac_shld: SHLD
|
| 1406 |
|
|
|
| 1407 |
|
|
25: nextstate = `cpus_read; // read high byte
|
| 1408 |
|
|
26: nextstate = `cpus_movrtwa; // move read to write address
|
| 1409 |
|
|
27: nextstate = `cpus_write; // write to destination low
|
| 1410 |
|
|
28: nextstate = `cpus_write; // write to destination high
|
| 1411 |
|
|
29: nextstate = `cpus_fetchi; // Fetch next instruction
|
| 1412 |
|
|
|
| 1413 |
|
|
// mac_lhld: LHLD
|
| 1414 |
|
|
|
| 1415 |
|
|
30: nextstate = `cpus_read; // read high byte
|
| 1416 |
|
|
31: nextstate = `cpus_movrtra; // move read to write address
|
| 1417 |
|
|
32: nextstate = `cpus_read; // read byte low
|
| 1418 |
|
|
33: nextstate = `cpus_read; // read byte high
|
| 1419 |
|
|
34: nextstate = `cpus_lhld; // move to register
|
| 1420 |
|
|
35: nextstate = `cpus_fetchi; // Fetch next instruction
|
| 1421 |
|
|
|
| 1422 |
|
|
// mac_writedbyte: write double byte
|
| 1423 |
|
|
|
| 1424 |
|
|
36: nextstate = `cpus_write; // double write
|
| 1425 |
|
|
37: nextstate = `cpus_fetchi; // then fetch
|
| 1426 |
|
|
|
| 1427 |
|
|
// mac_pop: POP
|
| 1428 |
|
|
|
| 1429 |
|
|
38: nextstate = `cpus_read; // double it
|
| 1430 |
|
|
39: nextstate = `cpus_pop; // then finish
|
| 1431 |
|
|
|
| 1432 |
|
|
// mac_xthl: XTHL
|
| 1433 |
|
|
|
| 1434 |
|
|
40: nextstate = `cpus_read; // double it
|
| 1435 |
|
|
41: nextstate = `cpus_write; // then write
|
| 1436 |
|
|
42: nextstate = `cpus_write; // double it
|
| 1437 |
|
|
43: nextstate = `cpus_movmthl; // place word in hl
|
| 1438 |
|
|
|
| 1439 |
|
|
// mac_accimm: accumulator immediate
|
| 1440 |
|
|
|
| 1441 |
|
|
44: nextstate = `cpus_accimm; // finish
|
| 1442 |
|
|
|
| 1443 |
|
|
// mac_jmp: JMP
|
| 1444 |
|
|
|
| 1445 |
|
|
45: nextstate = `cpus_read; // double read
|
| 1446 |
|
|
46: nextstate = `cpus_jmp; // then go pc
|
| 1447 |
|
|
|
| 1448 |
|
|
// mac_call: CALL
|
| 1449 |
|
|
|
| 1450 |
|
|
47: nextstate = `cpus_read; // double read
|
| 1451 |
|
|
48: nextstate = `cpus_write; // then write
|
| 1452 |
|
|
49: nextstate = `cpus_write; // double write
|
| 1453 |
|
|
50: nextstate = `cpus_jmp; // then go to that
|
| 1454 |
|
|
|
| 1455 |
|
|
// mac_in: IN
|
| 1456 |
|
|
|
| 1457 |
|
|
51: nextstate = `cpus_in; // go to IN after getting that
|
| 1458 |
|
|
|
| 1459 |
|
|
// mac_out: OUT
|
| 1460 |
|
|
|
| 1461 |
|
|
52: nextstate = `cpus_out; // go to OUT after getting that
|
| 1462 |
|
|
|
| 1463 |
|
|
// mac_rst: RST
|
| 1464 |
|
|
|
| 1465 |
|
|
53: nextstate = `cpus_write; // double write
|
| 1466 |
|
|
54: nextstate = `cpus_jmp; // then go to that
|
| 1467 |
|
|
|
| 1468 |
|
|
default nextstate = 6'bx; // other states never reached
|
| 1469 |
|
|
|
| 1470 |
|
|
endcase
|
| 1471 |
|
|
|
| 1472 |
|
|
endmodule
|
| 1473 |
|
|
|
| 1474 |
|
|
//
|
| 1475 |
|
|
// Alu module
|
| 1476 |
|
|
//
|
| 1477 |
|
|
// Finds arithmetic operations needed. Latches on the positive edge of the
|
| 1478 |
|
|
// clock. There are 8 different types of operations, which come from bits
|
| 1479 |
|
|
// 3-5 of the instruction.
|
| 1480 |
|
|
//
|
| 1481 |
|
|
|
| 1482 |
|
|
module alu(res, opra, oprb, cin, cout, zout, sout, parity, auxcar, sel);
|
| 1483 |
|
|
|
| 1484 |
|
|
input [7:0] opra; // Input A
|
| 1485 |
|
|
input [7:0] oprb; // Input B
|
| 1486 |
|
|
input cin; // Carry in
|
| 1487 |
|
|
output cout; // Carry out
|
| 1488 |
|
|
output zout; // Zero out
|
| 1489 |
|
|
output sout; // Sign out
|
| 1490 |
|
|
output parity; // parity
|
| 1491 |
|
|
output auxcar; // auxiliary carry
|
| 1492 |
|
|
input [2:0] sel; // Operation select
|
| 1493 |
|
|
output [7:0] res; // Result of alu operation
|
| 1494 |
|
|
|
| 1495 |
|
|
reg cout; // Carry out
|
| 1496 |
|
|
reg zout; // Zero out
|
| 1497 |
|
|
reg sout; // sign out
|
| 1498 |
|
|
reg parity; // parity
|
| 1499 |
|
|
reg auxcar; // auxiliary carry
|
| 1500 |
|
|
reg [7:0] resi; // Result of alu operation intermediate
|
| 1501 |
|
|
reg [7:0] res; // Result of alu operation
|
| 1502 |
|
|
|
| 1503 |
|
|
always @(opra, oprb, cin, sel, res, resi) begin
|
| 1504 |
|
|
|
| 1505 |
|
|
case (sel)
|
| 1506 |
|
|
|
| 1507 |
|
|
`aluop_add: begin // add
|
| 1508 |
|
|
|
| 1509 |
|
|
{ cout, resi } = opra+oprb; // find result and carry
|
| 1510 |
|
|
// auxcar = ((opra[3:0]+oprb[3:0]) >> 4) & 1'b1; // find auxiliary carry
|
| 1511 |
|
|
// if ((opra[3:0]+oprb[3:0])>>4) auxcar=1'b1; else auxcar=1'b0;
|
| 1512 |
|
|
auxcar = (((opra[3:0]+oprb[3:0]) >> 4) & 1'b1) ? 1'b1 : 1'b0 ; // find auxiliary carry
|
| 1513 |
|
|
|
| 1514 |
|
|
|
| 1515 |
|
|
end
|
| 1516 |
|
|
`aluop_adc: begin // adc
|
| 1517 |
|
|
|
| 1518 |
|
|
{ cout, resi } = opra+oprb+cin; // find result and carry
|
| 1519 |
|
|
auxcar = (((opra[3:0]+oprb[3:0]+cin) >> 4) & 1'b1) ? 1'b1 : 1'b0; // find auxiliary carry
|
| 1520 |
|
|
|
| 1521 |
|
|
end
|
| 1522 |
|
|
`aluop_sub, `aluop_cmp: begin // sub/cmp
|
| 1523 |
|
|
|
| 1524 |
|
|
{ cout, resi } = opra-oprb; // find result and carry
|
| 1525 |
|
|
auxcar = (((opra[3:0]-oprb[3:0]) >> 4) & 1'b1) ? 1'b1 : 1'b0; // find auxiliary borrow
|
| 1526 |
|
|
|
| 1527 |
|
|
end
|
| 1528 |
|
|
`aluop_sbb: begin // sbb
|
| 1529 |
|
|
|
| 1530 |
|
|
{ cout, resi } = opra-oprb-cin; // find result and carry
|
| 1531 |
|
|
auxcar = (((opra[3:0]-oprb[3:0]-cin >> 4)) & 1'b1) ? 1'b1 : 1'b0; // find auxiliary borrow
|
| 1532 |
|
|
|
| 1533 |
|
|
end
|
| 1534 |
|
|
`aluop_and: begin // ana
|
| 1535 |
|
|
|
| 1536 |
|
|
{ cout, resi } = {1'b0, opra&oprb}; // find result and carry
|
| 1537 |
|
|
auxcar = 1'b0; // clear auxillary carry
|
| 1538 |
|
|
|
| 1539 |
|
|
end
|
| 1540 |
|
|
`aluop_xor: begin // xra
|
| 1541 |
|
|
|
| 1542 |
|
|
{ cout, resi } = {1'b0, opra^oprb}; // find result and carry
|
| 1543 |
|
|
auxcar = 1'b0; // clear auxillary carry
|
| 1544 |
|
|
|
| 1545 |
|
|
end
|
| 1546 |
|
|
`aluop_or: begin // ora
|
| 1547 |
|
|
|
| 1548 |
|
|
{ cout, resi } = {1'b0, opra|oprb}; // find result and carry
|
| 1549 |
|
|
auxcar = 1'b0; // clear auxillary carry
|
| 1550 |
|
|
|
| 1551 |
|
|
end
|
| 1552 |
|
|
|
| 1553 |
|
|
endcase
|
| 1554 |
|
|
|
| 1555 |
|
|
if (sel != `aluop_cmp) res = resi; else res = opra;
|
| 1556 |
|
|
zout <= ~|resi; // set zero flag from result
|
| 1557 |
|
|
sout <= resi[7]; // set sign flag from result
|
| 1558 |
|
|
parity <= ~^resi; // set parity flag from result
|
| 1559 |
|
|
|
| 1560 |
|
|
end
|
| 1561 |
|
|
|
| 1562 |
|
|
endmodule
|
