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samiam9512 |
Release 8.2.02i - Bitgen I.33
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Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
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Loading device for application Rf_Device from file '3s1000.nph' in environment
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C:\Xilinx.
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"testbench" is an NCD, version 3.1, device xc3s1000, package ft256, speed -4
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Opened constraints file testbench.pcf.
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samiam9512 |
Sat Nov 18 17:16:32 2006
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samiam9512 |
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C:\Xilinx\bin\nt\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:6 -g CclkPin:PullNone -g M0Pin:PullNone -g M1Pin:PullNone -g M2Pin:PullNone -g ProgPin:PullNone -g DonePin:PullNone -g TckPin:PullNone -g TdiPin:PullNone -g TdoPin:PullNone -g TmsPin:PullNone -g UnusedPin:PullNone -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g DCIUpdateMode:AsRequired -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Match_cycle:Auto -g Security:None -g DonePipe:No -g DriveDone:No testbench.ncd
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Summary of Bitgen Options:
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+----------------------+----------------------+
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| Option Name | Current Setting |
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+----------------------+----------------------+
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| Compress | (Not Specified)* |
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+----------------------+----------------------+
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| Readback | (Not Specified)* |
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+----------------------+----------------------+
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| CRC | Enable** |
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+----------------------+----------------------+
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| DebugBitstream | No** |
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+----------------------+----------------------+
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| ConfigRate | 6** |
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+----------------------+----------------------+
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| StartupClk | Cclk** |
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+----------------------+----------------------+
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| DCMShutdown | Disable** |
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+----------------------+----------------------+
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| DCIUpdateMode | AsRequired** |
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+----------------------+----------------------+
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| CclkPin | Pullnone |
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+----------------------+----------------------+
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| DonePin | Pullnone |
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+----------------------+----------------------+
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| HswapenPin | Pullup* |
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+----------------------+----------------------+
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| M0Pin | Pullnone |
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+----------------------+----------------------+
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| M1Pin | Pullnone |
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+----------------------+----------------------+
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| M2Pin | Pullnone |
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+----------------------+----------------------+
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| ProgPin | Pullnone |
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+----------------------+----------------------+
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| TckPin | Pullnone |
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+----------------------+----------------------+
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| TdiPin | Pullnone |
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+----------------------+----------------------+
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| TdoPin | Pullnone |
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+----------------------+----------------------+
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| TmsPin | Pullnone |
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+----------------------+----------------------+
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| UnusedPin | Pullnone |
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+----------------------+----------------------+
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| GWE_cycle | 6** |
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+----------------------+----------------------+
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| GTS_cycle | 5** |
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+----------------------+----------------------+
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| LCK_cycle | NoWait** |
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+----------------------+----------------------+
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| Match_cycle | Auto** |
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+----------------------+----------------------+
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| DONE_cycle | 4** |
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+----------------------+----------------------+
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| Persist | No* |
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+----------------------+----------------------+
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| DriveDone | No** |
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+----------------------+----------------------+
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| DonePipe | No** |
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+----------------------+----------------------+
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| Security | None** |
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+----------------------+----------------------+
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| UserID | 0xFFFFFFFF** |
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+----------------------+----------------------+
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| ActivateGclk | No* |
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+----------------------+----------------------+
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| ActiveReconfig | No* |
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+----------------------+----------------------+
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| PartialMask0 | (Not Specified)* |
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+----------------------+----------------------+
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| PartialMask1 | (Not Specified)* |
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+----------------------+----------------------+
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| PartialMask2 | (Not Specified)* |
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+----------------------+----------------------+
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| PartialGclk | (Not Specified)* |
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+----------------------+----------------------+
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| PartialLeft | (Not Specified)* |
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+----------------------+----------------------+
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| PartialRight | (Not Specified)* |
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+----------------------+----------------------+
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| IEEE1532 | No* |
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+----------------------+----------------------+
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| Binary | No** |
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+----------------------+----------------------+
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* Default setting.
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** The specified setting matches the default setting.
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Running DRC.
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20 |
samiam9512 |
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is
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11 |
samiam9512 |
sourced by a combinatorial pin. This is not good design practice. Use the CE
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pin to control the loading of data into the flip-flop.
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is
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sourced by a combinatorial pin. This is not good design practice. Use the CE
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pin to control the loading of data into the flip-flop.
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samiam9512 |
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is
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11 |
samiam9512 |
sourced by a combinatorial pin. This is not good design practice. Use the CE
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pin to control the loading of data into the flip-flop.
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20 |
samiam9512 |
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is
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11 |
samiam9512 |
sourced by a combinatorial pin. This is not good design practice. Use the CE
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pin to control the loading of data into the flip-flop.
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20 |
samiam9512 |
WARNING:PhysDesignRules:812 - Dangling pin on
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block::
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6A>.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block::
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6A>.
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WARNING:PhysDesignRules:812 - Dangling pin on
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block::
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6A>.
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DRC detected 0 errors and 7 warnings.
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samiam9512 |
Creating bit map...
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Saving bit stream in "testbench.bit".
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Bitstream generation is complete.
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