OpenCores
URL https://opencores.org/ocsvn/cpu8080/cpu8080/trunk

Subversion Repositories cpu8080

[/] [cpu8080/] [trunk/] [project/] [testbench.drc] - Blame information for rev 33

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 20 samiam9512
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is
2 11 samiam9512
   sourced by a combinatorial pin. This is not good design practice. Use the CE
3
   pin to control the loading of data into the flip-flop.
4
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is
5
   sourced by a combinatorial pin. This is not good design practice. Use the CE
6
   pin to control the loading of data into the flip-flop.
7 20 samiam9512
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is
8 11 samiam9512
   sourced by a combinatorial pin. This is not good design practice. Use the CE
9
   pin to control the loading of data into the flip-flop.
10 20 samiam9512
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is
11 11 samiam9512
   sourced by a combinatorial pin. This is not good design practice. Use the CE
12
   pin to control the loading of data into the flip-flop.
13 20 samiam9512
WARNING:PhysDesignRules:812 - Dangling pin  on
14
   block::
15
   6A>.
16
WARNING:PhysDesignRules:812 - Dangling pin  on
17
   block::
18
   6A>.
19
WARNING:PhysDesignRules:812 - Dangling pin  on
20
   block::
21
   6A>.
22
DRC detected 0 errors and 7 warnings.

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.