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[/] [cpu8080/] [trunk/] [project/] [testbench.drc] - Blame information for rev 18
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| Line No. |
Rev |
Author |
Line |
| 1 |
18 |
samiam9512 |
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectb/_and0000 is
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| 2 |
11 |
samiam9512 |
sourced by a combinatorial pin. This is not good design practice. Use the CE
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| 3 |
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pin to control the loading of data into the flip-flop.
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| 4 |
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WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selecta/_and0000 is
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| 5 |
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sourced by a combinatorial pin. This is not good design practice. Use the CE
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| 6 |
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pin to control the loading of data into the flip-flop.
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| 7 |
18 |
samiam9512 |
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectc/_and0000 is
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| 8 |
11 |
samiam9512 |
sourced by a combinatorial pin. This is not good design practice. Use the CE
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| 9 |
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pin to control the loading of data into the flip-flop.
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| 10 |
18 |
samiam9512 |
WARNING:PhysDesignRules:372 - Gated clock. Clock net select1/selectd/_and0000 is
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| 11 |
11 |
samiam9512 |
sourced by a combinatorial pin. This is not good design practice. Use the CE
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| 12 |
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pin to control the loading of data into the flip-flop.
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| 13 |
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DRC detected 0 errors and 4 warnings.
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