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[/] [cpu8080/] [trunk/] [project/] [testbench.par] - Blame information for rev 11

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Release 8.2.02i par I.33
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
 
SCOTT-H-PC::  Wed Nov 01 08:45:45 2006
 
par -w -intstyle ise -ol std -t 1 testbench_map.ncd testbench.ncd testbench.pcf
 
 
Constraints file: testbench.pcf.
Loading device for application Rf_Device from file '3s1000.nph' in environment C:\Xilinx.
   "testbench" is an NCD, version 3.1, device xc3s1000, package ft256, speed -4
 
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
 
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a
   balance between the fastest runtime and best performance, set the effort level to "med".
 
Device speed data version:  "PRODUCTION 1.39 2006-07-07".
 
 
Device Utilization Summary:
 
   Number of BUFGMUXs                  3 out of 8      37%
   Number of External IOBs            44 out of 173    25%
      Number of LOCed IOBs            44 out of 44    100%
 
   Number of MULT18X18s                1 out of 24      4%
   Number of RAMB16s                   2 out of 24      8%
   Number of Slices                 3425 out of 7680   44%
      Number of SLICEMs              950 out of 3840   24%
 
 
 
Overall effort level (-ol):   Standard
Placer effort level (-pl):    High
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard
 
 
Starting Placer
 
Phase 1.1
Phase 1.1 (Checksum:996b76) REAL time: 9 secs
 
Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 10 secs
 
Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 10 secs
 
Phase 4.2
......
..................
 
 
Phase 4.2 (Checksum:98bdbb) REAL time: 22 secs
 
Phase 5.8
......................................................................................................................................................................................................................................
..............
.......................................................................................................................
.................
....................
.........................................................
Phase 5.8 (Checksum:ad58a9) REAL time: 3 mins 6 secs
 
Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 3 mins 6 secs
 
Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 4 mins 29 secs
 
Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 4 mins 29 secs
 
Writing design to file testbench.ncd
 
 
Total REAL time to Placer completion: 4 mins 34 secs
Total CPU time to Placer completion: 3 mins 57 secs
 
Starting Router
 
Phase 1: 26573 unrouted;       REAL time: 4 mins 34 secs
 
Phase 2: 24811 unrouted;       REAL time: 4 mins 40 secs
 
Phase 3: 7304 unrouted;       REAL time: 4 mins 47 secs
 
Phase 4: 7304 unrouted; (26511)      REAL time: 4 mins 48 secs
 
Phase 5: 7292 unrouted; (0)      REAL time: 4 mins 53 secs
 
Phase 6: 0 unrouted; (0)      REAL time: 5 mins 11 secs
 
Phase 7: 0 unrouted; (0)      REAL time: 5 mins 15 secs
 
WARNING:Route:447 - CLK Net:reset_n_BUFGP may have excessive skew because
   332 NON-CLK pins failed to route using a CLK template.
WARNING:Route:447 - CLK Net:clkdiv<3> may have excessive skew because
   1 NON-CLK pins failed to route using a CLK template.
 
Total REAL time to Router completion: 5 mins 15 secs
Total CPU time to Router completion: 4 mins 34 secs
 
Partition Implementation Status
-------------------------------
 
  No Partitions were found in this design.
 
-------------------------------
 
Generating "PAR" statistics.
 
**************************
Generating Clock Report
**************************
 
+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|       reset_n_BUFGP |      BUFGMUX5| No   |  348 |  0.159     |  1.033      |
+---------------------+--------------+------+------+------------+-------------+
|           clkdiv<3> |      BUFGMUX2| No   |  287 |  0.436     |  1.140      |
+---------------------+--------------+------+------+------------+-------------+
|         clock_BUFGP |      BUFGMUX0| No   | 1266 |  0.519     |  1.221      |
+---------------------+--------------+------+------+------------+-------------+
|select1/selectd/_and |              |      |      |            |             |
|                0000 |         Local|      |    7 |  0.011     |  2.195      |
+---------------------+--------------+------+------+------------+-------------+
|select1/selecta/_and |              |      |      |            |             |
|                0000 |         Local|      |    7 |  0.143     |  3.148      |
+---------------------+--------------+------+------+------------+-------------+
|select1/selectb/_and |              |      |      |            |             |
|                0000 |         Local|      |    7 |  0.066     |  2.239      |
+---------------------+--------------+------+------+------------+-------------+
|select1/selectc/_and |              |      |      |            |             |
|                0000 |         Local|      |    7 |  0.120     |  2.850      |
+---------------------+--------------+------+------+------------+-------------+
 
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
 
 
   The Delay Summary Report
 
 
The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0
 
   The AVERAGE CONNECTION DELAY for this design is:        2.120
   The MAXIMUM PIN DELAY IS:                              12.443
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   9.291
 
   Listing Pin Delays by value: (nsec)
 
    d < 2.00   < d < 4.00  < d < 6.00  < d < 8.00  < d < 13.00  d >= 13.00
   ---------   ---------   ---------   ---------   ---------   ---------
       15385        8001        2840         587          73           0
 
Timing Score: 0
 
Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.
 
------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of
                                            |            |            | Levels | Slack      |errors
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | N/A        | 23.680ns   | 3      | N/A        | N/A
  div<3>                                    |            |            |        |            |
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clo | N/A        | 33.066ns   | 12     | N/A        | N/A
  ck_BUFGP                                  |            |            |        |            |
------------------------------------------------------------------------------------------------------
 
 
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
 
 
Generating Pad Report.
 
All signals are completely routed.
 
Total REAL time to PAR completion: 5 mins 25 secs
Total CPU time to PAR completion: 4 mins 42 secs
 
Peak Memory Usage:  263 MB
 
Placement: Completed - No errors found.
Routing: Completed - No errors found.
 
Number of error messages: 0
Number of warning messages: 2
Number of info messages: 1
 
Writing design to file testbench.ncd
 
 
 
PAR done!

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Subversion Repositories cpu8080

[/] [cpu8080/] [trunk/] [project/] [testbench.par] - Blame information for rev 11

Line No.	Rev	Author	Line
1	11	samiam9512	`Release 8.2.02i par I.33`
2			`Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.`
3
4			`SCOTT-H-PC:: Wed Nov 01 08:45:45 2006`
5
6			`par -w -intstyle ise -ol std -t 1 testbench_map.ncd testbench.ncd testbench.pcf`
7
8
9			`Constraints file: testbench.pcf.`
10			`Loading device for application Rf_Device from file '3s1000.nph' in environment C:\Xilinx.`
11			`"testbench" is an NCD, version 3.1, device xc3s1000, package ft256, speed -4`
12
13			`Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)`
14			`Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)`
15
16			`INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par`
17			`-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all`
18			`internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For`
19			`the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a`
20			`balance between the fastest runtime and best performance, set the effort level to "med".`
21
22			`Device speed data version: "PRODUCTION 1.39 2006-07-07".`
23
24
25			`Device Utilization Summary:`
26
27			`Number of BUFGMUXs 3 out of 8 37%`
28			`Number of External IOBs 44 out of 173 25%`
29			`Number of LOCed IOBs 44 out of 44 100%`
30
31			`Number of MULT18X18s 1 out of 24 4%`
32			`Number of RAMB16s 2 out of 24 8%`
33			`Number of Slices 3425 out of 7680 44%`
34			`Number of SLICEMs 950 out of 3840 24%`
35
36
37
38			`Overall effort level (-ol): Standard`
39			`Placer effort level (-pl): High`
40			`Placer cost table entry (-t): 1`
41			`Router effort level (-rl): Standard`
42
43
44			`Starting Placer`
45
46			`Phase 1.1`
47			`Phase 1.1 (Checksum:996b76) REAL time: 9 secs`
48
49			`Phase 2.7`
50			`Phase 2.7 (Checksum:1312cfe) REAL time: 10 secs`
51
52			`Phase 3.31`
53			`Phase 3.31 (Checksum:1c9c37d) REAL time: 10 secs`
54
55			`Phase 4.2`
56			`......`
57			`..................`
58
59
60			`Phase 4.2 (Checksum:98bdbb) REAL time: 22 secs`
61
62			`Phase 5.8`
63			`......................................................................................................................................................................................................................................`
64			`..............`
65			`.......................................................................................................................`
66			`.................`
67			`....................`
68			`.........................................................`
69			`Phase 5.8 (Checksum:ad58a9) REAL time: 3 mins 6 secs`
70
71			`Phase 6.5`
72			`Phase 6.5 (Checksum:39386fa) REAL time: 3 mins 6 secs`
73
74			`Phase 7.18`
75			`Phase 7.18 (Checksum:42c1d79) REAL time: 4 mins 29 secs`
76
77			`Phase 8.5`
78			`Phase 8.5 (Checksum:4c4b3f8) REAL time: 4 mins 29 secs`
79
80			`Writing design to file testbench.ncd`
81
82
83			`Total REAL time to Placer completion: 4 mins 34 secs`
84			`Total CPU time to Placer completion: 3 mins 57 secs`
85
86			`Starting Router`
87
88			`Phase 1: 26573 unrouted; REAL time: 4 mins 34 secs`
89
90			`Phase 2: 24811 unrouted; REAL time: 4 mins 40 secs`
91
92			`Phase 3: 7304 unrouted; REAL time: 4 mins 47 secs`
93
94			`Phase 4: 7304 unrouted; (26511) REAL time: 4 mins 48 secs`
95
96			`Phase 5: 7292 unrouted; (0) REAL time: 4 mins 53 secs`
97
98			`Phase 6: 0 unrouted; (0) REAL time: 5 mins 11 secs`
99
100			`Phase 7: 0 unrouted; (0) REAL time: 5 mins 15 secs`
101
102			`WARNING:Route:447 - CLK Net:reset_n_BUFGP may have excessive skew because`
103			`332 NON-CLK pins failed to route using a CLK template.`
104			`WARNING:Route:447 - CLK Net:clkdiv<3> may have excessive skew because`
105			`1 NON-CLK pins failed to route using a CLK template.`
106
107			`Total REAL time to Router completion: 5 mins 15 secs`
108			`Total CPU time to Router completion: 4 mins 34 secs`
109
110			`Partition Implementation Status`
111			`-------------------------------`
112
113			`No Partitions were found in this design.`
114
115			`-------------------------------`
116
117			`Generating "PAR" statistics.`
118
119			`**************************`
120			`Generating Clock Report`
121			`**************************`
122
123			`+---------------------+--------------+------+------+------------+-------------+`
124			`\| Clock Net \| Resource \|Locked\|Fanout\|Net Skew(ns)\|Max Delay(ns)\|`
125			`+---------------------+--------------+------+------+------------+-------------+`
126			`\| reset_n_BUFGP \| BUFGMUX5\| No \| 348 \| 0.159 \| 1.033 \|`
127			`+---------------------+--------------+------+------+------------+-------------+`
128			`\| clkdiv<3> \| BUFGMUX2\| No \| 287 \| 0.436 \| 1.140 \|`
129			`+---------------------+--------------+------+------+------------+-------------+`
130			`\| clock_BUFGP \| BUFGMUX0\| No \| 1266 \| 0.519 \| 1.221 \|`
131			`+---------------------+--------------+------+------+------------+-------------+`
132			`\|select1/selectd/_and \| \| \| \| \| \|`
133			`\| 0000 \| Local\| \| 7 \| 0.011 \| 2.195 \|`
134			`+---------------------+--------------+------+------+------------+-------------+`
135			`\|select1/selecta/_and \| \| \| \| \| \|`
136			`\| 0000 \| Local\| \| 7 \| 0.143 \| 3.148 \|`
137			`+---------------------+--------------+------+------+------------+-------------+`
138			`\|select1/selectb/_and \| \| \| \| \| \|`
139			`\| 0000 \| Local\| \| 7 \| 0.066 \| 2.239 \|`
140			`+---------------------+--------------+------+------+------------+-------------+`
141			`\|select1/selectc/_and \| \| \| \| \| \|`
142			`\| 0000 \| Local\| \| 7 \| 0.120 \| 2.850 \|`
143			`+---------------------+--------------+------+------+------------+-------------+`
144
145			`* Net Skew is the difference between the minimum and maximum routing`
146			`only delays for the net. Note this is different from Clock Skew which`
147			`is reported in TRCE timing report. Clock Skew is the difference between`
148			`the minimum and maximum path delays which includes logic delays.`
149
150
151			`The Delay Summary Report`
152
153
154			`The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0`
155
156			`The AVERAGE CONNECTION DELAY for this design is: 2.120`
157			`The MAXIMUM PIN DELAY IS: 12.443`
158			`The AVERAGE CONNECTION DELAY on the 10 WORST NETS is: 9.291`
159
160			`Listing Pin Delays by value: (nsec)`
161
162			`d < 2.00 < d < 4.00 < d < 6.00 < d < 8.00 < d < 13.00 d >= 13.00`
163			`--------- --------- --------- --------- --------- ---------`
164			`15385 8001 2840 587 73 0`
165
166			`Timing Score: 0`
167
168			`Asterisk (*) preceding a constraint indicates it was not met.`
169			`This may be due to a setup or hold violation.`
170
171			`------------------------------------------------------------------------------------------------------`
172			`Constraint \| Requested \| Actual \| Logic \| Absolute \|Number of`
173			`\| \| \| Levels \| Slack \|errors`
174			`------------------------------------------------------------------------------------------------------`
175			`Autotimespec constraint for clock net clk \| N/A \| 23.680ns \| 3 \| N/A \| N/A`
176			`div<3> \| \| \| \| \|`
177			`------------------------------------------------------------------------------------------------------`
178			`Autotimespec constraint for clock net clo \| N/A \| 33.066ns \| 12 \| N/A \| N/A`
179			`ck_BUFGP \| \| \| \| \|`
180			`------------------------------------------------------------------------------------------------------`
181
182
183			`All constraints were met.`
184			`INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the`
185			`constraint does not cover any paths or that it has no requested value.`
186
187
188			`Generating Pad Report.`
189
190			`All signals are completely routed.`
191
192			`Total REAL time to PAR completion: 5 mins 25 secs`
193			`Total CPU time to PAR completion: 4 mins 42 secs`
194
195			`Peak Memory Usage: 263 MB`
196
197			`Placement: Completed - No errors found.`
198			`Routing: Completed - No errors found.`
199
200			`Number of error messages: 0`
201			`Number of warning messages: 2`
202			`Number of info messages: 1`
203
204			`Writing design to file testbench.ncd`
205
206
207
208			`PAR done!`