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[/] [cpu8080/] [trunk/] [project/] [testbench.stx] - Blame information for rev 9

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Line No. Rev Author Line
1 2 samiam9512 
Release 8.2.02i - xst I.33
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Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
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--> Parameter TMPDIR set to ./xst/projnav.tmp
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CPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s
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-->
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=========================================================================
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*                          HDL Compilation                              *
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=========================================================================
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Compiling verilog file "cpu8080.v" in library work
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Module  compiled
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Compiling verilog file "testbench.v" in library work
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Module  compiled
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Module  compiled
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Module
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Module  compiled
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Module  compiled
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Compiling verilog include file "test.lst"
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Module  compiled
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Module  compiled
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No errors in compilation
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Analysis of file <"testbench.prj"> succeeded.
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CPU : 0.16 / 0.37 s | Elapsed : 0.00 / 0.00 s
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-->
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28 9 samiam9512 
Total memory usage is 107620 kilobytes
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Number of errors   :    0 (   0 filtered)
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Number of warnings :    0 (   0 filtered)
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Number of infos    :    0 (   0 filtered)
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